JPH06232277A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device that requires fewer processes in manufacturing than a conventional one. CONSTITUTION:A first contact hole 7 is formed in an n-type diffusion layer 3. A silicon film 8 containing an n-type impurity is deposited thereon, and a coating film 9 is formed on the silicon film 8. After a second contact hole 11 is formed in a p-type diffusion layer 4, a silicon film 12 containing a p-type impurity is so formed that the silicon film 12 remains at least in the contact hole 11. A tungsten silicide film 13 is deposited all thereon. Then, a desired wiring pattern is formed in a lithographic step, and the connection through the direct contact is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a direct contact.

[0002]

2. Description of the Related Art In a recent LSI, a contact hole is formed in a part of an insulating film covering a source / drain region, and a polycrystalline silicon film containing a conductive impurity in the source / drain region is formed as a wiring. , A direct contact method for electrically connecting a source / drain region and a polycrystalline silicon film for wiring is used.

The wiring by the direct contact method can improve the step coverage in the step portion and the heat resistance.

At present, wiring is highly integrated, miniaturized, and multilayered, and there is a demand for the wiring to have improved step coverage and high heat resistance at the step portion. Therefore, 16
In the DRAM designs up to M, aluminum wiring has been used in the P-type region and direct contact has been exclusively used in the N-type region.

FIG. 5 shows a method of manufacturing a semiconductor device using a direct contact in an N-type region, for example. First, the N-type region 3 is formed on or in the surface of the semiconductor substrate 1 (FIG. 5A), the insulating film 5 is formed on the semiconductor substrate 1, and the mask pattern 6 is provided thereon ( 5 (b)), the insulating film 5 is etched using this mask pattern to form a contact hole on the N-type region 3 (FIG. 5 (c)).
Then, a polycrystalline silicon film 15 is deposited on the entire surface (see FIG.
(d)), phosphorus or arsenic is ion-implanted to form a polycrystalline silicon film 8 containing N-type impurities (FIG. 5 (e)).
). After that, a metal silicide film such as a tungsten silicide film 13 or a molybdenum silicide film is formed on the entire surface to connect the direct contacts (FIG. 5 (f)).
).

As described above, the direct contact is applied to the electrical connection between the regions of the same conductivity type. However, with higher integration and miniaturization of devices, it is indispensable to use the direct contact method for P-type regions as well, for example, in the design of DRAM of 64M or later, and therefore, direct contact between different conductivity type regions is required. There has been a need for a technique for forming contacts and enabling electrical connection.

However, in the conventional method, when ion implantation is performed to form different conductivity type regions, when one (eg N type) ion implantation is performed, the other (eg P type) is performed.
It is necessary to form a resist on the polycrystalline silicon film. Furthermore, here, in general, 2
A high dose amount of × 10 ¹⁶ ions / cm ² is required, but if this is injected once, curing of the resist occurs,
Since it becomes difficult to peel off the resist, it is necessary to divide the ion implantation into two times and to perform the implantation by 1 × 10 ¹⁶ ions / cm ² , which significantly increases the number of steps.

Further, if an attempt is made to form a direct contact by the conventional method using CVD, polycrystalline silicon containing N-type impurities and polycrystalline silicon containing P-type impurities are independently formed. After depositing the polycrystalline silicon containing the N-type impurities, and before depositing the polycrystalline silicon containing the P-type impurities, the polycrystalline silicon containing the N-type impurities is patterned to contain the N-type impurities. It is necessary to selectively cover with a pattern mask of crystalline silicon. Further, a step of removing the mask before depositing a refractory metal or the like on the polycrystalline silicon containing N-type impurities and the polycrystalline silicon containing P-type impurities, and patterning the polycrystalline silicon containing P-type impurities. -A process such as training is required. Therefore, as in the case of using the ion implantation method, the number of steps is significantly increased and becomes complicated.

As described above, when the direct contact is formed between the different conductivity type regions by the conventional technique, the number of steps is unavoidably increased.

[0010]

As described above, in the conventional manufacturing method, there is a problem in that direct contact with different conductivity type regions complicates the process. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a semiconductor device that solves the above-mentioned problems of the prior art and can reduce the number of steps.

[0011]

In order to solve the above-mentioned problems, a first aspect of the present invention is to form a first conductivity type region and a second conductivity type region on or in the surface of a semiconductor substrate,
Forming an insulating film on the semiconductor substrate and forming a first contact hole on the first conductivity type region of the insulating film; and forming a first contact hole on the insulating film so as to fill the first contact hole. A step of forming a first semiconductor film containing an impurity of one conductivity type, a mask pattern is provided on the first semiconductor film, and the first semiconductor film and the insulating film are etched using this pattern. A second on the second conductivity type region
Forming a contact hole, forming a second semiconductor film containing an impurity of the second conductivity type in at least the second contact hole, and from the surface of the first semiconductor film to the second semiconductor film. And a step of forming a film made of a metal or a silicide thereof so as to extend over the surface of the film.

Here, a second contact is formed in the second contact hole.
When forming the second semiconductor film containing conductivity type impurities, it is preferable that the second semiconductor film is formed on the entire surface and is left only in the second contact hole by etch back.

Preferably, an etching resistant film serving as a mask against the etch back of the second semiconductor film is formed on the first semiconductor film, and the etching resistant film is formed using the mask pattern. Good to etch.

Furthermore, preferably, the mask pattern is used as a resist and the pattern is peeled off before the second semiconductor film is formed.

The second aspect of the present invention is to provide a first conductivity type region and a second region.
Forming a conductivity type region on or in the surface of a semiconductor substrate; forming an insulating film on the semiconductor substrate; and forming a first contact hole on the first conductivity type region of the insulating film. A step of forming a first semiconductor film containing an impurity of the first conductivity type on the insulating film so as to fill the first contact hole, and a metal or a silicide thereof on the first semiconductor film. A step of forming a conductive film, a mask pattern is provided on the conductive film, and the conductive film, the first semiconductor film, and the insulating film are etched using the pattern, and the mask is formed on the second conductive type region. And a step of forming a second semiconductor film containing an impurity of the second conductivity type so as to fill the second contact hole. The manufacturing method of .

[0016]

According to the method of manufacturing the semiconductor device of the present invention,
The mask pattern provided on the first semiconductor film is commonly used to etch the first semiconductor film and the insulating film,
Since the second contact hole is formed and then the second semiconductor film is formed in this contact hole, the direct contact can be easily formed even in the P-type region and the number of steps can be reduced. A multilayer wiring structure can be realized without using aluminum wiring. In particular, when the second semiconductor film is left only in the second contact hole by etching, the second semiconductor film can be patterned without using a mask pattern. Can be significantly reduced. At this time, the mask pattern and the etching resistant film formed on the first semiconductor film are not covered by the second pattern.
It acts as an etching stop for the etching of the semiconductor film.

[0017]

Embodiments of the method of manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

Embodiment 1 FIGS. 1 and 2 are process sectional views showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

(Step A) First, a field oxide film 2 for element isolation is formed on a P-type silicon substrate 1. After that, an N-type diffusion layer (source / drain electrode) 3 having a thickness of 50 nm and a P-type diffusion layer (source / drain electrode) 4 having a thickness of 70 nm are formed.

Next, as an interlayer insulating film, a CVD (Chemic
A silicon oxide film or a silicon oxide film 5 containing impurities such as phosphorus and boron is deposited to a thickness of 1500 nm by the al Vapor Deposition method. After that, a resist pattern 6 is formed by the lithography method. And CH
F ₃ gas flow rate 70 SCCM, CF ₄ gas flow rate 60 SCCM, Ar
Reactive ion etching of the silicon oxide film 5 is performed using the resist pattern 6 as a mask under the conditions of a gas flow rate of 1000 SCCM and a pressure of 1.7 Torr. At this time, 750W for the electrode
Power is applied. By this etching, the first contact hole 7 is opened with a diameter of 600 nm to expose a part of the N-type diffusion layer 3 (FIG. 1 (a)).

(Step B) Next, a polycrystalline or amorphous silicon film 8 containing N type impurities such as phosphorus at 5 × 10 ²⁰ cm ^-3 is deposited on the entire surface of about 300 nm. After that, for example, oxidization is performed in an oxidizing atmosphere at 900 ° C.,
A thin thermal oxide film 9 having a thickness of about 30 nm is formed on the surface of the silicon film 8 (FIG. 1 (b)). At this point, the silicon film 8 and N
A direct contact with the mold diffusion layer 3 is formed. Instead of the thermal oxide film 9, a silicon film 8 which is a post-process is used.
If a film having etching resistance is formed in the etching process of the silicon oxide film 5 and the silicon oxide film 5, the resist pattern 6 is formed.
Even if the degenerate, the film acts as a mask, which is still preferable. For example, the silicon nitride film may be formed by thermal nitridation or CVD.

(Step C) Next, a resist pattern 10 is formed by a lithography method, and the resist pattern 10 is formed.
CHF ₃ gas flow rate 70 SCCM, CF ₄ gas flow rate 60 SCCM, Ar gas flow rate 1000 SCCM, pressure 1.
Reactive ion etching of the thermal oxide film 9 is performed under the condition of 7 Torr. At this time, a power of 750 W is applied to the electrodes. Further, the polycrystalline or amorphous silicon film 8 of 300 nm also has a Cl ₂ gas flow rate of 100 SCCM and a pressure of 75 mTor.
Reactive ion etching is performed under the condition of r using the resist pattern 10 and the thermal oxide film 9 as a mask. At this time, an electric power of 150 W is applied to the electrodes. When a film having etching resistance in etching the silicon film 8 and the silicon oxide film 5 is used instead of the thermal oxide film 9 in this step, the resist pattern 10 may be peeled off in advance and only this film may be used as a mask. good. afterwards,
Reactive ion etching is performed on the silicon oxide film 5 serving as the interlayer insulating film under the same conditions as when the thermal oxide film 9 was etched to form the second contact hole 11 having a diameter of 600 mm.
to expose a part of the P-type diffusion layer 4 (FIG. 1).
(c)). Then, the resist pattern 10 is removed by plasma ashing or the like.

(Step D) Next, a polycrystalline or amorphous silicon film 12 containing P type impurities such as boron at 5 × 10 ²⁰ cm ^-3 is deposited to a thickness of 400 nm on the entire surface (FIG. 1 (d)). ).

(Step E) After that, a Cl ₂ gas flow rate of 10
Etchback is performed on the entire surface of the silicon film 12 by anisotropic reactive ion etching under the conditions of 0 SCCM and a pressure of 75 mTorr. At this time, an electric power of 150 W is applied to the electrodes. At this time, the thin thermal oxide film 9 having a thickness of 30 nm serves as a stopper for etching back (FIG. 1 (e)). Also, when the above-described silicon nitride film or the like is used instead of the thermal oxide film 9,
This film can be used as a stopper for etch back.

Here, as shown in FIG. 1 (e), the etched back silicon film 12 containing P-type impurities is N
It is not in contact with the silicon film 8 containing the type impurities. However, they may be in contact as shown in FIG.

(Step F) Next, the 30 nm thin thermal oxide film 9 is removed by etching with a solution containing HF,
A 300 nm thick tungsten silicide film 13 is deposited on the entire surface by sputtering (FIG. 1 (f)).

(Step G) After that, a desired wiring pattern is formed by a lithography method, and heat treatment is performed at about 900 ° C. to connect the direct contacts. The order of the wiring patterning step and the heat treatment step may be reversed. This makes it possible to obtain a good ohmic contact and also a good step coverage, so that a device having good characteristics can be obtained even with miniaturization.

In this embodiment, a thin thermal oxide film 9 having a thickness of 30 nm is used.
Was formed by the oxidation method, but the same effect can be obtained by forming it by the CVD method.

Example 2 In the first example, the thermal oxide film 9 was peeled off by etching after the step E was carried out. However, in this example, the thermal oxide film 9 was peeled off. The film 13 is deposited on the entire surface (FIG. 3).

After that, a desired wiring pattern is formed by a lithography method, and heat treatment is performed at about 900 ° C. to connect the dilent contacts. Also by this method, good ohmic contact can be obtained, and step coverage is also good, so that a device having good characteristics can be obtained. Further, there is an effect that the total number of steps is reduced as compared with the first embodiment.

Embodiment 3 FIGS. 4A to 4C are process cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device according to the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

Step A was carried out in the same manner as in the first embodiment (FIG. 4 (a)). After that, an N-type impurity such as phosphorus is added to 5 × 1.
A polycrystalline or amorphous silicon film 8 containing 0 ²⁰ cm ^-3 is deposited on the entire surface of about 300 nm. Then, a tungsten or tungsten alloy thin film 14 having a thickness of about 200 nm is formed by the CVD method or the sputter deposition method (FIG. 4 (b)).
). At this point, direct contact between the polycrystalline or amorphous silicon film 8 and the N-type diffusion layer 3 is formed.

Next, a resist pattern 10 is formed on the P-type diffusion layer 4 by a lithography method, and using this resist pattern 10 as a mask, Cl ₂ gas flow rate is 5 SCCM, BCl ₃
Gas flow rate 30 SCCM, N ₂ gas flow rate 200 SCCM, CCl ₄
The reactive ion etching of the tungsten or tungsten alloy thin film 14 is performed under the conditions of a gas flow rate of 35 SCCM and a pressure of 150 mTorr. At this time, a power of 240 W is applied to the electrodes. Further, the polycrystalline or amorphous silicon film 8 of 300 nm is also subjected to reactive ion etching under the conditions of Cl ₂ gas flow rate of 100 SCCM and pressure of 75 mTorr using the resist pattern 10 as a mask,
A second contact hole 11 having a diameter of 600 nm is formed, and P
A part of the mold diffusion layer 4 is exposed (FIG. 4 (c)). At this time, an electric power of 150 W is applied to the electrodes. Then, the resist pattern 10 is removed by plasma ashing or the like.

Next, a P-type impurity such as boron is added to 5 ×.
A polycrystalline or amorphous silicon film 12 containing 10 ²⁰ cm ^-3 is deposited to a thickness of 400 nm (FIG. 4 (d)).
Then, the reactive ion etching of the silicon film 12 is performed under the conditions of a Cl ₂ gas flow rate of 100 SCCM and a pressure of 75 mTorr. At this time, a power of 150 W is applied to the electrodes. This reactive ion etching is performed until the surface of the tungsten or tungsten alloy thin film 14 is exposed, and as a result, the surface of the thin film 14 and the silicon film 12 are exposed.
The surface is almost in the same plane (Fig. 4 (e)).

Thereafter, as in the first embodiment, a desired wiring pattern is formed by the lithography method, and heat treatment is performed at about 900 ° C. to connect the direct contacts. This makes it possible to obtain a good ohmic contact and also a good step coverage, so that a device having good characteristics can be obtained even with miniaturization.

In this embodiment, the etch back step is performed as shown in FIG. 4 (e), but this step can be omitted. In this case, the number of steps should be reduced. You can

Further, although the tungsten or tungsten alloy thin film is used as the conductive film in the first to third embodiments, a refractory metal such as titanium or molybdenum or a silicide thereof such as TiSi ₂ or MoSi _{2 is used.} Etc. may be used.

Further, in the above embodiment, the different conductivity type regions are the source / drain regions, but the present invention is not limited to this, and the gate electrodes or other electrode wirings may be used.

Furthermore, as a method for selectively forming a silicon film in the contact hole, a selective CVD method, a lift-off method, or the like can be used instead of the etchback method.

Furthermore, although the silicon film is used as the semiconductor film, another semiconductor film made of a compound semiconductor or the like may be used.

In addition, various modifications can be made without departing from the scope of the present invention.

[0042]

As described above, according to the method of manufacturing a semiconductor device of the present invention, direct contacts to different conductivity type regions can be formed in a small number of steps, which is extremely useful in practice. A method for manufacturing a semiconductor device can be provided.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a process sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention.

3A to 3C are process cross-sectional views showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a process sectional view showing an embodiment of the method for manufacturing a semiconductor device of the present invention.

5A to 5C are process sectional views showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1 Silicon substrate 2 Field oxide film 3 N-type diffusion layer 4 P-type diffusion layer 5 Interlayer insulating film 6,10 Resist pattern 7,11 Contact hole 8 Polycrystalline or amorphous silicon film containing N-type impurities 9 Thermal oxide film 12 P-type Polycrystalline or amorphous silicon film containing impurities 13 Tungsten silicide film 14 Tungsten or tungsten alloy thin film 15 Polycrystalline silicon film

Claims (5)

[Claims] 1. A step of forming a first conductivity type region and a second conductivity type region on or in a surface of a semiconductor substrate, and forming an insulating film on the semiconductor substrate, wherein the first conductivity type of the insulating film is formed. Forming a first contact hole on the region; forming a first semiconductor film containing an impurity of the first conductivity type on the insulating film so as to fill the first contact hole; By providing a mask pattern on the semiconductor film of 1,
Etching the first semiconductor film and the insulating film using this pattern to form a second contact hole on the second conductive type region; and a second conductive hole at least in the second contact hole. A step of forming a second semiconductor film containing a second type impurity, and the step of forming a second semiconductor film from the surface of the first semiconductor film.
And a step of forming a film made of a metal or a silicide thereof so as to extend over the surface of the semiconductor film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second semiconductor film is formed on the entire surface and is left only in the second contact hole by etching. 3. An etching resistant film serving as a mask for etching the second semiconductor film is formed on the first semiconductor film, and the etching resistant film is etched using the mask pattern. The method for manufacturing a semiconductor device according to claim 2, wherein 4. The method of manufacturing a semiconductor device according to claim 1, wherein the mask pattern is made of a resist, and the pattern is peeled off before forming the second semiconductor film. 5. A step of forming a first conductivity type region and a second conductivity type region on or in a surface of a semiconductor substrate, and an insulating film is formed on the semiconductor substrate, and the first conductivity type of the insulating film is formed. Forming a first contact hole on the region; forming a first semiconductor film containing an impurity of the first conductivity type on the insulating film so as to fill the first contact hole; Forming a conductive film made of a metal or a silicide thereof on the first semiconductor film, providing a mask pattern on the conductive film, and using the pattern, the conductive film, the first semiconductor film, and the insulating film Etching each,
The method includes the steps of forming a second contact hole on the second conductivity type region, and forming a second semiconductor film containing a second conductivity type impurity so as to fill the second contact hole. A method of manufacturing a semiconductor device, comprising: