JPH06232173A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize high performance and high level integration, by reducing the interval between the gate electrode and the source electrode in a field effect transistor having a self-aligned gate electrode. CONSTITUTION:A gate part composed of a temporary gate electrode 3b and an insulating film 4a and a plated metal film 10 on the electrode 3b is formed on a semiinsulative GaAs substrate 1. A source-drain region 11 is formed by ion implantation using the gate part as a mask. Source-drain electrode material is evaporated by using the gate part as a mask. A source-drain ohmic electrode 13a is formed by a lift-off process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a field effect transistor having a self-aligned gate electrode.

[0002]

2. Description of the Related Art Conventionally, field effect transistors have been
There is a field effect transistor made of gallium arsenide having a self-aligned structure in which the gate electrode and the source / drain regions are positioned by self-alignment. In such a transistor, in order to improve its characteristics, especially the gate electrode is Short gate length,
It is required that the gate electrode has a structure in which the distance to the source electrode is short and that the gate electrode has low resistance.

FIG. 4 is a diagram for explaining a conventional method of forming a self-aligned field effect transistor. In the figure, 1 is a semi-insulating GaAs substrate and 2 is n-GaAs formed on the substrate 1. The active layer 3 is WSi or WSiN for forming the gate electrode 3a on the active layer 2.
A film, 6a is a resist mask for patterning the WSi or WSiN film, and 11 is n ⁺ -Ga formed on both sides of the gate electrode 3a to serve as source and drain regions.
As active layer, 12 is a resist mask for ion implantation for forming the n ⁺ -GaAs active layer 11 by ion implantation, 13a is a source / drain electrode formed on the source / drain regions, 14 is the source, It is a resist mask for forming the drain electrode 13a.

Next, a method of manufacturing the GaAs field effect transistor will be described. First, as shown in FIG. 4 (a), an n-GaAs active layer 2 having a thickness of 600 angstroms or less is formed on a semi-insulating GaAs substrate 1, and a gate electrode material 3 such as WSi or WSiN is further formed thereon. Sputter formation.

Next, a resist film 6a having a pattern width of about 0.35 μm to 1 μm is formed on the gate electrode material 3 by photolithography, and the gate electrode material 3 is patterned by performing etching such as RIE using this as a mask. To form the gate electrode 3a (FIG. 2 (b)).

Thereafter, by photolithography, a resist film 12 serving as a mask at the time of ion implantation for forming the source and drain regions is formed together with the gate electrode 3a, and then ion implantation is performed on the entire surface to form the gate electrode 3 described above.
n ⁺ -GaAs to be source and drain regions on both sides of a
The active layer 11 is formed. At this time, the depth of the active layer 11 is about 1000 to 2000 angstroms (FIG. 4 (c)).

After removing the unnecessary resist film 12, a resist mask 14 for forming source and drain electrodes is newly formed by photolithography (FIG. 4 (d)).
), And then the source and drain electrodes 13a are formed by vapor deposition and lift-off of the electrode material on the entire surface to obtain the self-aligned field effect transistor 200 (FIG.
(e)).

[0008]

However, in the conventional method for manufacturing a field effect transistor having a self-aligned gate electrode, when the source / drain electrode 13a is formed, the gate electrode 3a is also formed by the resist mask 14 for electrode formation. Need to cover.

At this time, the exposure mask for forming the resist mask 14 is superposed on the gate electrode 3a to determine the formation position of the source / drain electrode 13a, so that an overlapping margin is required and the gate electrode 3a is required. There is a problem in that the distance between the source electrode 13a and the source electrode 13a cannot be shortened, and the degree of integration cannot be improved.

An edge type phase shift mask may be used to form a fine gate. In this mask, an unnecessary pattern is generated at the same time when the resist film is patterned. Therefore, an erasing step of an unnecessary portion is required. Not only the process becomes complicated, but also a necessary pattern cannot be arranged in a portion where an unnecessary pattern is formed, which is a problem in improving the degree of integration.

The present invention has been made to solve the above problems, and eliminates the need for pattern overlapping of source and drain electrodes with respect to the gate electrode of a self-aligned field effect transistor, thereby eliminating the need for gate electrode and source electrode. It is an object of the present invention to obtain a method for manufacturing a semiconductor device in which the separation distance can be easily narrowed and thereby the degree of integration can be improved.

Further, according to the present invention, an unnecessary pattern erasing step in the case of using the edge type phase shift mask can be omitted, and the miniaturization of the pattern and the improvement of the degree of integration can be achieved easily and stably. An object of the present invention is to obtain a method of manufacturing a semiconductor device that can be manufactured.

[0013]

According to a method of manufacturing a semiconductor device according to the present invention, a gate electrode material, an insulating film serving as an etching mask, and a metal film are formed on a semiconductor substrate, and then a gate electrode forming region is formed thereon. A resist mask having a fringed linear pattern is formed, the metal film and the insulating film are selectively etched using the resist mask, and then a portion of the gate electrode material other than the gate electrode formation region is covered with the resist. Forming a plating metal layer on the gate electrode material in the gate electrode forming region by electrolytic plating, and using the plating metal layer, the metal film and the insulating film as a mask, ion implantation for forming source and drain regions, and source , The drain electrode material is vapor-deposited and lift-off is performed.

Further, according to the present invention, in the method for manufacturing a semiconductor device, a resist mask having a linear pattern that borders the gate electrode formation region is formed by exposing and developing a resist film using an edge type phase shift mask. It is a thing.

[0015]

In the present invention, after the gate electrode is formed, the source and drain diffusion regions are formed by ion implantation using the gate electrode as a mask, and further the source and drain electrode materials are vapor-deposited and lifted off using the gate electrode as a mask. As a result, the source and drain ohmic electrodes are formed, so that it is not necessary to overlap the mask pattern for forming the source and drain electrodes with the gate electrode, and by reducing the overlapping margin, the gate electrode and the source electrode can be reduced. The separation distance can be narrowed, so that the transistor characteristics such as mutual conductance can be greatly improved, and the degree of integration can be improved.

Further, in the present invention, since the resist film is patterned by the edge type phase shift mask so that the resist pattern becomes a linear pattern that outlines the outer shape of the gate electrode, the resist film pattern is entirely gated. It will be effectively used for the formation of electrodes,
An unnecessary pattern erasing step that occurs when the edge type phase shift mask is used can be omitted, and thus the miniaturization of the pattern and the improvement of the degree of integration can be easily and stably achieved.

[0017]

EXAMPLES Example 1. 1 to 3 are sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of main steps. FIG. 1 shows a resist pattern for edging the outer shape of a gate electrode by an edge type phase shift mask. 2A and 2B are explanatory diagrams of a forming process, FIG. 2 is an explanatory diagram of a process of forming a gate electrode and source / drain regions, and FIG. In the figure,
1 is a semi-insulating GaAs substrate, 2 is an n-GaAs active layer formed on the GaAs substrate 1, 3 is a gate electrode material formed on the active layer 2, and 4 is formed on the gate electrode material 3. An insulating film 5 such as a SiO2 film is a metal film formed on the insulating film 4, and here, the metal film 5 has a lower side M.
Although it has a two-layer structure in which the o layer and the upper side are Au layers, the metal film may be made of only Mo or Au. 6b is a resist mask formed by photolithography using the edge type phase shift mask 7 (first
Resist film), which has a linear pattern that surrounds the periphery of the gate electrode formation region. Reference numerals 4a and 5a denote a mask insulating film and a mask metal, respectively, which are formed by selectively etching the insulating film 4 and the metal film 5 using the resist mask 6b and serve as a mask when the gate electrode material 3 is etched. It is a film.

Reference numeral 8 is a resist mask 8 for plating when selective plating is performed on the gate electrode material 3 in the gate electrode forming region.
A second resist film for forming b, 9 is an exposure mask for the resist film 8, and 10 is a plated metal layer formed on the gate electrode material 3 by selective plating. Also 3b
Is a temporary gate electrode formed by etching the gate electrode material 3 using the mask insulating film 4a and the mask metal film 5a as a mask, and 11 is selective ion implantation on both sides of the temporary gate electrode 3b. And the n ⁺ -GaAs active region formed by the annealing treatment, which becomes the source and drain regions. Reference numeral 12 denotes a third resist film which serves as an ion implantation mask together with the mask insulating film 4a and the mask metal film 5a during the selective ion implantation.
Reference numeral 3a denotes a source / drain ohmic electrode formed on the source / drain region 11 by vapor deposition of the source / drain electrode material 13 and lift-off, and 3c etches the temporary gate electrode 3b using the plated metal layer as a mask. The gate electrode is formed by.

Next, the manufacturing method will be described. Figure 1 (a)
On the semi-insulating GaAs substrate 1 as shown in FIG.
The s active layer 2 is formed to a thickness of 600 angstroms or less, and the gate electrode material 3 is formed on the s active layer 2 by sputtering WSi or WSiN.
An O2 film 4 and a Mo / Au metal film 5 are formed.

Next, after a resist film 6 is formed by coating on the metal film 5, an edge type phase shift mask 7 is arranged at a predetermined position on the resist film 6 (FIG. 1 (b)), and then the resist is continuously formed. The film 6 is exposed and developed by photolithography to form a resist film 6b having a linear pattern that outlines the outer shape of the gate electrode (FIG. 1 (c)).

After that, the Mo / Au metal film 5 and the SiO2 film 4 are etched by RIE or the like using the resist film 6b as a mask to selectively expose the gate electrode material 3. At this time, the metal film 5 is patterned so that it slightly protrudes from the resist film 6b in an eaves shape, and the SiO2 film 4 is patterned so as to have a pattern corresponding to the resist film 6b (FIG. 1 (d)).
).

Next, as shown in FIG. 2 (a), after removing the resist film 6b, the resist film 8 is again formed on the gate electrode material 3 and the metal film 5a patterned in the eaves shape is not buried. To form a coating. Then, a resist opening 8a is formed in the gate electrode formation region surrounded by the patterned SiO2 film 4a by photolithography using the exposure mask 9 (FIG. 2 (b)), and then the gate electrode material 3 is fed. Au by layer electroplating
Etc. are plated and grown to form a plated metal layer 10 (FIG. 2 (c)).

After the plating growth, the unnecessary resist mask 8b is removed, and the gate electrode material 3 is selectively removed by etching using the SiO2 film 4a and the plated metal layer 10 as a mask. After that, a resist mask 12 for forming an ohmic electrode is formed by photolithography, and ion implantation is performed using the resist mask 12 and the SiO2 film 4a and the plated metal layer 10 as masks, and then annealing is performed to form source and drain regions. ⁺
-A GaAs active layer 11 is formed (FIG. 2 (d)).

Further, as shown in FIGS. 3 (a) and 3 (b), source / drain electrode material 13 is vapor-deposited on the entire surface, and unnecessary vapor-deposited metal deposited on the resist mask 12 is removed by a lift-off method to remove the source. , The drain ohmic electrode 13a is formed.

Next, the patterned temporary gate electrode 3 is formed.
The unnecessary SiO2 film 4a on the surface b is removed with a hydrofluoric acid aqueous solution, and unnecessary source and drain electrode materials adhering to the side walls and the surface of the SiO2 film 4a are lifted off (FIG. 3 (c)).

Finally, the temporary gate electrode 3b is again RI
Etching with E etc., self-aligned gate electrode 3
A field effect transistor 101 having c is obtained (FIG.
(d)).

As described above, in this embodiment, after the gate electrode material 3 is patterned, the n ⁺ -GaAs active layer 11 is formed by ion implantation using the gate electrode material 3 as a mask, and the patterned temporary gate electrode 3b is formed. Since the source / drain ohmic electrode 13a is formed by vapor deposition and lift-off of the source / drain electrode material used as a mask, the distance between the gate electrode 3c and the source electrode 13a can be narrowed, which allows a transistor such as mutual conductance. It is possible to improve the characteristics and the degree of integration.

Further, since the resist film 6 is patterned by the edge type phase shift mask 7 so that the resist pattern becomes a linear pattern which borders the outer shape of the gate electrode 3c, the resist film 6b is entirely patterned. 3c is effectively used, and an unnecessary pattern erasing step that occurs when an edge type phase shift mask is used can be omitted, which facilitates miniaturization of the pattern and improvement of the integration degree. And it can be achieved stably.

[0029]

As described above, according to the method of manufacturing a semiconductor device of the present invention, after forming the gate electrode, the source and drain diffusion regions are formed using the gate electrode as a mask,
Further, since the source and drain ohmic electrodes are formed by using the gate electrode as a mask, it is not necessary to overlay the mask pattern for forming the source and drain electrodes on the gate electrode, and the overlay margin can be reduced. The distance between the gate electrode and the source electrode can be narrowed, which has the effect of significantly improving the transistor characteristics and improving the degree of integration.

Further, according to the present invention, in the method for manufacturing a semiconductor device described above, the resist film is patterned by the edge type phase shift mask so that the resist pattern becomes a linear pattern that outlines the outer shape of the gate electrode.
All the patterns of the resist film are effectively used, and the unnecessary pattern erasing step that occurs when using the edge type phase shift mask can be omitted,
As a result, there is an effect that further miniaturization of the pattern and higher integration can be achieved easily and stably.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a patterning process using an edge type phase shift mask in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a step of forming a gate electrode and source / drain regions in the method of manufacturing a semiconductor device.

FIG. 3 is a cross-sectional view for explaining a step of forming source and drain electrodes in the method of manufacturing the semiconductor device.

FIG. 4 is a cross-sectional view for explaining a method for manufacturing a conventional field effect transistor having a self-aligned structure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semi-insulating GaAs substrate 2 n-GaAs active layer 3 Gate electrode material 3b Temporary gate electrode 3c Gate electrode 4 SiO2 film 4a Patterned SiO2 film 5 Mo / Au metal film 6,8,12 Resist film 6a, 8a Resist Mask 7 Edge type phase shift mask 9 Exposure mask 10 Plating metal layer 11 n ⁺ -GaAs active layer (source / drain region) 13 Ohmic electrode material 13a Source / drain electrode

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device for manufacturing a field effect transistor having a self-aligned gate electrode, comprising the steps of forming a gate electrode material on a semiconductor substrate and patterning the material to form a gate electrode, A step of forming a resist film having a predetermined opening pattern on a semiconductor substrate and forming a mask layer formed of the resist film and the gate electrode and having openings at portions corresponding to source and drain electrode formation regions; A step of forming a source / drain diffusion region by selective ion implantation using a layer, and then a source / drain electrode material is entirely vapor-deposited, and the source / drain electrode material is lifted off by removing the resist film. And a step of forming a drain electrode, the method of manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the gate electrode, a resist film is formed on the gate electrode material, and the resist film is exposed using an edge type phase shift mask. A method for manufacturing a semiconductor device, comprising: developing to form a resist mask having a linear pattern that surrounds the periphery of the gate electrode formation region, and patterning the gate electrode material using the resist mask. 3. A method of manufacturing a semiconductor device for forming a field effect transistor having a self-aligned gate electrode, the method comprising: forming a gate electrode material on a semiconductor substrate having an n-type semiconductor layer formed on the surface thereof; After sequentially forming an insulating film and a metal film on the gate electrode material, a first resist film having a linear pattern that borders the periphery of the gate electrode formation region is formed by photolithography using an edge type phase shift mask. And a step of etching the insulating film and the metal film by an anisotropic etching process using the first resist film as a mask so that the metal film has an eaves-like cross-sectional shape protruding to both sides of the resist film. After removing the first resist film, a resist is applied on the exposed gate electrode material, and the photolithography is applied to the resist. Forming a second resist film having an opening in the gate electrode formation region, and forming a plated metal layer by electrolytic plating using the gate electrode material exposed in the opening of the second resist film as a power supply layer And a step of selectively etching the gate electrode material using the insulating film and the plated metal layer as a mask after removing the second resist film, and opening the source and drain electrode formation regions by photolithography. Forming a third resist film having: and performing selective ion implantation using the third resist film, the insulating film and the plated metal layer as a mask, and annealing treatment to form source and drain diffusion regions The source and drain electrode materials are entirely vapor-deposited, and the source and drain electrodes are lifted off by removing the third resist film. And a step of lifting off the source / drain electrode material adhered to the sidewall and surface of the insulating film by removing the insulating film, and anisotropically etching the gate electrode material again using the plated metal layer as a mask. A step of forming the gate electrode to form a gate electrode.