JPH06232168A - Field effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide the structure and the manufacturing method wherein an FET capable of very high speed operation is manufactured in a self-alignment manner. CONSTITUTION:An active layer 2 composed of GaAs containing impurities is formed on a GaAs semiconductor substrate 1. A contact layer 3 which contains high concentration impurities or consists of semiconductor material of low energy gap is formed on the active layer 2. An insulating film 4 is formed on the contact layer 3. By using the same mask composed of resist 5, the insulatig film 4 is selectively eliminated, and each of the electrode regions of gate-source-drain is opened. The contact layer 3 of a gate electrode region is eliminated, and a part of the active layer 2 is exposed. After that, electrode metal is formed on the whole surface on the insulating film 4. The electrode metal is selectively eliminated, and electrically isolated so as to form each of the electrodes of gate-source-drain.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (FET) having a fine gate length and a method for manufacturing the same.

[0002]

2. Description of the Related Art When the gate length of an FET becomes extremely short to about 0.5 μm or less, the intrinsic transconductance g _mo actually observed in the FET increases, but the source resistance Rs hardly changes. Therefore, the effective transconductance g _msat ′ (= g _mo / (1 + Rs · g _mo )) becomes low. Therefore, when the gate length becomes extremely short, the performance deterioration of the FET becomes remarkable. Source resistance Rs due to many surface states
When a FET having a short gate length is formed by using a GaAs material having a large value, the performance of the FET is deteriorated. In order to prevent this performance deterioration, a method of forming the high concentration layers (n ⁺ regions) of the source region and the drain region in a self-aligned manner with the gate electrode is used. For example, an n ⁺ region is formed in a self-aligned manner by forming a SiO ₂ film on the side wall of the gate electrode and ion-implanting impurities into the semiconductor substrate using the gate electrode and the SiO ₂ film as a mask. A method of manufacturing such an FET is described in, for example, 8 of the following document.
It is disclosed on pages 2-85, the distance between the gate electrode and the source region is shortened, and the source resistance Rs is reduced.

1985 IEEE IEDM “A HIGH TRANSCONDUCTA
NCE GaAs MESFET WITH REDUCED SHORT CHANNEL EFFECT
Further, in order to further reduce the source resistance Rs, a method of forming an ohmic electrode in a self-aligned manner with a gate electrode has been devised, and is disclosed on pages 542 to 544 of the following document.

IEEE ELECTRON DEVICE LETTERS, VOL.EDL-
6.NO.10, OCTOBER 1985 `` A New Self-Aligned GaAs FET
With A Mo / WSix T-Gate ”In the method of manufacturing the FET shown in the same document, Mo / W
Using the T-shaped gate made of Six as a mask, n ⁺ impurities are implanted into the semi-insulating GaAs semiconductor substrate to form the n ⁺ region in a self-aligned manner. Further, ohmic metal is formed in a self-aligned manner using this T-shaped gate as a mask. This FE
According to the manufacturing method of T, not only the n ⁺ region but also the ohmic electrode is formed close to the gate electrode, so that the source resistance Rs is further reduced and the effective transconductance g is reduced.
_msat 'becomes high.

[0005]

In the above-mentioned conventional FET manufacturing method in which the ohmic electrode is formed in a self-aligned manner, after the gate electrode is formed, the source electrode and the drain electrode are formed using this gate electrode as a mask. It AuGe / Ni alloy is used for ohmic electrode material,
An alloying treatment at a high temperature near 400 ° C is required. Therefore, the gate electrode material formed before the ohmic electrode is formed is required to have heat resistance that can withstand this alloying treatment. However, when the gate electrode is formed using a material having high heat resistance, the gate resistance is generally high.
Further, in the FET using the AuGe / Ni alloy as the gate electrode material, the resistance component of the gate electrode increases when used in a high temperature environment. Therefore, the conventional FET manufacturing method described above in which the ohmic electrode is formed in self-alignment with the gate electrode is not optimal.

Further, in the conventional FET manufacturing method in which the source / drain regions are formed in a self-aligned manner with respect to the gate electrode, ion implantation is performed on the substrate using the gate electrode as a mask, and the low resistance source / drain is formed. A region is formed. Therefore, when the gate length is shortened, the ion-implanted layers forming the source / drain regions come close to each other under the channel layer, and a leak current easily flows. Therefore, when the gate length is shortened, the threshold voltage of the FET shifts to the negative side, a short channel effect appears, and improvement of the FET characteristics is hindered.

[0007]

The present invention has been made in order to solve such a problem, and includes a step of forming an active layer on a semiconductor substrate, a semiconductor material containing impurities at a high concentration or a low energy gap. A step of forming a contact layer made of a semiconductor material on the active layer, a step of forming an insulating film on this contact layer, and a step of selectively removing this insulating film using the same mask to remove the gate, source and drain. Opening each electrode region, removing the contact layer in the gate electrode region to expose the active layer, forming an electrode metal on the insulating film, and selectively removing the electrode metal on the insulating film And a step of electrically separating the electrode metal into respective electrodes of the gate, the source and the drain to manufacture the FET.

An active layer formed on the semiconductor substrate,
A contact layer formed on the active layer, which is made of a semiconductor material containing a high concentration of impurities or a semiconductor material having a low energy gap, and insulation in which the gate, source, and drain electrode regions formed on the contact layer are opened. From the same electrode material as the film, the gate electrode in contact with the active layer exposed by removing the contact layer in the gate electrode region, and the gate electrode formed in contact with the contact layer exposed in each of the source and drain electrode regions The FET is configured by including the source electrode and the drain electrode.

[0009]

The electrode patterns of the source, drain and gate are simultaneously formed on the insulating film on the contact layer using the same mask, and these electrodes are formed in self-alignment with the insulating film. Therefore, the distance between the electrodes is reduced to a length determined by the limit of exposure resolution when patterning the insulating film.

Further, the source and drain electrodes make ohmic contact with the contact layer containing a high concentration of impurities or having a low energy gap without alloying treatment. Therefore, the selection range of the gate electrode material is widened, and the electrode material having low heat resistance is also selected.

Further, the source / drain regions are formed by selectively removing the contact layer, and it is not necessary to perform ion implantation as in the conventional case. Therefore, the source / drain regions do not approach each other below the channel layer as in the conventional case.

[0012]

1 to 3 show an ME according to an embodiment of the present invention.
FIG. 6 is a process cross-sectional view showing the method of manufacturing the SFET.

First, G is grown on the semi-insulating GaAs semiconductor substrate 1 by a crystal growth method such as a molecular beam epitaxy method.
The aAs layer is crystal-grown to form the active layer 2. This active layer 2 contains n type impurities such as Si and Se at 5 × 10 ¹⁷ / c.
It is formed in a thickness of 1000 angstrom including the concentration of m ³ . Next, a contact layer 3 having a thickness of 500 angstrom is formed on the active layer 2 (see FIG. 1).
(See (a)). The contact layer 3 is formed of Ge containing impurities such as As in a high concentration of about 10 ²⁰ / cm ³ . In addition, the contact layer 3 may be formed of a material having a low energy gap, such as In _x Ga _1-x As. In addition, the In _x Ga _1-x As semiconductor material contains Si
It may be formed by including impurities such as.

Next, an insulating film 4 made of SiO ₂ , SiN or the like is formed on the entire surface of the wafer on the contact layer 3 by the PCVD method (see FIG. 2B). The thickness of this insulating film 4 is set to 5000 angstroms.

Next, a resist 5 is applied on the insulating film 4. The resist 5 is exposed / developed by a lithographic technique, and patterned into a shape in which each electrode region of the gate / source / drain is opened (FIG. 7C).
reference). In the current optical exposure technology, the length a of the gate electrode opening can be shortened to 0.35 μm, and the distance between the source electrode opening and the gate electrode opening, that is, between the source and gate electrodes The distance b and the distance between the drain electrode opening and the gate electrode opening, that is, the distance c between the drain and gate electrodes can be shortened to 0.35 μm.

Next, this patterned resist 5 is used.
The insulating film 4 is etched using the mask as a mask. By this etching, the insulating film 4 in each electrode forming region of the gate, source and drain is selectively removed, and the contact layer 3 is partially exposed (see FIG. 3D). As a result, the gate
Each source / drain electrode pattern is formed on this one insulating film 4.

Next, a resist 6 is applied on the patterned insulating film 4 to form a resist pattern which partially overlaps the insulating film 4 forming the gate electrode opening. Then, etching is performed by using the patterned resist 6 as a mask to selectively remove the contact layer 3 opening in the resist pattern to expose the active layer 2 in the gate electrode region. At this time, the contact layer 3 is slightly side-etched so that the gate metal formed in a later step and the contact layer 3 do not come into electrical contact with each other (see FIG. 2E).

Next, the resist 6 on the insulating film 4 is removed (see (f) in the same figure), and the electrode metal 7 is vapor-deposited on the entire surface of the wafer on the patterned insulating film 4 (see (g) in the same figure). ). The electrode metal 7 is composed of Ti / Pt / Au metal 30
It is formed to have a thickness of 0/400/3000 angstroms.

Next, a resist 8 is applied to the entire surface of the wafer to flatten the surface of the substrate, and subsequently the entire surface of the wafer is etched back (see FIG. 6 (h)). This etch back is performed up to the surface of the insulating film 4 shown by the dotted line.

Next, the electrode metal 7 exposed on each insulating film 4
Are selectively removed by ion milling, and the electrode metal 7 is electrically separated into source, drain and gate electrodes. As a result, the gate electrode 7a that is in Schottky contact with the active layer 2 is formed, and the source electrode 7b and the drain electrode 7c that are in ohmic contact are formed in the contact layer 3 to complete the MESFET (see FIG. 3).

As described above, according to this embodiment, the source, drain and gate electrode patterns are simultaneously formed on one insulating film 4 by using the same mask made of the resist 5. The gate electrode 7a, the source electrode 7b and the drain electrode 7c are formed in self-alignment with the insulating film 4. Therefore, the distance between electrodes c and d (Fig. 1 (c)
(See) is shortened to a length determined by the limit of exposure resolution when forming the resist 5 for patterning the insulating film 4, for example, 0.35 μm. Therefore, the distance between the gate and the source is extremely short, and the source resistance R
s is significantly reduced and effective transconductance g
_msat 'becomes high.

Further, the source electrode 7b and the drain electrode 7c are not subjected to alloying treatment, and Ge containing a high concentration of impurities or In _x Ga having a low energy gap is used.
_It makes ohmic contact with the contact layer 3 made of _1-x As. As described above, the alloying is not necessary because the width of the barrier formed between the ohmic electrode and the contact layer 3 becomes thin when the impurity concentration of the contact layer 3 is high, and carriers pass through this barrier due to the tunnel effect. This is because
Further, when the energy gap of the contact layer 3 is low, the height of the barrier formed between the ohmic electrode and the contact layer 3 becomes low, and the carriers easily get over this barrier. As a result of eliminating the need for alloying, the selection range of the gate electrode material is widened, and the electrode material having low heat resistance is also selected. Therefore, the same material can be used for the ohmic electrode and the gate electrode, and each electrode is simultaneously formed in self-alignment with the insulating film 4 as in the present embodiment. That is, each electrode is easily and accurately formed.

Further, the source region and the drain region are formed by selectively removing the contact layer 3, and it is not necessary to perform ion implantation as in the conventional case. Therefore, the high-concentration regions of the source and drain do not come close to each other under the channel layer as in the conventional case. For this reason,
A leak current is less likely to occur between the source and drain regions, the short channel effect is suppressed, and the characteristics are improved even in an FET having a short gate length.

[0024]

As described above, according to the present invention, the source, drain and gate electrode patterns are simultaneously formed by using the same mask. Therefore, the distance between the electrodes is reduced to a length determined by the limit of exposure resolution. Therefore, the source resistance is remarkably reduced, the effective transconductance is increased, and an FET suitable for ultrahigh-speed operation is provided.

The source / drain electrodes make ohmic contact with the contact layer without alloying. Therefore, the selection range of the gate electrode material is widened, and the electrode material having low heat resistance is also selected. Therefore, the same material can be used for the source, drain, and gate electrodes,
Each electrode is simultaneously formed in a self-aligned manner with respect to one insulating film pattern. That is, each electrode is easily and accurately formed.

Since the source / drain regions are formed by selectively removing the contact layer, the source / drain regions do not approach each other below the channel layer as in the conventional case. . Therefore, the short channel effect is suppressed and the FET characteristics with a short gate length are improved.

As described above, according to the present invention, since a high-performance and fine FET is provided, an ultrahigh-speed IC, a microwave
It is particularly effective when applied to the basic element of a device used in the millimeter wave band.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a first half of a manufacturing method according to an embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing the middle half of the manufacturing method according to the embodiment of the present invention.

FIG. 3 is a process sectional view showing a latter half of the manufacturing method according to the embodiment of the present invention.

[Explanation of symbols]

1 ... Semi-insulating GaAs semiconductor substrate, 2 ... Active layer, 3 ... Contact layer, 4 ... Insulating film, 5, 6, 8 ... Resist, 7 ...
Electrode metal, 7a ... Gate electrode, 7b ... Source electrode, 7c
… Drain electrode.

Claims (2)

[Claims] 1. A step of forming an active layer on a semiconductor substrate,
A step of forming a contact layer made of a semiconductor material containing a high concentration of impurities or a semiconductor material having a low energy gap on the active layer, a step of forming an insulating film on the contact layer, and a step of forming the insulating film on the same mask are used. And selectively removing the gate electrode, the source electrode, and the drain to open the electrode regions, the contact layer in the gate electrode region to expose the active layer, and the electrode metal on the insulating film. And a step of selectively removing the electrode metal on the insulating film to electrically separate the electrode metal into gate, source and drain electrodes. 2. An active layer formed on a semiconductor substrate, a contact layer formed on the active layer, the contact layer being made of a semiconductor material containing a high concentration of impurities or a semiconductor material having a small energy gap, and formed on the contact layer. Gate
An insulating film in which each electrode region of the source / drain is opened, a gate electrode in contact with the active layer exposed by removing the contact layer in the gate electrode region, and the contact layer exposed in each electrode region of the source and drain Field effect transistor having a source electrode and a drain electrode made of the same electrode material as the gate electrode formed in contact with.