JPH06196494A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an excellent LDD structure by a method wherein a gate electrode of an LDD transistor structure is formed by one ion implanting operation. CONSTITUTION:A gate electrode is formed through such a process that a polysilicon film 3 is formed first on a gate SiO2 film 2 on a substrate 1, an amorphous silicon film 4 is formed thereon, a photoresist 5 is laid thereon, and the amorphous silicon film 4 is dry-etched 6 while kept undoped. The side face 7 of the amorphous silicon 4 grows vertical, and the side face 8 of the polysilicon 3 becomes tapered. Then, ions are implanted, whereby an excellent gate electrode of LDD structure can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having an LDD transistor structure.

[0002]

2. Description of the Related Art LDD (lightly doped)
drain: lightly doped drain) transistor
Generally, it is created by the following steps. (1) A gate electrode is formed. (2) Low-concentration shallow source / drain regions are formed by ion implantation. (3) Oxide film deposition is performed by CVD. (4) Anisotropic etching is performed to form sidewalls on the sidewalls of the gate electrode. With this sidewall, the tip of the lateral diffusion of the region ion-implanted in the next step is determined by the position of polysilicon and the width of the sidewall. (5) A high concentration source / drain region is formed by ion implantation. At this time, the gate does not overlap with the heavily doped source / drain regions, and a low impurity gradient at the drain-channel interface can be realized.

[0003]

In the above conventional technique, the ion implantation process is performed twice, and the process such as the sidewall formation process is complicated and costly. Further, there is a problem that the Si substrate is dug by the SiO ₂ etching at the time of forming the side wall, which becomes a source of the defect layer and causes a junction leak.

An object of the present invention is to solve the above problems and provide a method for easily forming an excellent LDD transistor.

[0005]

According to the present invention, the lower layer of the gate electrode material is polysilicon and the upper layer is amorphous silicon, and anisotropic etching is performed with the gate electrode material left undoped. The sidewall of the lower polysilicon layer is etched into a tapered shape. At this time, the etching condition does not need to be multi-step, and only one process of the condition that the amorphous silicon layer can be vertically etched is sufficient.

[0006] Then the N-channel side for the source and drain regions formed a P ⁺ or As ^+, the P-channel side B ⁺ or BF ₂ ⁺ is ion-implanted. This makes it possible to inject a high concentration of impurities into the gate electrode simultaneously with the formation of the source / drain, and because the polysilicon layer of the gate electrode has a tapered shape,
An LDD structure can be formed by performing high-concentration ion implantation into the drain only once.

[0007]

According to the conventional method, (1) gate polysilicon film formation, (2) impurity implantation and annealing, (3) gate processing, (4) low concentration ion implantation, (5) sidewall formation, (6) high concentration Ion implantation and 6 steps were required,
According to the method of the present invention, (a) gate (poly / amorphous) silicon film formation, (b) gate processing, (c) high-concentration ion implantation, (d) gate etching (isotropic etching) and 4
It can be omitted in the process.

The polysilicon film formation and the amorphous silicon film formation can be performed in the same process by setting the film formation temperature to 600 ° C. or more and 570 ° C. or less by a low pressure CVD apparatus and changing them during the film formation. it can.
Further, since the SiO ₂ etching for forming the side wall can be omitted, the substrate is not dug. Therefore, the junction leak defect can be prevented.

[0009]

Example A polysilicon and amorphous silicon film is formed on a gate oxide film by a low pressure CVD apparatus. This sequence is shown in FIG. Polysilicon film at 620 ° C
Then, 1500 Å is formed, and after forming a polysilicon film, the temperature of the furnace is lowered to 550 ° C. to form an amorphous silicon film. Amorphous silicon film thickness is 3000Å
And This is shown in FIG. 1, in which polysilicon 3 is deposited on the silicon substrate 1 and the gate SiO ₂ film 2 at 620 ° C.
500Å, 3000 amorphous silicon 4 on it
Å It is formed and the photoresist 5 is put on it.

Next, gate etching is performed by the RIE apparatus under the following conditions. Gas used: CCl ₄ / He / O ₂ = (90-100) / 350/20 (sccm) Pressure: 290-360 (mTorr) RF power: 120-150 (W) Electrode temperature: 45-55 (° C) Figure As shown in FIG. 2, the side surface 7 of the layer of the amorphous silicon 4 which has undergone the anisotropic etching 6 becomes vertical, and the side surface 8 of the layer of the polysilicon 3 becomes tapered. As shown in FIG. 3, the width of the polysilicon 3 in the tapered shape is about 0.15 μm.

Next, as shown in FIG. 4, ions are implanted into the region 9 in the substrate. 40 Ke for As on the N channel side
Ion implantation is performed at V, 5 × 10 ¹⁵ / cm ² , and BF ₂ is ion implanted at 40 KeV and 5 × 10 ¹⁵ / cm ² on the P channel side. Impurity can be implanted into the gate electrode 12 at a high concentration, and then annealed. Then, as shown in FIG. 5, N ⁻ source / drain 10 and N ⁺ are formed on the N channel side.
The source / drain 11 is formed.

Finally, as shown in FIG. 6, the gate silicon film 12 is isotropically etched by chemical dry etching,
The length of the bottom edge of the gate should match the low concentration side of the source / drain. The etching amount of the etching part 13 is 100
It is 0Å. The transistor thus formed has a performance equivalent to that of a conventional LDD transistor having a sidewall length of 0.15 μm.

[0013]

According to the present invention, a polysilicon layer is formed in the lower layer and an amorphous silicon layer is formed in the upper layer, and the amorphous silicon layer is dry-etched without being doped,
The side surface of the amorphous layer is vertical and the side surface of the polysilicon layer is tapered. Therefore, it becomes possible to form a drain region having an excellent LDD structure by one-time ion implantation.

[Brief description of drawings]

FIG. 1 is a cross-sectional view at the time of resist molding.

FIG. 2 is an explanatory diagram of an anisotropic etching process.

FIG. 3 is an explanatory diagram at the end of the anisotropic etching step.

FIG. 4 is an explanatory diagram of an ion implantation process.

FIG. 5 is a cross-sectional view after annealing.

FIG. 6 is a cross-sectional view of a silicon etching process.

FIG. 7 is a temperature pattern diagram when forming a silicon film.

[Explanation of symbols]

1 Si substrate 2 gate Si
O ₂ film 3 Polysilicon 4 Amorphous silicon 5 Photoresist 6 Etching 7, 8 Side surface 9 Region 10 N ^- Source / drain 11 N ⁺ Source / drain 12 Gate silicon film 13 Etched part

Claims (1)

[Claims] 1. In forming an LDD transistor structure, polysilicon is first formed, amorphous silicon is subsequently formed, and this silicon film is dry-etched as it is without doping to form a gate electrode, and then a gate and a source. And a method for manufacturing a semiconductor device, characterized in that impurity ion implantation is simultaneously performed in the drain region.