JPH06163690A - Placement and routing apparatus for electronic device - Google Patents

Placement and routing apparatus for electronic device

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Publication number
JPH06163690A
JPH06163690A JP4314788A JP31478892A JPH06163690A JP H06163690 A JPH06163690 A JP H06163690A JP 4314788 A JP4314788 A JP 4314788A JP 31478892 A JP31478892 A JP 31478892A JP H06163690 A JPH06163690 A JP H06163690A
Authority
JP
Japan
Prior art keywords
wiring
source terminal
placement
electronic device
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4314788A
Other languages
Japanese (ja)
Inventor
Izumi Hayashibara
泉 林原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP4314788A priority Critical patent/JPH06163690A/en
Publication of JPH06163690A publication Critical patent/JPH06163690A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To make it possible to lay out wirings more easily in the case when a PLD is included in electronic devices wires on a circuit board by providing a pin function conversion means which changes the functions of an input pin or an output pin of a programmable logic device laid out by a device layout means. CONSTITUTION:A before-wiring to be processed is assumed to be a wiring 1. As for a source terminal A of the unlaid out wiring 1, there is found a source terminal changeable to this source terminal A with the same PLD. The found source terminal B is exchanged with the source terminal A and the wiring 1 is connected to the source terminal B where a wiring 2 is connected to the source terminal A. When all wiring, which are not laid out yet, are processed, the whole processing will be ended. If there remains any wiring which is not laid out yet, the process will return to the original process as an uncompleted wiring. In the case when a PLD is included as an electronic device, it will be possible to lay out wirings more smoothly in automatic mode with no attendance of an operator who directs replacement of devices by himself or herself. What differs from the prior art process, is in the point that a step (i) is inserted between steps (f) and (g).

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複数の電子デバイスの
回路基板上への配置配線設計を行なう電子デバイス配置
配線装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device placement / wiring apparatus for designing placement / wiring of a plurality of electronic devices on a circuit board.

【0002】[0002]

【従来の技術】従来より、回路基板(PCB;Prin
t−Circuit Board)上に配置されるI
C,トランジスタ,抵抗,コンデンサ等の電子デバイス
の、回路基板上の配置位置を自動的に決定し、決定され
た位置に従って各電子デバイスの端子間の結線を自動的
に決定するアルゴリズムを備えた電子デバイス配置配線
装置が用いられている。
2. Description of the Related Art Conventionally, a circuit board (PCB;
I placed on the t-Circuit Board)
An electronic device equipped with an algorithm that automatically determines the placement positions of electronic devices such as C, transistors, resistors, and capacitors on the circuit board, and automatically determines the connection between the terminals of each electronic device according to the determined positions. A device placement and wiring device is used.

【0003】図3は従来の電子デバイス配置配線装置に
おける配置配線設計の手順の一例を示したフローチャー
トである。回路基板上に配置配線されるべき複数の電子
デバイスの入力ピン,出力ピンの配置位置とそれら複数
の電子デバイス間の配線図が入力されると、先ずこれら
複数の電子デバイスの回路基板上への配置順序が定めら
れ(ステップ(a))、この定められた順序に従い、さ
らに必要に応じて、その回路基板への入力を受ける電子
デバイスあるいはその回路基板から外部への出力を担う
電子デバイスはその回路基板の端子の近傍に配置するこ
と等の制約条件に従って、回路基板上に電子デバイスを
配置する(ステップ(b))。尚ここで「配置」と称し
ているのは、電子デバイスを回路基板上に物理的に配置
することを意味するものではなく、仮想された平面への
配置、即ち配置設計を行なうことを意味している。
FIG. 3 is a flow chart showing an example of a layout and wiring design procedure in a conventional electronic device layout and wiring apparatus. When the arrangement positions of the input pins and output pins of a plurality of electronic devices to be arranged and wired on the circuit board and the wiring diagram between the plurality of electronic devices are input, first, the plurality of electronic devices are arranged on the circuit board. The arrangement order is determined (step (a)), and the electronic device that receives an input to the circuit board or the electronic device that takes an output from the circuit board to the outside according to the determined order is the The electronic device is arranged on the circuit board according to a constraint condition such as arrangement in the vicinity of the terminal of the circuit board (step (b)). It should be noted that the term “arrangement” here does not mean that the electronic device is physically arranged on the circuit board, but means that the electronic device is arranged on a virtual plane, that is, the layout is designed. ing.

【0004】次に、回路基板上に配置された複数の電子
デバイスの信号を送出する各端子(以下これを「ソース
端子」と称する)に配線順序が付され(ステップ
(c))、その順序に従って配線が行なわれる。尚、こ
こで「配線」と称するのは、上記「配置」と同様、仮想
された平面上における配線、即ち配線設計を意味してい
る。次にステップ(e)において、多数の配線が互いに
交差することなく配線できたか否か、および必要に応じ
て配線ピッチが細かすぎないかどうか等が判断され、全
ての配線が基準を満たしているときは配置配線設計が終
了する。一本でも基準を満たさず、例えば交差して配線
することが許されていない場合に他の配線と交差しない
と配線することができない場合は、ステップ(f)に進
み、全ての配線順序について配線を試みたか否かが判定
され、まだ試みていない配線順序が残っている場合はス
テップ(c)に戻り、ソース端子の配線順序を変更し、
再度配線が試みられる。このようにしてどの配線順序に
ついても配線を試みた結果いずれも基準を満たすことが
できなかったときは、ステップ(g)に進み、全ての配
置順序について配線を試みたか否かが判定され、また配
線を試みていない配置順序があれば複数の電子デバイス
の配置順序を変更して(ステップ(a))配線する(ス
テップ(b))。また、ステップ(g)において全ての
配置について配線を試みたのであれば全配置の全配線に
ついて基準を満たすことができない旨出力する(ステッ
プ(h))。
Next, the wiring order is given to each terminal (hereinafter referred to as "source terminal") for transmitting signals of a plurality of electronic devices arranged on the circuit board (step (c)), and the order is given. Wiring is carried out according to. It should be noted that the term "wiring" as used herein means wiring on a virtual plane, that is, wiring design, like the above-mentioned "arrangement". Next, in step (e), it is judged whether or not a large number of wirings can be arranged without intersecting each other, and if the wiring pitch is not too small, etc., and all the wirings satisfy the criteria. Then, the layout and wiring design is completed. If even one wire does not meet the criteria, for example, if wiring is not allowed to intersect, if wiring cannot be performed unless it intersects with another wiring, the process proceeds to step (f), and wiring is performed for all wiring orders. It is determined whether or not, and if the wiring order that has not been tried remains, the process returns to step (c) to change the wiring order of the source terminal,
The wiring is tried again. When none of the wiring orders satisfy the criteria as a result of attempting the wiring in this way, the process proceeds to step (g), where it is determined whether the wiring has been attempted for all the placement orders. If there is an arrangement order in which wiring is not attempted, the arrangement order of a plurality of electronic devices is changed (step (a)) and wiring is performed (step (b)). Further, if wiring is attempted for all the arrangements in step (g), it is output that the standard cannot be satisfied for all the wirings of all the arrangements (step (h)).

【0005】従来は、回路基板上への電子デバイスの配
置配線の一例として、例えば上述のアルゴリズムが採用
されている。
Conventionally, for example, the above-described algorithm has been adopted as an example of arrangement and wiring of electronic devices on a circuit board.

【0006】[0006]

【発明が解決しようとする課題】従来は、例えば上述し
た配置配線アルゴリズムを採用して回路基板上への電子
デバイスの配置配線を行なっているため、他の配線を跨
ぐことなく配線が行なえたとしても特に配線長を短くし
ようとすると配線が混雑するケースも多いという問題が
ある。
In the prior art, for example, the placement and routing algorithm described above is employed to place and route electronic devices on a circuit board, so that wiring can be performed without straddling other wiring. However, there is a problem that the wiring is often congested especially when trying to shorten the wiring length.

【0007】本発明は、上記事情に鑑み、特に機能が自
在に変換される複数のピンを備えた、いわゆるPLD
(Programmable Logic Devic
e)(FPGA,PAL等を含む)を回路基板上に配置
されるべき電子デバイスとして含む場合の電子デバイス
の配置配線設計に有効な電子デバイス配置配線装置を提
供することを目的とする。
In view of the above circumstances, the present invention is a so-called PLD having a plurality of pins whose functions can be freely converted.
(Programmable Logic Device
It is an object of the present invention to provide an electronic device placement and routing apparatus effective for placement and routing design of an electronic device when e) (including FPGA, PAL, etc.) is included as an electronic device to be placed on a circuit board.

【0008】[0008]

【課題を解決するための手段】上記目的を達成する本発
明の電子デバイス配置配線装置は、機能が変更される複
数の入力ピンまたは出力ピンを備えた電子デバイスであ
るプログラマブルロジックデバイスを含む複数の電子デ
バイスの回路基板上への配置配線設計を行なう電子デバ
イス配置配線装置において、複数の電子デバイスの回路
基板上への配置設計を行なうデバイス配置手段と、デバ
イス配置手段により配置された複数の電子デバイス間の
配線設計を行なうデバイス間配線手段と、デバイス配置
手段により配置されたプログラマブルロジックデバイス
の入力ピンまたは出力ピンの機能を変更するピン機能変
換手段とを備えたことを特徴とするものである。
An electronic device placement and routing apparatus of the present invention which achieves the above object includes a plurality of programmable logic devices which are electronic devices having a plurality of input pins or output pins whose functions are changed. In an electronic device placement and routing apparatus for designing placement and routing of electronic devices on a circuit board, device placement means for designing placement of a plurality of electronic devices on a circuit board, and a plurality of electronic devices placed by the device placement means The inter-device wiring means for designing the wiring between the devices and the pin function conversion means for changing the function of the input pin or the output pin of the programmable logic device arranged by the device arranging means are provided.

【0009】ここで、「上記入力ピンまたは出力ピンの
機能を変更する」とは、図1(A)に示すように複数の
ピンP1,P2の機能を互いに交換すること、および図
1(B)に示すように所定の機能を有するピンをある1
つのピンP1から他の1つのピンP2に移動することの
双方を含む。
Here, "changing the function of the input pin or the output pin" means exchanging the functions of a plurality of pins P1 and P2 with each other as shown in FIG. 1 (A), and FIG. 1 (B). ) Has a pin with a predetermined function as shown in 1)
Both include moving from one pin P1 to another pin P2.

【0010】[0010]

【作用】本発明の電子デバイス配置配線装置は、従来と
同様なデバイス配置手段とデバイス間配線手段のほか、
ピン機能変更手段を備えたため、回路基板上に配置配線
される電子デバイスとしてプログラマブルロジックデバ
イス(PLD;FPGA,PAL等を含む)を有する場
合に配線の混雑が緩和され、従来よりも容易に、所要の
要件を満足する配置配線が行なわれる。
The electronic device placement / wiring apparatus of the present invention includes the same device placement means and inter-device wiring means as in the prior art,
Since the pin function changing means is provided, wiring congestion is alleviated when a programmable logic device (PLD; including FPGA, PAL, etc.) is provided as an electronic device arranged and wired on a circuit board, and it is easier and more necessary than before. Placement and routing satisfying the requirement of is performed.

【0011】[0011]

【実施例】以下、本発明の実施例について説明する。図
2は、本発明の一実施例に係る電子デバイス配置配線装
置における処理手順を示したフローチャートである。図
3に示すフローチャートと同一内容のステップについて
は図3に付した番号と同一の番号を付し相違点について
のみ説明する。
EXAMPLES Examples of the present invention will be described below. FIG. 2 is a flowchart showing a processing procedure in the electronic device placement and routing apparatus according to the embodiment of the present invention. The steps having the same contents as those in the flowchart shown in FIG. 3 are designated by the same numbers as those given in FIG. 3, and only the differences will be described.

【0012】この図2に示すフローチャートの、図3に
示すフローチャートとの相違点は、ステップ(f)とス
テップ(g)との間に端子交換のステップ(i)が挿入
されている点である。以下ステップ(i)の端子交換ア
ルゴリズムについて詳述する。この端子交換アルゴリズ
ムは以下の手順により行なわれる。 (i)すべての未配線の配線について以下の処理(ii)
〜(xi)を繰り返す。処理する未配線を配線1とする。 (ii)未配線1のソース端子Aについて 同じPLDでこのソース端子Aと交換可能なソース端子
Bを発見する。交換可能なソース端子Bが発見できなけ
れば処理(vi)へ進む。発見された端子Bに既に配線が
接続されていた場合、その配線を以下配線2とする。 (iii )発見したソース端子Bをソース端子Aと交換す
る。この場合、配線1をソース端子Bと接続し、配線2
をソース端子Aと接続することになる。 (iv)配線1、配線2をそれぞれ配線する。 (v)両者のいずれもが配線されれば、その配線につい
ては処理を終了し、処理(xi)へ進む。いずれか一方が
配線されなければ、B以外の端子を発見するため処理
(ii) へ戻る。 (vi)未配線1のすべてのロード端子(ソース端子と接
続される負荷側の端子をいう)A′について、以下の処
理(vii )〜(x)を行なう。 (vii )ロード端子A′と同じPLD上で、このロード
端子A′と交換可能なロード端子B′を発見する。交換
可能な端子B′が発見できなければ処理(xi)進む。発
見された端子B′に既に配線が接続されていた場合、そ
の配線を以下配線3と呼ぶ。 (viii)発見したロード端子A′をロード端子B′と交
換する。この場合、配線1がロード端子B′に接続さ
れ、配線3がロード端子A′に接続されることになる。 (ix)配線1と配線3をそれぞれ配線する。(おのおの
の配線1、3に関してすべてのロードとソース間で配線
されれば配線されたことになる。) (x)両者のいずれもが配線されれば、その未配線につ
いて処理を終了する。処理(xi)へ進む。いずれかが配
線されなければ、ほかの交換可能なロード端子を発見す
るため処理(vii )戻る。 (xi)すべての未配線について処理(最終的に配線がで
きなかった場合を含む)が行なわれていれば、全体の処
理を終了する。全体の処理の終了時点で未配線がなくな
っていた場合は「正常終了」、未配線が残っていれば
「配線未完終了」として図2に示すフローに戻る。処理
の行なわれていない未配線が残っている場合は、処理(i
i)へ戻る。
The difference between the flowchart shown in FIG. 2 and the flowchart shown in FIG. 3 is that the step (i) for terminal exchange is inserted between the steps (f) and (g). . The terminal exchange algorithm of step (i) will be described in detail below. This terminal exchange algorithm is performed by the following procedure. (I) The following processing for all unwired wiring (ii)
Repeat ~ (xi). The unwiring to be processed is called wiring 1. (Ii) Regarding the source terminal A of the unwired 1, find the source terminal B that can be exchanged with the source terminal A in the same PLD. If the replaceable source terminal B cannot be found, the process proceeds to the process (vi). When a wire is already connected to the found terminal B, the wire will be referred to as a wire 2 hereinafter. (Iii) Replace the found source terminal B with the source terminal A. In this case, the wiring 1 is connected to the source terminal B, and the wiring 2
Will be connected to the source terminal A. (Iv) Wiring the wiring 1 and the wiring 2 respectively. (V) If both of them are wired, the processing for that wiring is terminated, and the processing proceeds to processing (xi). If either one of them is not wired, the process returns to the process (ii) to find a terminal other than B. (Vi) The following processes (vii) to (x) are performed on all the load terminals (referred to as load side terminals connected to the source terminals) A ′ of the unwired 1. (Vii) On the same PLD as the load terminal A ', find the load terminal B'which is replaceable with the load terminal A'. If the replaceable terminal B ′ cannot be found, the process (xi) proceeds. If a wire is already connected to the found terminal B ', the wire will be referred to as a wire 3 hereinafter. (Viii) Replace the found load terminal A'with the load terminal B '. In this case, the wiring 1 is connected to the load terminal B'and the wiring 3 is connected to the load terminal A '. (Ix) Wire 1 and wire 3 respectively. (Each of the wirings 1 and 3 has been wired if it is wired between all the loads and sources.) (X) If both of them are wired, the processing is completed for the unwired. Proceed to processing (xi). If either is not wired, return (vii) to find another replaceable load terminal. (Xi) If the processing (including the case where the wiring could not be completed finally) is performed for all the unwired, the entire processing is ended. If there are no unwired wires at the end of the entire processing, "normal termination" is performed, and if unwired wires remain, "wiring unfinished" is returned to the flow shown in FIG. If there are unprocessed wires that have not been processed,
Return to i).

【0013】本実施例は、上記のような端子交換を行な
うものであるため、電子デバイスとしてPLDが含まれ
ている場合に、オペレータがわざわざ端子の交換を指示
しなくてもよりスムーズな自動配置配線が行なわれる。
尚、上記実施例では、図2に示すステップ(i)におい
て配線未完終了の場合は、電子デバイスの配置の変更へ
と進むが、配線未完終了の場合に配線順を変更するよう
にしてもよく、あるいは配線未完の程度やその他の状況
により、次に配線順を変更するステップに進むか配置順
を変更するステップに進むかを分けてもよい。
In this embodiment, the terminals are exchanged as described above. Therefore, when a PLD is included as an electronic device, a smoother automatic arrangement can be performed without the operator's instruction to exchange the terminals. Wiring is done.
In the above embodiment, if the wiring is not completed in step (i) shown in FIG. 2, the electronic device layout is changed. However, if the wiring is not completed, the wiring order may be changed. Alternatively, whether to proceed to the step of changing the wiring order or the step of changing the arrangement order may be divided depending on the degree of uncompleted wiring and other circumstances.

【0014】また上記実施例は一例に過ぎず、上述した
端子変換アルゴリズム以外のアルゴリズムにより端子変
換を行なうようにしてもよいことはもちろんである。
The above embodiment is merely an example, and it goes without saying that the terminal conversion may be performed by an algorithm other than the terminal conversion algorithm described above.

【0015】[0015]

【発明の効果】以上説明したように、本発明の電子デバ
イス配置配線装置は、従来と同様なデバイス配置手段と
デバイス間配線手段のほか、ピン機能変更手段を備えた
ものであるため、回路基板上に配置配線される電子デバ
イスにPLDが含まれる場合に、従来よりも容易に配置
配線が行なわれる。
As described above, the electronic device placement / wiring apparatus of the present invention includes the same device placement means and inter-device wiring means as in the prior art, and the pin function changing means. When the PLD is included in the electronic device to be placed and routed above, the placement and routing is performed more easily than before.

【図面の簡単な説明】[Brief description of drawings]

【図1】PLDのピンの機能の変換(A),ピンの移動
(B)を示した模式図である。
FIG. 1 is a schematic diagram showing conversion (A) and pin movement (B) of a PLD pin function.

【図2】本発明の一実施例に係る電子デバイス配置配線
装置における処理手順を示したフローチャートである。
FIG. 2 is a flow chart showing a processing procedure in an electronic device placement and routing apparatus according to an embodiment of the present invention.

【図3】従来の電子デバイス配置配線装置における配置
配線設計の手順の一例を示したフローチャートである。
FIG. 3 is a flowchart showing an example of a procedure for layout and wiring design in a conventional electronic device layout and wiring apparatus.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 機能が変更される複数の入力ピンまたは
出力ピンを備えた電子デバイスであるプログラマブルロ
ジックデバイスを含む複数の電子デバイスの回路基板上
への配置配線設計を行なう電子デバイス配置配線装置に
おいて、 前記複数の電子デバイスの回路基板上への配置設計を行
なうデバイス配置手段と、 前記デバイス配置手段により配置された前記複数の電子
デバイス間の配線設計を行なうデバイス間配線手段と、 前記デバイス配置手段により配置された前記プログラマ
ブルロジックデバイスの入力ピンまたは出力ピンの機能
を変更するピン機能変更手段とを備えたことを特徴とす
る電子デバイス配置配線装置。
1. An electronic device placement and routing apparatus for designing placement and routing of a plurality of electronic devices including a programmable logic device, which is an electronic device having a plurality of input pins or output pins whose functions are changed, on a circuit board. A device placement means for designing placement of the plurality of electronic devices on a circuit board; an inter-device wiring means for designing wiring between the plurality of electronic devices placed by the device placement means; and the device placement means. And a pin function changing means for changing a function of an input pin or an output pin of the programmable logic device arranged by the electronic device placement and routing apparatus.
JP4314788A 1992-11-25 1992-11-25 Placement and routing apparatus for electronic device Withdrawn JPH06163690A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4314788A JPH06163690A (en) 1992-11-25 1992-11-25 Placement and routing apparatus for electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4314788A JPH06163690A (en) 1992-11-25 1992-11-25 Placement and routing apparatus for electronic device

Publications (1)

Publication Number Publication Date
JPH06163690A true JPH06163690A (en) 1994-06-10

Family

ID=18057603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4314788A Withdrawn JPH06163690A (en) 1992-11-25 1992-11-25 Placement and routing apparatus for electronic device

Country Status (1)

Country Link
JP (1) JPH06163690A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7784011B2 (en) 2006-12-04 2010-08-24 Fujitsu Limited Reflecting pin swap of PLD performed in package design in circuit design and PLD design
US7831944B2 (en) 2006-12-04 2010-11-09 Fujitsu Limited Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method
US7904863B2 (en) 2006-12-04 2011-03-08 Fujitsu Limited Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method
US7913220B2 (en) 2006-12-04 2011-03-22 Fujitsu Limited Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, and printed-circuit-board manufacturing method
US8176457B2 (en) 2006-12-04 2012-05-08 Fujitsu Limited Apparatus and method updating diagram of circuit based on pin swap performed in package design with respect to PLD
US8255844B2 (en) 2006-12-04 2012-08-28 Fujitsu Limited Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7784011B2 (en) 2006-12-04 2010-08-24 Fujitsu Limited Reflecting pin swap of PLD performed in package design in circuit design and PLD design
US7831944B2 (en) 2006-12-04 2010-11-09 Fujitsu Limited Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method
US7904863B2 (en) 2006-12-04 2011-03-08 Fujitsu Limited Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method
US7913220B2 (en) 2006-12-04 2011-03-22 Fujitsu Limited Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, and printed-circuit-board manufacturing method
US8176457B2 (en) 2006-12-04 2012-05-08 Fujitsu Limited Apparatus and method updating diagram of circuit based on pin swap performed in package design with respect to PLD
US8255844B2 (en) 2006-12-04 2012-08-28 Fujitsu Limited Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method

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