JPH0613604A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide strong coupling between a gate and n<-> regions below a gate electrode by reducing the thickness of a gate insulating film at end portions of the gate electrode. CONSTITUTION:An insulating film 2 is formed on the surface of a p-type Si semiconductor substrate 1. After a nitride film 3 is deposited on the insulating film 2, the nitride film 3 is etched in an area to become a gate region. Then, a gate insulating film 5 is formed by thermal oxidation, in which the insulating film 5 is thin in the vicinity of the nitride film 3 because of insufficient supply of O2. After a polysilicon electrode 6 is deposited on the above structure, the polysilicon electrode 6 is etched to form a gate electrode 7. After the nitride film 3 is removed, phosphorus ions are implanted from above the substrate surface to form a first source 8 and a first drain 9. After an insulating film is deposited around the gate electrode 7 and then etched to form side walls 10, arsenic ions are implanted to form a second source 11 and a second drain 12 and a heat treatment is then performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device which is an insulated gate field effect transistor having high speed and high reliability and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a conventional Nch MOS type (insulated gate type) transistor, in order to provide high reliability, an LDD (a drain region is used to positively reduce the concentration near the channel in the drain region). Lightl
y Doped Drain) structures have been used. L like this
The DD structure is, for example, IEE Transaction on Electron Devices ((IEEE
TRANSACTIONS ON ELECTRON DEVICES) Vol. 29, No. 4,
April 1982). In this structure, as shown in FIG. 3, the insulating film 5 is formed on the semiconductor substrate 1, the gate electrode 7 is formed on the insulating film 5, and the sidewall 10 is formed around the gate electrode 7. . A first source 8 and a first drain 9 are provided on the semiconductor substrate 1 below the insulating film 5 and at positions corresponding to the ends of the gate electrode 7, and below the insulating film 5 Source 8 and 1
The second source 11 is provided outside the drain 9 of the
And a second drain 12 are provided. According to this structure, the drain region 9 (n ⁻ region) having a relatively low concentration is formed.
Plays a role of relaxing the electric field in the vicinity of the drain, so that high reliability such as drain breakdown voltage can be obtained.

[0003]

However, in the MOS type (insulated gate type) transistor having the above LDD structure, the n ⁻ region is pinched off and the resistance is remarkably increased, so that the drive current is apt to be deteriorated. Had.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an insulated gate field effect transistor which prevents a high resistance and has a high driving force.

[0005]

In order to solve the above problems, according to the present invention, the gate insulating film of the insulated gate field effect transistor is formed thin at the end of the gate electrode.

Further, according to the present invention, an insulating film is formed on a surface of a semiconductor substrate, a nitride film is deposited on the insulating film, the nitride film in a portion to be a gate region is selectively removed, and then thermal oxidation is performed. Forming a gate insulating film having a thin thickness in the vicinity of the nitride film in the removed portion, depositing a gate electrode material on the gate insulating film, and etching back the gate electrode material to form a gate electrode Then, the nitride film is removed, and ion implantation of a conductivity type opposite to that of the semiconductor substrate is performed on the semiconductor substrate using the gate electrode as a mask to form low-concentration source / drain. A side wall is formed by depositing an insulating film around the electrode and anisotropically etching, and then using the gate electrode and the side wall as a mask, the semi-concentration is higher than that of the ion implantation. By ion implantation of the body opposite to the substrate conductivity type to form a source and drain of a high concentration, and finally by performing a heat treatment, a semiconductor device was manufactured.

In the method of the present invention, the material of the side wall may be the same as that of the gate electrode.

[0008]

As described above, since the insulated gate field effect transistor of the present invention has a structure in which the gate insulating film at the end of the gate electrode is thin, the n ⁻ region below the gate electrode is strongly coupled with the gate. . This prevents pinch-off and high resistance in the n ⁻ region.

Further, according to the method of the present invention, when the thermal oxidation is performed, oxygen is not sufficiently supplied in the vicinity of the nitride film, and the oxide film becomes thin, so that the gate insulating film is formed at the end of the gate electrode. By making it thin, it is possible to manufacture an insulated gate field effect transistor in which the n ⁻ region under the gate electrode is strongly coupled to the gate.

Further, according to the method of the present invention, the same material as the gate electrode is used for the side wall, and the side wall is made a part of the gate electrode, so that the n ⁻ region below the side wall is also gated. It is possible to manufacture an insulated gate field effect transistor that strongly couples with.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the semiconductor device of the present invention. The insulating film 2 is formed on the semiconductor substrate 1, the gate electrode 7 is formed on the insulating film 2, and the sidewalls 10 are formed around the gate electrode 7. A gate insulating film 5 is formed under the gate electrode 7, and the gate insulating film 5 has a structure in which the gate insulating film 5 is thinned at the end portion of the gate electrode 7. The semiconductor substrate 1 is provided with a first source 8 and a first drain 9 below the insulating film 2 at positions corresponding to the ends of the gate insulating film 5, and below the insulating film 2 1
Outside the source 8 and the first drain 9 of
A second source 11 and a second drain 12 are provided.

FIG. 2 shows a manufacturing process of the semiconductor device of the present invention. An insulating film 2 having a thickness of 2 nm is formed on the surface of a P-type semiconductor substrate 1 having an impurity concentration of 1E16 cm ^-3 , and a nitride film 3 is deposited thereon to a thickness of 100 nm, and then a MOS transistor gate region 4 (gate length 0 0.5 μm) nitride film 3
Are selectively etched (FIG. 2A).

Next, a gate insulating film 5 having a thickness of 15 nm is formed by thermal oxidation (FIG. 2 (b)). At this time, since O ₂ is not sufficiently supplied in the vicinity of 3, 5 is thinly formed as shown in the figure. The polysilicon electrode 6 which is the material for the gate electrode is formed thereon by CVD until it becomes substantially flat.
nm (FIG. 2C), and then the polysilicon electrode 6
By etching 170 nm, the gate electrode 7 having a film thickness of ˜80 nm is formed (FIG. 2D).

Then, the nitride film 3 is removed with phosphoric acid or the like,
After that, phosphorus ions are implanted (40 keV, 3E13 cm ⁻² ) from the surface of the semiconductor substrate using the gate electrode 7 as a mask to form a first source 8 and a first drain 9 (FIG. 2 (e)). .

Next, an insulating film is deposited around the gate electrode 7 by CVD, and anisotropic etching is performed to form a sidewall 10 having a length of 100 nm in the peripheral portion of the gate electrode 7. Then, the gate electrode 7 and the sidewall 1
By implanting high-concentration arsenic ions (40 keV, 6E15 cm ⁻² ) into the semiconductor substrate using 0 as a mask, the second source 11 and the second source 11 having a higher impurity concentration than the first source 8 and the first drain 9 are formed. 2 drain 12 is formed, and finally heat treatment is performed at 900 ° C. for 70 minutes (FIG. 2).
(F)).

By the above method, the edge portion of the gate electrode is
Insulated gate type electric field transistor with thin gate insulating film
You can get Dista. This ensures that it is below the gate electrode.
N ^- The region can be strongly coupled with the gate
It

Further, the material of the side wall 10 may be the same as that of the gate electrode 7 or a material capable of making ohmic contact with the gate electrode 7 to form a part of the gate electrode 7. This allows the n ⁻ region under the sidewall to be strongly coupled with the gate.

Although the method of the present invention is applied to the NchMOS type transistor in the above embodiment, the method of the present invention may be applied to the PchMOS type transistor. Further, although the method of the present invention is applied to both the source and the drain in the above embodiment, it may be applied only to the drain or only to the source.

Further, when forming the first source 8 and the first drain 9, ions may be implanted from an oblique direction.

[0021]

As described above, since the insulated gate field effect transistor of the present invention has a structure in which the gate insulating film at the end of the gate electrode is thin, the n ⁻ region below the gate electrode is strongly connected to the gate. Can be coupled,
It is possible to prevent pinch-off and increase in resistance in the n ⁻ region and secure a high drive current. Therefore, it has higher performance than before.

Further, according to the method of the present invention, when the thermal oxidation is performed, oxygen is not sufficiently supplied in the vicinity of the nitride film, and the oxide film becomes thin. By doing so, it is possible to manufacture an insulated gate field effect transistor in which the n ⁻ region under the gate electrode is strongly coupled to the gate.

Further, by making the material of the side wall the same as the material of the gate electrode and forming a part of the gate electrode, the n ⁻ region under the side wall is also strongly coupled with the gate. Therefore, it is possible to further prevent pinch-off and increase in resistance in the n ⁻ region, and to secure a higher drive current.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a MOS transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the MOS transistor of FIG.

FIG. 3 is a cross-sectional view showing a conventional MOS transistor having an LDD structure.

[Explanation of symbols]

 1 semiconductor substrate 2 insulating film 3 nitride film 4 gate region 5 gate insulating film 7 gate electrode 8 first source 9 first drain 10 sidewall 11 second source 12 second drain

Claims (3)

[Claims] 1. A semiconductor device, wherein a gate insulating film of an insulated gate field effect transistor is thinly formed at a gate electrode end portion. 2. An insulating film is formed on a surface of a semiconductor substrate, a nitride film is deposited on the insulating film, the nitride film in a portion to be a gate region is selectively removed, and then the removal is performed by thermal oxidation. Forming a gate insulating film having a thin thickness in the vicinity of the nitride film at a portion, depositing a gate electrode material on the gate insulating film, and etching back the gate electrode material to form a gate electrode, and , The nitride film is removed, and ion implantation of a conductivity type opposite to that of the semiconductor substrate is performed on the semiconductor substrate using the gate electrode as a mask to form a low concentration source / source.
A drain is formed, and then an insulating film is deposited around the gate electrode and anisotropically etched to form a sidewall. After that, the gate electrode and the sidewall are used as a mask to form a higher concentration than the ion implantation. 2. A method of manufacturing a semiconductor device, comprising performing ion implantation of a conductivity type opposite to that of the semiconductor substrate to form high-concentration source / drain, and finally performing heat treatment. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the sidewall is formed of the same material as the gate electrode or a material capable of making ohmic contact.