JPH06109804A - Temperature rise detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a temp. rise detecting circuit capable of detecting the temp. rise in a semiconductor integrated circuit such as an LSI chip and preventing the erroneous operation and destruction of the semiconductor integrated circuit such as the LSI chip due to a temp. rise. CONSTITUTION:The temp. rise detecting circuit 10 incorporated in a semiconductor integrated circuit has a delay circuit 12 for delaying a reference clock of predetermined frequency by a predetermined time corresponding to a temp. rise, for example, by the time equal to the half cycle of the reference clock under the worst conditions of the operation guarantee of the semiconductor integrated circuit and a flip-flop 14 for inputting the reference clock and the output signal of the delay circuit 12. When the delay of the delay circuit 12 due to a temp. rise exceeds a predetermined value to become larger than the half cycle of the reference clock, the flip-flop 14 outputs a danger signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a temperature rise detecting circuit, and more particularly to a temperature rise detecting circuit which is used by being built in a semiconductor integrated circuit and which detects that the temperature inside the circuit has risen above a predetermined temperature. .

[0002]

2. Description of the Related Art Currently, a large number of highly integrated semiconductor integrated circuits (ICs) such as ICs, LSIs, and VLSIs are used in high-speed arithmetic processing devices for processing a large amount of data, and these are highly densely arranged on a circuit board. . As described above, when the semiconductor integrated circuit chips (IC chips) are arranged at a high density, a large number or a large number of driving power supplies are required to supply power to the respective chips in order to drive these semiconductor chips. Also,
The degree of integration of the IC chip itself is increasing, and the amount of power supplied to the entire IC chip is increasing.

Therefore, IC chips such as LSIs generate a considerable amount of heat and are affected by the heat generated by the adjacent IC chips. This heat is I
There is a case where the temperature inside the C chip is increased, which has a great influence on the normal operation of the LSI, that is, causes a malfunction, and a correct output cannot be obtained. In some cases, the temperature rise is so large that the LSI is destroyed.

Therefore, in the past, I for mounting an IC chip was used.
Various devices for promoting heat dissipation from the C package have been proposed and put into practical use (for example, Japanese Patent Laid-Open No. 2-49).
457 and 2-87560). Also,
In order to guarantee the temperature characteristics of such an IC chip, conventionally, the IC chip is heated or cooled by this heating / cooling device while externally monitoring the temperature data of the heating / cooling device.

However, even if the temperature of the heating / cooling device is externally monitored, the temperature inside the semiconductor chip is not measured, so that the accurate temperature cannot be measured and a reliable temperature characteristic can be obtained. In some cases, the temperature cannot be guaranteed reliably. Therefore, Japanese Patent Application Laid-Open No. 2-52263 discloses a semiconductor test apparatus that incorporates a temperature sensor into a semiconductor chip and measures the output of the temperature sensor during a temperature characteristic test to guarantee the temperature characteristic of the semiconductor chip. Has been done.

[0006]

However, in the semiconductor test apparatus disclosed herein, it is necessary to embed a temperature sensor, for example, a thermoelectric conversion element such as a thermistor or a thermocouple in a part of the semiconductor chip. Since the signal of this built-in temperature sensor is taken out of the semiconductor chip and the temperature is monitored externally during the test, it is necessary to measure the temperature at the time of mounting or using the semiconductor chip and to use it for temperature control. A device is required, and it is difficult to apply this temperature control to a signal processing device using a large number of semiconductor chips.

Further, in the semiconductor laser module disclosed in Japanese Patent Application Laid-Open No. 2-90584, a thermoelectric element for temperature control of a semiconductor laser and a thermocouple for temperature detection are housed in the same package to provide a highly accurate temperature. Although measurement and temperature control are possible, there is a problem that such a technique cannot be applied in a signal processing circuit such as an LSI.

Therefore, there is a problem in that the actual temperature inside the signal processing LSI or the like cannot be measured during operation, and means for avoiding malfunction due to temperature rise cannot be taken. Further, depending on the degree of temperature rise, it may not be possible to avoid the worst state of LSI destruction.

An object of the present invention is to solve the above-mentioned problems of the prior art, to enable detection of temperature rise in a semiconductor integrated circuit such as an LSI chip, and to prevent malfunction or destruction of the semiconductor integrated circuit such as LSI due to temperature rise. It is to provide a temperature rise detection circuit capable of preventing the temperature rise.

[0010]

In order to achieve the above object, the present invention is a temperature rise detecting circuit incorporated in a semiconductor integrated circuit and used, wherein the delay circuit delays a reference clock of a predetermined frequency, A flip-flop that receives the reference clock and the output signal of the delay circuit as input, and the flip-flop outputs a danger signal when the delay of the delay circuit due to temperature rise exceeds a predetermined value. A characteristic temperature rise detection circuit is provided.

Here, it is preferable that the flip-flop outputs a danger signal when the delay of the delay circuit exceeds a half cycle of the reference clock.
Further, it is preferable that the delay circuit has a plurality of gates connected in stages. Furthermore, it is preferable that the number of stages of the gates forming the delay circuit is configured such that the delay time is equal to a half cycle of the reference clock under the worst condition of operation guarantee of the semiconductor integrated circuit.

[0012]

The temperature rise detection circuit of the present invention is a delay circuit for delaying a reference clock having a predetermined frequency such as a system clock by a predetermined time interval, for example, a delay circuit having a plurality of connected gates, and an output of the delay circuit. A flip-flop that receives the reference clock is provided, and the flip-flop can output a danger signal when the delay due to the temperature rise of the delay circuit exceeds a predetermined value, that is, a half cycle of the reference clock. .

Therefore, according to the temperature rise detection circuit of the present invention, by incorporating the temperature rise detection circuit, the LS caused by the temperature rise is increased.
It is possible to prevent malfunction or destruction of the semiconductor integrated circuit such as I.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A temperature rise detecting circuit according to the present invention will be described in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram of an embodiment of a temperature rise detecting circuit of the present invention, and FIG. 2 is an embodiment of a delay circuit used in the present invention. As shown in the figure, the temperature rise detection circuit 10 of the present invention is used by being incorporated in a semiconductor integrated circuit such as an LSI (not shown), and has a delay circuit 12 and a flip-flop 14. Here, the system clock a is input to the input terminal of the delay circuit 12, and its output terminal is connected to one input terminal of the flip-flop 14. The above-mentioned system clock a is input to the other input terminal of the flip-flop 14, and the danger signal c is output from the output terminal thereof.

As shown in FIGS. 1 and 3, the delay circuit 12 delays the system clock a by a predetermined delay time td and outputs the delay signal b, but the delay time td increases due to the temperature rise. is there. Here, it is preferable that the delay circuit 12 used in the present invention has a plurality of gates 16 such as a buffer connected in series, for example, n stages, as shown in FIG. The reason for this is that the LS
The main cause of the malfunction of I is that the operation does not end at the system clock frequency (the frequency of the system clock a) due to the increase in the delay of the gate, and this phenomenon is used to detect the temperature rise. Is. In addition,
The reference clock used in the present invention is not limited to the system clock a, and any clock having a required frequency may be used.

That is, the present invention uses the delay circuit 12 in which a large number of gates 16 are connected in series as shown in FIG. 2, and as shown in FIG.
Is passed through a large number of gates 16 of the delay circuit 12 to obtain a delayed signal b, which is a system clock a which is an original signal.
On the other hand, when the delay time exceeds the half cycle (T / 2) of the system clock a, this is detected by the flip-flop 14 and output as the danger signal c. Therefore, in the present invention, the increase in the delay time td of the delay circuit 12 detects the temperature increase in the delay circuit 12 itself and as a result, the temperature inside the LSI.

The delay circuit 12 used in the present invention uses the gates 16 connected in multiple stages. The number n of stages of the gates 16 is not particularly limited, and the gates 16 may be connected in any number of stages. The delay time in the delay circuit 12 is the system clock a under the condition that the gate delay becomes maximum within the guaranteed operating range of the semiconductor integrated circuit (usually at the maximum temperature defined by the recommended operating condition and at the minimum power supply voltage). May be appropriately selected according to the delay time of each gate 16 at a predetermined temperature, the temperature characteristics, etc. The delay time for each temperature of each individual gate serving as a reference can be obtained by an actual measurement value, a simulation, or a combination of both.

Further, the gate 16 constituting the delay circuit 12 used in the present invention is not limited to the buffer shown in FIG. 2, and any kind of inverter, NAND gate, AND gate, NOR gate, OR gate, etc. can be used. May be used, or these may be used in combination. Further, the connection method of the gate 16 is not limited to series connection, and any method can be used as long as a predetermined delay can be created and a delay time of a half cycle of the system clock a is obtained under the worst condition of guaranteed operation or the maximum allowable temperature. It may be connected as described above, or may be appropriately selected according to the type of gate. Further, a gate such as an inverter or a buffer may be combined with a capacitor or a resistor.

The flip-flop 14 is a D-type flip-flop which has a D input terminal and a T (or G) input terminal as input terminals and has at least one of a Q output terminal and a Q bar output terminal as an output terminal. The output terminal of the delay circuit 12 is connected to the D input terminal, and the delay signal b is input. On the other hand, the system clock a is directly input to the T input terminal. This D-type flip-flop 1
4, the positive edge trigger type outputs the data input from the D input terminal, that is, the delayed signal b at the rising edge of the clock T input, that is, the system clock a at the same time as reading, as shown in FIG. Therefore, if the clock T input, that is, the system clock a rises when the D input, that is, the delay signal b is high (H "1"), the Q output is H, and the D input (the delay signal b) is low (L "0"). When the clock T input (system clock a) rises at "", the Q output is L.

Therefore, the flip-flop 14 shown in FIG.
Is a delayed signal b which is the output of the delay circuit 12 with respect to the system clock a input from the T terminal as shown in FIG.
Is delayed by a delay time (td) longer than the half cycle (T / 2) of the siltem clock a, its Q output, that is, the dangerous signal c is changed from L to H, and the delay time (td)> half cycle (T /
2), the output Q (danger signal c) maintains the H state, and the delay time td of the delay signal b is equal to the system clock a.
The output Q (danger signal c) changes from H to L when it is less than a half cycle (T / 2) of Q, and Q is maintained while td ≦ T / 2.
The output (danger signal c) is kept in the L state. Therefore, the danger signal c
Is H while delay time td> half period (T / 2)
(“1”) is reached, and it is detected that the temperature rise has exceeded the allowable range, and a danger signal is emitted. Of course, the inverted output Q bar of the output Q may be output as the danger signal c.

The danger signal c from the flip-flop 14 becomes H.
In a semiconductor integrated circuit such as an LSI in which the temperature rise detection circuit 10 is incorporated, the circuit that consumes the most power and therefore generates the most heat is shut off or the bypass circuit is used. Therefore, by bypassing the circuit, the temperature of the LSI is prevented from further increasing, and the circuit is energized and the predetermined operation is performed only when the temperature of the LSI falls within the allowable range. do it. For this reason, the upper limit of the allowable range of temperature rise may be set with a sufficient margin in the allowable conditions of the semiconductor integrated circuit such as the LSI to be incorporated. Here, the flip-flop 14 used in the present invention is a positive edge trigger type D flip-flop shown in FIG. 1, but the present invention is not limited to this, and a negative edge trigger type master flip-flop is used.
It may be either a slave type or a master / slave data lockout type, or may realize the above-mentioned function by a JK flip-flop, an RS flip-flop, a D latch or another logic circuit configuration. Good.

FIG. 4 shows an embodiment in which the temperature rise detection circuit 10 of the present invention is applied to an adaptive digital filter. The digital filter 20 includes an FIR (finite impulse response) filter 28 including a plurality (for example, M) of delay elements 22, a plurality (for example, M + 1) of multipliers 24, and a plurality (for example, M) of adders 26. , And a control circuit 32 for setting the coefficient C _i (i = 0, 1, ..., M) to be output to the multiplier 24. Here, each of these circuits is composed of a plurality of gates. FIR filter 28
The temperature detection circuit 10 of the present invention is incorporated in the vicinity of the multiplier 24. The digital filter 20 obtains an output signal y _n by performing the calculation of the following equation to remove noise and the like from the input signal x _n .

[0024]

[Equation 1]

The system clock a is the FIR filter 2
8 delay element 22, multiplier 24, adder 26, adder 30 and control circuit 32, and are used as reference clocks. The control circuit 32 sets M + 1 coefficients C _i (i = 0, 1, ...,) set in the M + 1 multipliers 24.
M) is set and the filtering of the digital filter 20 is appropriately controlled. The danger signal c output from the temperature rise detection circuit 10 of the present invention is input to the control circuit 32.

In the digital filter 20, the power consumption is determined by the coefficient C _i (i = 0,
1, ..., M) to a large extent and may be determined by this coefficient C _i . Here, since the power consumption in the multiplier 24 is large and therefore the heat generation is large, the temperature of the digital filter 20 may exceed the allowable temperature rise range of the operating condition. At this time, heat is also transferred to the temperature rise detection circuit 10 of the present invention which is provided adjacently, and exceeds the allowable temperature rise range described above, and the gate of the delay circuit 12 outputs the input system clock a to its half cycle ( Output as a delay signal b having a delay time td exceeding T / 2). Therefore, the flip-flop 14 receives the delay signal b and outputs the dangerous signal c in the H state.

The danger signal thus output from the temperature detection circuit 10 is input to the control circuit 32. Control circuit 32
Limits the coefficient C _i given to the multiplier 24 and suppresses heat generation of the multiplier 24. As a result, the temperature of the multiplier 24, that is, the temperature of the digital filter 20 and the temperature rise detection circuit 10 returns to within the allowable range. By performing such control, the multiplier 2 composed of a plurality of gates
It is possible to always perform stable operation without causing malfunction or destruction of 4.

[0028]

As described in detail above, according to the present invention,
In the operating state, it is possible to detect a temperature rise in a semiconductor integrated circuit such as an LSI, and as a result, it is possible to prevent malfunction or destruction of the semiconductor integrated circuit due to the temperature rise.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a temperature rise detection circuit according to the present invention.

FIG. 2 is a configuration diagram of an embodiment of a delay circuit used in the temperature rise detection circuit according to the present invention.

FIG. 3 is a time chart of signals and temperatures of respective parts of the temperature rise detection circuit shown in FIG.

FIG. 4 is a configuration diagram of an embodiment of a digital filter to which the temperature rise detection circuit of the present invention is applied.

[Explanation of symbols]

 10 Temperature Rise Detection Circuit 12 Delay Circuit 14 Flip-Flop 16 Gate (Buffer) 20 Digital Filter (ICR Type) 22 Delay Element 24 Multiplier 26, 30 Adder 28 FIR Type (Digital) Filter 32 Control Circuit

Claims (4)

[Claims] 1. A temperature rise detection circuit used by being incorporated in a semiconductor integrated circuit, the delay circuit delaying a reference clock of a predetermined frequency, and a flip-flop having the reference clock and an output signal of the delay circuit as inputs. And a temperature rise detection circuit, wherein the flip-flop outputs a danger signal when the delay of the delay circuit due to a temperature rise exceeds a predetermined value. 2. The temperature rise detection circuit according to claim 1, wherein the flip-flop outputs a danger signal when the delay of the delay circuit becomes larger than a half cycle of the reference clock. 3. The temperature rise detection circuit according to claim 1, wherein the delay circuit has a plurality of gates connected in stages. 4. The number of stages of gates constituting the delay circuit is
4. The temperature rise detection circuit according to claim 3, wherein the delay time matches the half cycle of the reference clock under the worst condition of guaranteeing the operation of the semiconductor integrated circuit.