JPH0591440A - Television signal processing circuit - Google Patents
Television signal processing circuitInfo
- Publication number
- JPH0591440A JPH0591440A JP3247756A JP24775691A JPH0591440A JP H0591440 A JPH0591440 A JP H0591440A JP 3247756 A JP3247756 A JP 3247756A JP 24775691 A JP24775691 A JP 24775691A JP H0591440 A JPH0591440 A JP H0591440A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- image
- frame
- contour
- contour correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Television Systems (AREA)
- Details Of Television Scanning (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＮＴＳＣ方式、高品位
テレビジョン方式などが受信できるテレビジョン信号受
信機に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television signal receiver capable of receiving the NTSC system, high definition television system and the like.
【０００２】[0002]
【従来の技術】近年、現行のＮＴＳＣ方式の持つアスペ
クト比４：３とは異なるアスペクト比（１６：９）を持
つ高品位テレビジョン方式が普及しようとしている。こ
のような高品位テレビジョン方式の普及に際しても、高
品位テレビジョン信号が受信出来ることはもちろんのこ
と、アスペクト比の異なる現行のテレビジョン信号が受
信できることが望ましい。１６：９の受信機に４：３の
画像を表示する信号処理装置の例として、特開平２−１
０８３７７などが上げられる。この場合、図５に示すよ
うに１６：９の画面の中に、左右映像の無い部分（図５
において斜線で示す。）を設けて４：３の映像を表示す
るものである。このような映像を得るための信号処理の
一例を図６に示す。同図において１０２はＡ／Ｄコンバ
ータ、１０３はＹ／Ｃ分離回路、１０４は色復調回路、
１０５及び１０６は走査線補間回路、１０７及び１０８
倍速変換回路、１０９及び１１０は時間軸圧縮回路、１
１１、１１２及び１１３は枠レベル発生回路、１１４、
１１５及び１１６は切り換え回路、１１７、１１８及び
１１９はＤ／Ａコンバータ、６０１は輝度信号出力端
子、６０２及び６０３はＲ−Ｙ及びＢ−Ｙ出力端子、１
２１は同期発生回路、１２２は枠位置発生回路である。
図６において、１６：９から４：３に変換する部分は、
主に時間軸圧縮回路である。この動作を図７を用いて説
明する。同図において（ａ）は、時間軸圧縮回路１０９
の入力信号である。時間軸圧縮回路１０９では、時間軸
を３／４に圧縮し４：３の映像を得る（図７（ｂ））。
枠レベル発生回路１１１では図５の斜線で示した部分
（枠）のレベルを得る。枠位置発生回路１２２では、図
５の枠の位置に相当するパルス（図７（ｃ）に示す。）
を発生し、枠レベル発生回路１１１で得た枠レベルと時
間軸圧縮回路出力信号を切り換え回路１１４で切り換え
て、図７（ｄ）のような信号を得る。2. Description of the Related Art In recent years, a high-definition television system having an aspect ratio (16: 9) different from the aspect ratio 4: 3 of the current NTSC system has been spreading. Even when such a high-definition television system spreads, it is desirable that not only high-definition television signals can be received, but also current television signals having different aspect ratios can be received. As an example of a signal processing device for displaying a 4: 3 image on a 16: 9 receiver, Japanese Patent Application Laid-Open No. 2-1.
08377 etc. are raised. In this case, as shown in FIG. 5, in the 16: 9 screen, the part without the left and right images (see FIG.
Is indicated by diagonal lines. ) Is provided to display a 4: 3 image. An example of signal processing for obtaining such an image is shown in FIG. In the figure, 102 is an A / D converter, 103 is a Y / C separation circuit, 104 is a color demodulation circuit,
Reference numerals 105 and 106 denote scanning line interpolation circuits, and 107 and 108.
Double speed conversion circuit, 109 and 110 are time axis compression circuit, 1
11, 112 and 113 are frame level generation circuits, 114,
115 and 116 are switching circuits, 117, 118 and 119 are D / A converters, 601 is a luminance signal output terminal, 602 and 603 are RY and BY output terminals, 1
Reference numeral 21 is a synchronization generation circuit, and 122 is a frame position generation circuit.
In FIG. 6, the part converted from 16: 9 to 4: 3 is
Mainly a time axis compression circuit. This operation will be described with reference to FIG. In the figure, (a) shows the time base compression circuit 109.
Input signal of. The time axis compression circuit 109 compresses the time axis to 3/4 to obtain a 4: 3 image (FIG. 7B).
The frame level generation circuit 111 obtains the level of the shaded portion (frame) in FIG. In the frame position generation circuit 122, a pulse corresponding to the position of the frame in FIG. 5 (shown in FIG. 7C).
Is generated and the frame level obtained by the frame level generation circuit 111 and the time axis compression circuit output signal are switched by the switching circuit 114 to obtain a signal as shown in FIG. 7 (d).
【０００３】[0003]
【発明が解決しようとする課題】図５に示したように、
１６：９の画面の中に４：３の映像を表示した場合に
は、左右に絵の無い部分（枠）ができ、映像部と枠の部
分の輝度差によって、ＣＰＴのマスクが変形して映像部
と枠の境界に縦筋が残る、いわゆる焼き付き現象が起こ
る。この問題を解決するために、枠のレベルは、表示画
像の平均輝度レベルを表示することを行なっている。し
かし、一般的に、図６に示した枠レベルの付随した輝度
信号出力端子６０１、色差信号出力端子６０２、６０３
の後段には、図８に示した回路が接続される。輝度信号
は、輪郭補正回路８０４が接続される。輪郭補正回路８
０４の入出力信号を図９（ａ），（ｂ）にそれぞれ示
す。輪郭補正回路を通した場合は、同図（ｂ）に示した
ように、映像と枠の境界を強調するために、境界部分に
シュートが付き枠と映像の輝度差が大きくなり、焼き付
き現象が生じてしまう。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As shown in FIG.
When a 4: 3 image is displayed on a 16: 9 screen, there is a pictureless part (frame) on the left and right, and the CPT mask is deformed due to the brightness difference between the image part and the frame part. A so-called burn-in phenomenon occurs in which vertical stripes remain at the boundary between the image part and the frame. In order to solve this problem, the level of the frame displays the average brightness level of the display image. However, generally, the luminance signal output terminal 601 and the color difference signal output terminals 602 and 603 with the frame level shown in FIG.
The circuit shown in FIG. 8 is connected to the subsequent stage. A contour correction circuit 804 is connected to the luminance signal. Contour correction circuit 8
The input / output signals of 04 are shown in FIGS. 9 (a) and 9 (b), respectively. In the case of passing through the contour correction circuit, as shown in (b) of the same figure, in order to emphasize the boundary between the image and the frame, a shoot is attached to the boundary portion, and the difference in brightness between the frame and the image becomes large, and the burn-in phenomenon occurs. Will occur.
【０００４】本発明の目的は、画像の輪郭補正を行なっ
ても、焼き付き現象の生じない信号処理回路を提供する
ことにある。An object of the present invention is to provide a signal processing circuit which does not cause a burn-in phenomenon even when the contour of an image is corrected.
【０００５】[0005]
【課題を解決するための手段】上記問題を解決するため
に本発明では、映像と枠の境界に対応したパルスを求め
る輪郭補正制御パルス発生回路と、前記パルスによって
輪郭補正回路をＯＦＦする輪郭補正制御回路から構成さ
れる。In order to solve the above problems, according to the present invention, a contour correction control pulse generation circuit for obtaining a pulse corresponding to a boundary between an image and a frame, and a contour correction for turning off the contour correction circuit by the pulse. It is composed of a control circuit.
【０００６】[0006]
【作用】前記輪郭補正制御パルス発生回路は、映像と枠
の境に位置するパルスを発生する。前記輪郭補正制御回
路は、前記パルスによって、映像と枠の境の期間におい
て、輪郭補正回路をＯＦＦする。従って、映像と枠の境
に生じるシュートが無くなるので、焼き付き現象が起こ
ることが無い。The contour correction control pulse generating circuit generates a pulse located at the boundary between the image and the frame. The contour correction control circuit turns off the contour correction circuit in the period between the image and the frame by the pulse. Therefore, there is no shoot occurring at the boundary between the image and the frame, and the burn-in phenomenon does not occur.
【０００７】[0007]
【実施例】以下図面を用いて本発明を説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【０００８】図１は、本発明による、第一の実施例を示
すブロック図である。本実施例は、ＥＤ（Ｅｎｈａｎｃ
ｅｄ Ｄｅｆｉｎｉｔｉｏｎ）ＴＶに本発明を適用した
例である。同図において、１０１はコンポジットビデオ
入力端子、１０２はＡ／Ｄコンバータ、１０３はＹ／Ｃ
分離回路、１０４は色復調回路、１０５、１０６は走査
線補間回路、１０７、１０８は倍速変換回路、１０９、
１１０は時間軸圧縮回路、１１１，１１２及び１１３は
枠レベル発生回路、１１４，１１５及び１１６は切り換
え回路、１１７、１１８及び１１９はＤ／Ａコンバー
タ、１２０は輪郭補正回路、１２１は同期発生回路、１
２２は枠位置パルス発生回路、１２３は輪郭補正制御パ
ルス発生回路、１２４はマトリックス回路、１２５、１
２６、１２７はＲＧＢ出力端子である。FIG. 1 is a block diagram showing a first embodiment according to the present invention. This embodiment is based on ED (Enhance).
This is an example in which the present invention is applied to an ed Definition) TV. In the figure, 101 is a composite video input terminal, 102 is an A / D converter, and 103 is a Y / C.
Separation circuit, 104 color demodulation circuit, 105 and 106 scanning line interpolation circuit, 107 and 108 double speed conversion circuit, 109 and
110 is a time axis compression circuit, 111, 112 and 113 are frame level generation circuits, 114, 115 and 116 are switching circuits, 117, 118 and 119 are D / A converters, 120 is a contour correction circuit, 121 is a synchronization generation circuit, 1
22 is a frame position pulse generation circuit, 123 is a contour correction control pulse generation circuit, 124 is a matrix circuit, 125, 1
26 and 127 are RGB output terminals.
【０００９】本回路の基本的動作を以下に説明する。コ
ンポジットビデオ入力端子に入力されたコンポジットビ
デオ信号は、Ａ／Ｄコンバータ１０２でディジタル値に
変換される。Ｙ／Ｃ分離回路１０３では、コンポジット
ビデオ信号から、輝度信号Ｙと色信号Ｃを分離する。色
信号Ｃは、色復調回路１０４において色差信号Ｒ−Ｙ及
びＢ−Ｙ信号に変換される。走査線補間回路１０５，１
０６、倍速変換回路１０７、１０８では、インタレース
信号からノンインタレース信号に変換される。時間軸圧
縮回路１０９，１１０では、４：３用に映像を圧縮す
る。枠レベル発生回路では、焼き付き現象が起きないよ
うに映像信号の平均値（例えば積分回路などで実現でき
る。）を出力する。時間軸圧縮回路１０９、１１０の出
力と、枠レベル発生回路１１１，１１２及び１１３の出
力は、切り換え回路１１４，１１５及び１１６におい
て、枠位置パルス発生回路１２２から出力されるパルス
によって切り換えられる。Ｄ／Ａコンバータ１１７、１
１８及び１１９によってアナログ値に変換された後、輝
度信号は輪郭補正回路１２０を通り、色差信号はそのま
まマトリックス回路１２４へ入力される。輪郭補正回路
１２０では、輪郭部を強調するために輪郭部にシュート
を付けると同じに、輪郭補正制御パルス発生回路１２３
から出力されるパルスによって映像と枠の境のシュート
を無くすよう輪郭補正回路をＯＦＦする。マトリックス
回路１２４ではＲＧＢ信号に変換し表示装置（ディスプ
レイ等、図示せず。）に出力する。The basic operation of this circuit will be described below. The composite video signal input to the composite video input terminal is converted into a digital value by the A / D converter 102. The Y / C separation circuit 103 separates the luminance signal Y and the color signal C from the composite video signal. The color signal C is converted into color difference signals RY and BY signals in the color demodulation circuit 104. Scan line interpolation circuit 105, 1
06, the double speed conversion circuits 107 and 108 convert the interlaced signal into a non-interlaced signal. The time axis compression circuits 109 and 110 compress the video for 4: 3. The frame level generation circuit outputs the average value of the video signal (which can be realized by, for example, an integrating circuit) so that the burn-in phenomenon does not occur. The outputs of the time axis compression circuits 109 and 110 and the outputs of the frame level generation circuits 111, 112 and 113 are switched in the switching circuits 114, 115 and 116 by the pulse output from the frame position pulse generation circuit 122. D / A converter 117, 1
After being converted into an analog value by 18 and 119, the luminance signal passes through the contour correction circuit 120, and the color difference signal is directly input to the matrix circuit 124. In the contour correction circuit 120, the contour correction control pulse generation circuit 123 is the same as when a chute is added to the contour portion in order to emphasize the contour portion.
The contour correction circuit is turned off so as to eliminate the shoot at the boundary between the image and the frame by the pulse output from the. The matrix circuit 124 converts the signals into RGB signals and outputs them to a display device (display or the like, not shown).
【００１０】輪郭補正回路１２０の動作を図２を用いて
説明する。同図において、（ａ）は輪郭補正回路の入力
信号である。今、同図に示すよう映像が白から黒、黒か
ら白へ変わるような場合を考える。輪郭補正回路では、
通常は、同図（ｂ）に示すよう枠と映像、白と黒、黒と
白の境にシュートを付けて輪郭を強調する。従って、こ
のままでは、枠と映像の境の輝度差が大きくなり焼き付
き現象が起きてしまう。輪郭補正制御パルス発生回路１
２３では、図２（ｃ）に示すよう映像と枠の境に位置す
るパルスを発生する。輪郭補正回路１２０では、このパ
ルスが”Ｈ”の期間輪郭補正動作をＯＦＦする。従っ
て、図２（ｄ）に示すよう、映像の輪郭強調は行なった
まま、映像と枠の境のシュートを無くすことが出来るの
で焼き付き現象を防止することができる。The operation of the contour correction circuit 120 will be described with reference to FIG. In the figure, (a) is an input signal of the contour correction circuit. Now, consider the case where the image changes from white to black and from black to white as shown in FIG. In the contour correction circuit,
Normally, as shown in FIG. 3B, the outline is emphasized by adding shoots to the frame and the image, white and black, and the boundary between black and white. Therefore, if this is left as it is, the difference in brightness between the frame and the image becomes large, and the burn-in phenomenon occurs. Contour correction control pulse generation circuit 1
At 23, a pulse positioned at the boundary between the image and the frame is generated as shown in FIG. In the contour correction circuit 120, the contour correction operation is turned off while this pulse is "H". Therefore, as shown in FIG. 2D, it is possible to eliminate the shoot at the boundary between the image and the frame while the outline of the image is being emphasized, so that the burn-in phenomenon can be prevented.
【００１１】図３に輪郭補正回路１２０の一具体例のブ
ロック図を示す。同図ににおいて、３０１は輪郭補正回
路入力端子、３０２、３０３は遅延素子、３０４、３０
５、３０６は乗算器、３０７、３１０は加算器、３０８
は可変乗算器、３０９は切り換え回路、３１１は輪郭補
正出力端子、３１２は輪郭補正制御パルス入力端子であ
る。可変乗算器３０８からは、画像の輪郭成分が出力さ
れる。輪郭補正制御パルス入力端子３１２からは、図２
（ｃ）に示すようなパルスが入力される。このパルス
が”Ｈ”の期間、切り換え回路３０９は”０”を選択す
るので、加算器３１０からは、この期間輪郭強調されな
い信号が出力される。従って、映像と枠の境には、シュ
ートが付かない。輪郭補正制御パルスが”Ｈ”の期間乗
算器の係数Ｋを０にしても同様の効果が得られる。ま
た、輪郭補正回路は、図１に示した、Ｄ／Ａコンバータ
１１７の前に挿入されてディジタル的に輪郭補正を行な
った場合においても同様な効果が得られる。FIG. 3 shows a block diagram of a specific example of the contour correction circuit 120. In the figure, 301 is a contour correction circuit input terminal, 302 and 303 are delay elements, and 304 and 30.
5, 306 are multipliers, 307, 310 are adders, 308
Is a variable multiplier, 309 is a switching circuit, 311 is a contour correction output terminal, and 312 is a contour correction control pulse input terminal. The variable multiplier 308 outputs the contour component of the image. 2 from the contour correction control pulse input terminal 312.
A pulse as shown in (c) is input. Since the switching circuit 309 selects "0" during the period in which this pulse is "H", the adder 310 outputs a signal whose contour is not emphasized during this period. Therefore, there is no shoot at the boundary between the image and the frame. The same effect can be obtained by setting the coefficient K of the multiplier to 0 while the contour correction control pulse is "H". Further, the contour correction circuit has the same effect when it is inserted in front of the D / A converter 117 and digitally performs contour correction as shown in FIG.
【００１２】図４に本発明による第二の実施例のブロッ
ク図を示す。同図において４０１は輝度信号入力端子、
４０２，４０３は色差信号入力端子、４０４はマトリッ
クス回路、４０５はブラウン管、４０６は速度変調コイ
ル、４０７は微分回路、４０８は増幅器、４０９は速度
変調御回路、４１０は速度変調制御パルス入力端子、４
１１、４１２は抵抗、４１３はトランジスタである。輪
郭を強調する回路として、輪郭部の走査速度を変調して
行なう方法がある。図４は、速度変調回路に本発明を適
用した例である。入力端子４０１，４０２，４０３は、
これまでの例と同様に、４：３の映像用に枠の付いた信
号が入力される。微分回路４０７では、輪郭信号が出力
される。増幅器４０８では、微分信号を増幅し、速度変
調用コイル４０６を駆動する。速度変調制御回路４０９
は、速度変調制御パルス入力端子４１０から入力され
る、映像と枠の境に位置するパルスによって、微分回路
４０７の出力を”０”とする。従って、映像と枠の境に
おいては速度変調が効かないので輪郭強調されない。よ
って焼き付き現象を防止できる。FIG. 4 shows a block diagram of a second embodiment according to the present invention. In the figure, 401 is a luminance signal input terminal,
402 and 403 are color difference signal input terminals, 404 is a matrix circuit, 405 is a cathode ray tube, 406 is a speed modulation coil, 407 is a differentiation circuit, 408 is an amplifier, 409 is a speed modulation control circuit, and 410 is a speed modulation control pulse input terminal.
Reference numerals 11, 412 are resistors, and 413 is a transistor. As a circuit for emphasizing the contour, there is a method of modulating the scanning speed of the contour portion. FIG. 4 is an example in which the present invention is applied to a speed modulation circuit. The input terminals 401, 402, 403 are
As in the previous examples, a framed signal for 4: 3 video is input. The differentiating circuit 407 outputs the contour signal. The amplifier 408 amplifies the differential signal and drives the velocity modulation coil 406. Speed modulation control circuit 409
Sets the output of the differentiating circuit 407 to “0” by the pulse input from the speed modulation control pulse input terminal 410 and located at the boundary between the image and the frame. Therefore, since the velocity modulation does not work at the boundary between the image and the frame, the contour is not emphasized. Therefore, the image sticking phenomenon can be prevented.
【００１３】以上の実施例は、ＥＤＴＶに適用した例を
示したが、標準速用のＴＶに適用しても同様の効果が得
られる。Although the above embodiment shows an example applied to an EDTV, the same effect can be obtained when applied to a standard speed TV.
【００１４】[0014]
【発明の効果】以上により、輪郭補正回路を接続した場
合においても、映像と枠に境は、シュートが付かず輪郭
を強調することが無いので、映像の輪郭は強調したまま
で、焼き付き現象も防止できる。As described above, even when the contour correction circuit is connected, since there is no chute at the boundary between the image and the frame and the contour is not emphasized, the contour of the image remains emphasized and a burn-in phenomenon occurs. It can be prevented.
【図１】本発明による第一の実施例を示すブロック図FIG. 1 is a block diagram showing a first embodiment according to the present invention.
【図２】図１の動作を示す波形図。FIG. 2 is a waveform chart showing the operation of FIG.
【図３】図１の輪郭補正回路の一具体例を示すブロック
図。3 is a block diagram showing a specific example of the contour correction circuit of FIG.
【図４】本発明による第二の実施例を示すブロック図。FIG. 4 is a block diagram showing a second embodiment according to the present invention.
【図５】１６：９の画面に４：３の映像を表示した場合
の状態図。FIG. 5 is a state diagram when a 4: 3 image is displayed on a 16: 9 screen.
【図６】従来例を示すブロック図。FIG. 6 is a block diagram showing a conventional example.
【図７】図６の動作を示す波形図。7 is a waveform chart showing the operation of FIG.
【図８】従来例を示すブロック図。FIG. 8 is a block diagram showing a conventional example.
【図９】図８の動作を示す波形図。9 is a waveform diagram showing the operation of FIG.
１０９、１１０…時間軸圧縮回路、 １１１、１１２、１１３…枠レベル発生回路、 １１４、１１５、１１６…切り換え回路、 １２０…輪郭補正回路、 １２２…枠位置発生回路、 １２３…輪郭補正制御パルス発生回路。 109, 110 ... Time axis compression circuit, 111, 112, 113 ... Frame level generation circuit, 114, 115, 116 ... Switching circuit, 120 ... Contour correction circuit, 122 ... Frame position generation circuit, 123 ... Contour correction control pulse generation circuit .
───────────────────────────────────────────────────── フロントページの続き (72)発明者 窪田 定雄 神奈川県横浜市戸塚区吉田町292番地株式 会社日立製作所ＡＶ機器事業部内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sadao Kubota 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi Ltd. AV equipment division
Claims (2)
標準テレビジョン信号を表示するテレビジョン信号処理
回路において、４：３に時間軸圧縮する時間軸圧縮回路
と、映像の無い部分（枠）のレベルを出力する枠レベル
発生回路と、前記時間軸圧縮回路の出力と前記枠レベル
発生回路の出力を切り換える切り換え回路と、前記切り
換え回路を制御するべく枠の位置に対応したパルスを発
生する枠位置発生回路と、前記切り換え回路の後段に接
続される輪郭補正回路と、前記輪郭補正回路を制御する
べく映像と枠の輪郭部の位置にに対応したパルスを発生
する輪郭補正制御パルス発生回路と、輪郭補正制御回路
を具備したことを特徴とするテレビジョン信号処理回
路。1. A television signal processing circuit for displaying a standard television signal of 4: 3 on a 16: 9 television receiver, and a time axis compression circuit for time axis compression of 4: 3, and a portion having no image. A frame level generation circuit that outputs the level of (frame), a switching circuit that switches the output of the time axis compression circuit and the output of the frame level generation circuit, and a pulse that corresponds to the position of the frame to control the switching circuit. A frame position generation circuit for generating, a contour correction circuit connected to the latter stage of the switching circuit, and a contour correction control pulse for generating a pulse corresponding to the position of the image and the contour portion of the frame to control the contour correction circuit. A television signal processing circuit comprising a generation circuit and a contour correction control circuit.
と、偏向速度変調用のコイルとから構成されることを特
徴とする請求項１のテレビジョン信号処理回路。2. The television signal processing circuit according to claim 1, wherein the contour correction circuit comprises a differentiating circuit, an amplifier, and a coil for deflection speed modulation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24775691A JP3147428B2 (en) | 1991-09-26 | 1991-09-26 | Television signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24775691A JP3147428B2 (en) | 1991-09-26 | 1991-09-26 | Television signal processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0591440A true JPH0591440A (en) | 1993-04-09 |
| JP3147428B2 JP3147428B2 (en) | 2001-03-19 |
Family
ID=17168198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24775691A Expired - Fee Related JP3147428B2 (en) | 1991-09-26 | 1991-09-26 | Television signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3147428B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6297854B1 (en) | 1997-03-25 | 2001-10-02 | Fujitsu General Limited | Contour emphasizing circuit |
-
1991
- 1991-09-26 JP JP24775691A patent/JP3147428B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6297854B1 (en) | 1997-03-25 | 2001-10-02 | Fujitsu General Limited | Contour emphasizing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3147428B2 (en) | 2001-03-19 |
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