JPH0552972A - Frequency distribution measuring circuit - Google Patents

Abstract

PURPOSE:To remove an increase in the capacity of a memory by adding a counter for delaying packet start, a register for setting delay, a coincidence circuit for detecting delay, the frequency divider of a flip flop for storing a detection result, a counter and a memory for storing frequency. CONSTITUTION:A counter 2 has function for delaying measurement start time and this delay is determined on the basis of the clock frequency set by a register 3. A counter 10 takes the AND of the output of a flip-flop 7 and a clock to count a burst clock. The value obtained by counting a packet interval by the counter 10 is sent to a frequency memory 6 through a multiplexer 4 and the memory 6 stores the frequency of the count value but does not store a part showing no change. By this constitution, since counting is started from an arbitrary start point, a measured result of high resolving power is obtained even by a memory of definite capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet interval measuring device in a packet switching network.

[0002]

2. Description of the Related Art In a packet switching network, when the transfer delay time of each packet is statistically processed and the result is to be displayed in real time, it has been conventionally constructed as shown in FIG. Here, 2 is a counter that is counted by a clock that measures the packet transfer interval, is reset at the start point of the next packet, and has a final value that indicates the packet transfer interval. Reference numeral 6 is a memory that stores the frequency with the packet transfer interval as a parameter. Reference numeral 11 is an adder for counting the frequency, and 1 is a read counter for reading the stored frequency for display, which is counted by a clock synchronized with the external display device. 4 is a multiplexer. In the memory 6, the count value of the counter 2 is connected to the address input, and the output of the adder 11 is input and stored as frequency information.

[0003]

Since the conventional frequency distribution measuring circuit has the above-mentioned configuration, the memory capacity increases if the variation in the packet transfer interval is large, and the delay time measurement resolution is increased. Then, there is a drawback that the memory capacity is also increased.

It is an object of the present invention to provide a frequency distribution measuring circuit capable of eliminating the disadvantage that the capacity of the memory becomes large when measuring the packet interval delay time with high accuracy.

[0005]

In order to achieve this object, a frequency distribution measuring circuit according to the present invention has a structure in which the start point of a packet interval delay time counting counter can be started from an arbitrary time. Is.

[0006]

The present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, in which 1 is a counter for reading the contents of a memory storing a frequency distribution to an external display device or a microcomputer, and 2 is a clock for counting packet intervals. Then, a counter 3 which is reset when the packet starts is a register which stores how much the packet interval is delayed from the packet start point, and the value is set by a microcomputer or the like. 5 is a matching circuit that outputs an output when the contents of the counter 2 and the register 3 match, 7 is a flip-flop that holds the output and is reset at the start point of the next packet, and 8 is a clock for counting the packet interval This is a 1 / N counter that determines whether to make a round, and the value of N is given in advance by a microcomputer. Reference numeral 9 is an AND gate circuit that outputs the clock of the 1 / N counter 8 while the output of the flip-flop is "1". Reference numeral 10 is a counter that starts counting when the counter 2 delays the start of counting. Reference numeral 4 is counter 1
A multiplexer for switching between 0 and the output of the counter 1, 6 is a memory which is accessed by the count value of the counter 10 and stores the frequency distribution, and 11 is an adder for counting the frequency.

Hereinafter, FIG. 1 will be described using the time chart of FIG.
The operation of the embodiment will be described. FIG. 2 shows signals of various parts in one embodiment of the present invention. Time chart (a)
Is a packet to be measured, and the packet intervals are T1, T2, T3 ... Tn. Counter 2 and counter 10 and flip-flop 7 upon packet reception
To reset. FIG. 2B shows the reset timing. The counter 2 delays the measurement start time, and the delay is determined by the clock frequency input to the counter 2 (the value set in the register 3 by a microcomputer or the like). For example, clock frequency 1kHz
When the value of register 3 is set to 100 in 1
The coincidence signal (b) is output from the coincidence circuit 5 at 00 ms,
Flip-flop 7 is set. That is, it is possible to obtain a certain delay after receiving the packet. TA of (d)
Is the delay time. The counter 10 ANDs the output of the flip-flop 7 which becomes "1" after a certain delay and the clock.
It is counted by the burst-shaped clock that is taken. The count value is T1-TA, T2-for each packet.
It becomes TA, T3-TA, ... Tn-TA and is input as address information of the memory 6 for storing the frequency. The clock for counting the counter 10 can count down the frequency by 1 / N by the 1 / N counter 8, and the count value in that case is (T1 / N) -TA, (T2 / N) -TA,
(T3 / N) -TA ... (Tn / N) -TA, and the number of bits required by the counter 10 can be further reduced. However, in this case, the measurement resolution of time drops to 1 / N. The time charts (e) and (f) show the counter 10
It is a clock signal input to. The value obtained by counting each packet interval by the counter 10 is sent to the frequency storage memory 6 through the read counter 1 and the multiplexer 4 for switching. The count value is given as address information of the frequency storage memory 6, and when an address is designated, the data corresponding to the address is read. The data is incremented by "1" by the adder 11. The increased data is written to the same address by the read / write signal. As a result, the frequency of the counted value is stored in the memory 6.

With such a structure, in the conventional circuit, the time variation of a normal packet is smaller than the packet interval, so that the frequency distribution can be measured only as shown in FIG. 5, and the horizontal axis time resolution is improved. Then, since the count value obtained by measuring the packet interval corresponds to the address of the memory 6, a large capacity memory is required. However, with the configuration of the present embodiment, since the frequency of the part having no fluctuation is not stored in the memory 6, the frequency distribution diagram of the packet interval delay time is measured with high resolution as shown in FIG. 3 with a limited memory capacity. Will be able to.

[0009]

As described above, according to the present invention,
Since counting can be started from an arbitrary start point and counting can be performed with an arbitrary frequency-divided clock, a high-resolution measurement result can be obtained even with a frequency storage memory having a fixed capacity.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the embodiment of FIG.

FIG. 3 is a diagram showing measurement results by the circuit of the present invention.

FIG. 4 is a block diagram showing an example of a conventional frequency distribution circuit.

FIG. 5 is a diagram showing measurement results by a conventional circuit.

[Explanation of symbols]

 1 Read Counter 2, 10 Counter 3 Register 4 Multiplexer 5 Matching Circuit 6 RAM 7 Flip Flop (FF) 8 1 / N Counter 9 AND Circuit 11 Adder

Claims (1)

[Claims] 1. A counter for delaying the start point of each packet, a register for setting a delay, a matching circuit for detecting the delay, a flip-flop for storing the detection result, and a frequency divider for dividing the measurement clock. An AND circuit for gating the divided clock with the output of the flip-flop storing the detection result, a counter for resetting and counting the output pulse from the AND circuit at each packet start point, A frequency distribution measuring circuit comprising a memory for storing the frequency of each counted value and an adder for counting the frequency.