JPH0547973A - Semiconductor chip module - Google Patents
Semiconductor chip moduleInfo
- Publication number
- JPH0547973A JPH0547973A JP3199554A JP19955491A JPH0547973A JP H0547973 A JPH0547973 A JP H0547973A JP 3199554 A JP3199554 A JP 3199554A JP 19955491 A JP19955491 A JP 19955491A JP H0547973 A JPH0547973 A JP H0547973A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- chip module
- chips
- heat sink
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 230000017525 heat dissipation Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、コンピュータや通信な
どの信号処理の高速化が要求される分野に適用できるマ
ルチチップモジュール、シングルチップモジュールなど
の半導体チップを搭載した半導体チップモジュールに関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip module having a semiconductor chip such as a multi-chip module or a single chip module, which is applicable to a field requiring high speed signal processing such as computer and communication. ..
【０００２】[0002]
【従来の技術】電子機器の機能の大規模化および高速化
が求められるにつれ、論理ＬＳＩゲート１個当りの遅延
時間は数百ｐｓと高速化してきた。それに対して、プリ
ント基板上に多数のＤＩＰやプラグインパッケージを搭
載する従来の実装形態では高速化したＬＳＩの性能を十
分に発揮させることが困難になってきた。そのために、
１枚のセラミック基板上に多くのチップを高密度に搭載
し、高速性能なマルチチップモジュールが開発され実用
されている（ＬＳＩハンドブック、第１版、ｐｐ．４１
５−４１６、電子通信学会、１９８４年）。2. Description of the Related Art With the demand for large-scale and high-speed functions of electronic devices, the delay time per logic LSI gate has been increased to several hundreds ps. On the other hand, in the conventional mounting mode in which a large number of DIPs and plug-in packages are mounted on the printed circuit board, it has become difficult to sufficiently exert the performance of the accelerated LSI. for that reason,
A high-speed multi-chip module has been developed and put into practical use by mounting many chips on one ceramic substrate at high density (LSI Handbook, 1st edition, pp. 41).
5-416, The Institute of Electronics and Communication Engineers, 1984).
【０００３】図４に示されるように、このようなマルチ
チップモジュール方式等において、半導体チップをフェ
イスアップで実装した場合には、図４に示すように半導
体チップ４で発生した熱をＸ方向すなわち基板１側に逃
していた。半導体チップモジュールは、この放熱動作に
より熱抵抗による性能悪化を防いでいた。As shown in FIG. 4, when the semiconductor chips are mounted face up in such a multi-chip module system, the heat generated in the semiconductor chips 4 is transferred in the X direction as shown in FIG. It was missed to the substrate 1 side. The semiconductor chip module has prevented the performance deterioration due to thermal resistance due to this heat radiation operation.
【０００４】[0004]
【発明が解決しようとする課題】しかし、発生した熱を
基板側に逃す方法のみでは、必ずしも十分な放熱を行う
ことができず、半導体チップモジュールの性能は序々に
悪化し、故障率も高くなり、長期間の使用が不可能にな
るという欠点があった。そこで本発明は、性能の悪化が
生じない良好な放熱設計ができる半導体チップモジュー
ルを提供することを目的とする。However, it is not always possible to sufficiently dissipate heat only by the method of releasing the generated heat to the substrate side, the performance of the semiconductor chip module gradually deteriorates, and the failure rate increases. However, there was a drawback that it could not be used for a long time. Therefore, an object of the present invention is to provide a semiconductor chip module capable of a good heat dissipation design without deterioration of performance.
【０００５】[0005]
【課題を解決するための手段】本発明に係る半導体チッ
プモジュールは、配線部が形成されている半導体基板
と、いわゆるフェイスアップですなわち回路面が上向き
になるように実装されて、この配線部上に配置された１
個または複数個の半導体チップと、この半導体チップの
上面中央部に一端部が接触したヒートシンクと、このヒ
ートシンクの他端部を外部に露出させる孔が穿設され、
半導体チップを全て内包するキャップとを備えて構成さ
れるものである。A semiconductor chip module according to the present invention is mounted in a so-called face-up manner on a semiconductor substrate on which a wiring portion is formed, that is, a circuit surface faces upward, and the semiconductor chip module is mounted on the wiring portion. Placed in
One or more semiconductor chips, a heat sink whose one end is in contact with the center of the upper surface of the semiconductor chip, and a hole for exposing the other end of this heat sink to the outside are provided.
And a cap including all the semiconductor chips.
【０００６】[0006]
【作用】本発明に係る半導体チップモジュールによれ
ば、フェイスアップ型の半導体チップから発生した熱は
半導体チップの上面に接触したヒートシンクの一端部か
ら他端部に伝導する。この熱伝導によって、熱はキャッ
プの外部に導かれ、キャップの外で発散される。しか
も、半導体チップの周辺部に配置されたパッドに触れな
いように、フェイスアップ面中央部に接触するようにヒ
ートシンクを設けているので、ヒートシンクによってパ
ッド間がショートするといった問題は全く生じない。According to the semiconductor chip module of the present invention, the heat generated from the face-up type semiconductor chip is conducted from one end of the heat sink contacting the upper surface of the semiconductor chip to the other end. By this heat conduction, heat is guided to the outside of the cap and radiated outside the cap. Moreover, since the heat sink is provided so as to come into contact with the central portion of the face-up surface so as not to touch the pads arranged in the peripheral portion of the semiconductor chip, the problem that the pads are short-circuited by the heat sink does not occur at all.
【０００７】[0007]
【実施例】図１は本発明の実施例に係る半導体チップモ
ジュールの外観を示す斜視図であり、図２は図１に示さ
れた半導体チップモジュールをＩＩ ＩＩ´で切断した
時の断面図である。下部基板１は、例えばアルミナ材で
形成され、その側面からは上部基板６の上に構成された
電気配線と接続した複数のリードピン５が延びている。
上部基板６は低誘電率絶縁材料で形成され、例えば、熱
抵抗３℃／Ｗ、サマーバイヤを併用した３インチ角のポ
リイミド多層配線構造を使用することができる（“銅ポ
リイミド多層配線基板”、ＨＹＢＲＩＤＳ、ＶＯＬ．
７，Ｎｏ．７，ｐｐ．１０−１２参照）。1 is a perspective view showing the appearance of a semiconductor chip module according to an embodiment of the present invention, and FIG. 2 is a sectional view of the semiconductor chip module shown in FIG. 1 taken along line II II '. is there. The lower substrate 1 is made of, for example, an alumina material, and a plurality of lead pins 5 connected to the electric wiring formed on the upper substrate 6 extend from the side surface of the lower substrate 1.
The upper substrate 6 is formed of a low dielectric constant insulating material, and for example, a 3-inch square polyimide multilayer wiring structure having a thermal resistance of 3 ° C./W and a summer bayer can be used (“copper polyimide multilayer wiring substrate”, HYBRIDS). , VOL.
7, No. 7, pp. 10-12).
【０００８】また、下部基板１は、上部基板６よりも大
きい平板で構成され、この下部基板１の上面に上部基板
６が積み重なった状態で固定されている。上部基板６が
重なっていない下部基板１の上面にはキャップ２の縁部
が覆い被せられている。したがって、キャップ２と下部
基板１により上部基板６は内包された状態になってい
る。上部基板６の表面には電極が露出しており、これら
の電極と接続するようにフェイスアップ型半導体チップ
４およびフェイスダウン型半導体チップ４ａが図のよう
に搭載されている。フェイスアップ型半導体チップ４
は、文字通り、回路面が上向きになっており、ボンディ
ングワイヤ法により上部基板６の配線と電気的に接続さ
れている。また、フェイスダウン型半導体チップ４ａ
は、回路面が下側になるようにダイボンディング法等に
より上部基板６の配線と電気的に接続されている。The lower substrate 1 is composed of a flat plate larger than the upper substrate 6, and the upper substrate 6 is fixed on the upper surface of the lower substrate 1 in a stacked state. An edge portion of the cap 2 is covered on the upper surface of the lower substrate 1 where the upper substrate 6 does not overlap. Therefore, the upper substrate 6 is enclosed by the cap 2 and the lower substrate 1. The electrodes are exposed on the surface of the upper substrate 6, and the face-up type semiconductor chip 4 and the face-down type semiconductor chip 4a are mounted as shown in the figure so as to be connected to these electrodes. Face-up type semiconductor chip 4
Literally has a circuit surface facing upward and is electrically connected to the wiring of the upper substrate 6 by a bonding wire method. Also, a face-down type semiconductor chip 4a
Are electrically connected to the wiring of the upper substrate 6 by a die bonding method or the like so that the circuit surface faces downward.
【０００９】また、キャップ２は、例えば、厚さ１ｍｍ
のコバールで蓋状に形成されていて、フェイスアップ型
半導体チップ４およびフェイスダウン型半導体チップ４
ａの搭載位置と対応した位置に、例えば直径３０〜５０
μｍぐらいの孔２ａが穿設されている。これらの穿孔２
ａにヒートシンク３の一端部が挿入される。これらのヒ
ートシンク３は熱導電率の高い材料であるＡｌやＣｕＷ
からなり、挿入部と放熱部で構成されている。挿入部
は、上記の穿孔２ａに挿入しやすい、例えば棒状となっ
ている。また、放熱部は、自動冷却されやすいように表
面積が大きくなる構造で、例えば、円盤上になってい
る。この放熱部は多段になるほど、冷却速度が速くな
る。ヒートシンク３は、このような構成になっているの
でキャップ２の内部への挿入が容易であり、キャップ２
の外部へフェイスアップ型半導体チップに発生した熱を
効率良く逃がすことができる。フェイスアップ型半導体
チップ４からヒートシンク３に熱を効率よく伝えるため
に、ヒートシンク３と半導体チップ４面の接触方法は、
面接触とするのが望ましい。したがって、半導体チップ
４の上面が平面になっている場合、ヒートシンク３の挿
入部の先端は平面になっているのが望ましい。上記ヒー
トシンク３の形成材料がＡｌやＣｕＷのような導体であ
る場合には、ボンディングワイヤ間およびＴＡＢパッド
間のショートが発生しないように、ヒートシンク３の先
端面積を比較的小さくしなければならないが、ＡｌＮや
立方相窒化ほう素（ＣＢＮ）等の絶縁物なら、ボンディ
ングワイヤとの多少の接触はかまわないため、余裕度は
高くなり、設計自由度が高くなる。The cap 2 has a thickness of 1 mm, for example.
Formed in a lid shape by Kovar, and is a face-up type semiconductor chip 4 and a face-down type semiconductor chip 4
At a position corresponding to the mounting position of a, for example, a diameter of 30 to 50
A hole 2a of about μm is formed. These perforations 2
One end of the heat sink 3 is inserted in a. These heat sinks 3 are made of a material having high thermal conductivity such as Al or CuW.
It is composed of an insertion part and a heat dissipation part. The insertion portion has a rod shape, for example, which can be easily inserted into the perforation 2a. Further, the heat radiating portion has a structure having a large surface area so as to be easily automatically cooled, and is, for example, a disk. The cooling speed increases as the number of stages of the heat radiation unit increases. Since the heat sink 3 has such a structure, it can be easily inserted into the inside of the cap 2,
The heat generated in the face-up type semiconductor chip can be efficiently dissipated to the outside of the. In order to efficiently transfer heat from the face-up type semiconductor chip 4 to the heat sink 3, the contact method between the heat sink 3 and the semiconductor chip 4 surface is
Surface contact is desirable. Therefore, when the upper surface of the semiconductor chip 4 is flat, the tip of the insertion portion of the heat sink 3 is preferably flat. When the material forming the heat sink 3 is a conductor such as Al or CuW, the tip area of the heat sink 3 must be made relatively small so that a short circuit between bonding wires and between TAB pads does not occur. Insulators such as AlN and cubic phase boron nitride (CBN) may have some contact with the bonding wires, so that the margin is increased and the design flexibility is increased.
【００１０】図３は、本実施例の半導体チップモジュー
ルに搭載されているフェイスアップ型半導体チップ４の
上面図である。この半導体チップ４の周辺部にはパッド
７が図の破線上に搭載され、中央部にヒートシンク３が
置かれる。この場合、例えば、ボンディングワイヤに２
５μｍΦの金線を使用するとパッドサイズｔ1 は８０μ
ｍ程度にできるので、半導体チップ４の周囲にだけパッ
ド７を並べ、パッド端とチップ端の距離ｔ2 を５０μｍ
とすると片側１３０μｍすなわち両側２６０μｍだけの
狭い場所を除いてヒートシンク３の接触が可能となる。
この構成では、熱抵抗を１０℃／Ｗから５℃／Ｗ程度ま
で低減させることができる。なお、このフェイスアップ
型半導体では、パッド７以外はＳｉＮやＳｉＯＮからな
るパッシベーション膜で保護されているので回路面にヒ
ートシンク３を接触しても性能上の問題は起こらない。FIG. 3 is a top view of the face-up type semiconductor chip 4 mounted on the semiconductor chip module of this embodiment. A pad 7 is mounted on the periphery of the semiconductor chip 4 on the broken line in the figure, and a heat sink 3 is placed in the center. In this case, for example, 2
Pad size t 1 is 80μ when using 5μmΦ gold wire
Since it can be about m, the pads 7 are arranged only around the semiconductor chip 4, and the distance t 2 between the pad end and the chip end is 50 μm.
Then, the heat sink 3 can be contacted except for a narrow place of 130 μm on one side, that is, 260 μm on both sides.
With this configuration, the thermal resistance can be reduced from 10 ° C./W to about 5 ° C./W. In this face-up type semiconductor, since the parts other than the pad 7 are protected by the passivation film made of SiN or SiON, the performance problem does not occur even if the heat sink 3 is brought into contact with the circuit surface.
【００１１】本実施例に係るマルチチップモジュール
は、例えば、半導体チップ４が搭載され、下部基板１に
固定された上部基板６の上面をキャップ２で内包する工
程、ヒートシンク３の一端をキャップ２の穿孔２ａに挿
入し、その先端を半導体チップ４の上面に接触させる工
程、ヒートシンク３と半導体チップ４が接触した状態
で、例えば、キャップの穿孔２ａとヒートシンク３の隙
間に半田を埋め込めることにより、ヒートシンク３をキ
ャップ２に固定する工程を経てパッケージ化される。In the multi-chip module according to the present embodiment, for example, the step of encapsulating the upper surface of the upper substrate 6 fixed to the lower substrate 1 with the cap 2 on which the semiconductor chip 4 is mounted, and one end of the heat sink 3 of the cap 2 are provided. A step of inserting into the hole 2a and bringing the tip thereof into contact with the upper surface of the semiconductor chip 4, in a state where the heat sink 3 and the semiconductor chip 4 are in contact with each other, for example, by embedding solder in a gap between the hole 2a of the cap and the heat sink 3, It is packaged through the process of fixing the heat sink 3 to the cap 2.
【００１２】また、本実施例では、すべての半導体チッ
プ４にヒートシンク３を装着しているが、発熱量が大き
い半導体チップに選択的に装着することができる。この
ように、ヒートシンクは１個の半導体チップに対して１
個装着されるので、基板面からの高さが異なる複数の半
導体チップに対しても、確実にヒートシンクを装着する
ことができる。Further, in the present embodiment, the heat sink 3 is mounted on all the semiconductor chips 4, but it can be selectively mounted on the semiconductor chips which generate a large amount of heat. Thus, one heat sink is used for each semiconductor chip.
Since they are individually mounted, the heat sink can be reliably mounted even on a plurality of semiconductor chips having different heights from the substrate surface.
【００１３】[0013]
【発明の効果】以上、詳細に説明した通り、本発明の構
成によればフェイスアップで実装された半導体チップに
個別にヒートシンクを装着しているので、良好な放熱設
計が可能で高速設計に支障がなく、フェイスアップ実装
方式の半導体チップの熱抵抗の低減を図ることができ
る。しかも、ヒートシンクは選択的に１個の半導体チッ
プに対して１個装着することが可能なので、フェイスア
ップ実装方式の半導体チップおよびフェイスダウン実装
方式の半導体チップが混在するマルチチップモジュール
でもフェイスアップ実装チップの熱抵抗の低減が可能と
なる。As described above in detail, according to the structure of the present invention, since the heat sinks are individually mounted on the semiconductor chips mounted face up, a good heat radiation design is possible and a high speed design is hindered. Therefore, the thermal resistance of the face-up mounting type semiconductor chip can be reduced. Moreover, since one heat sink can be selectively attached to one semiconductor chip, face-up mounting chips can be used even in a multi-chip module in which face-up mounting type semiconductor chips and face-down mounting type semiconductor chips are mixed. It is possible to reduce the thermal resistance of the.
【図１】本実施例の半導体チップモジュールの斜視図。FIG. 1 is a perspective view of a semiconductor chip module of this embodiment.
【図２】本実施例の半導体チップモジュールの断面図。FIG. 2 is a cross-sectional view of the semiconductor chip module of this embodiment.
【図３】本実施例の半導体チップの上面図。FIG. 3 is a top view of the semiconductor chip of this embodiment.
【図４】従来の方式を説明するための図。FIG. 4 is a diagram for explaining a conventional method.
１…下部基板 ２…キャップ ２ａ…キャップの穿孔 ３…ヒートシンク ４…フェイスアップ型半導体チップ ４ａ…フェイスダウン型半導体チップ ５…リードピン ６…上部基板 ７…パッド ８…ボンディングワイヤ DESCRIPTION OF SYMBOLS 1 ... Lower substrate 2 ... Cap 2a ... Perforation of cap 3 ... Heat sink 4 ... Face-up type semiconductor chip 4a ... Face-down type semiconductor chip 5 ... Lead pin 6 ... Upper substrate 7 ... Pad 8 ... Bonding wire
Claims (1)
１個または複数個の半導体チップと、 前記半導体チップの上面中央部に一端部が接触したヒー
トシンクと、 前記ヒートシンクの他端部を外部に露出させる孔が穿設
され、前記半導体チップを全て内包するキャップとを備
えて構成される半導体チップモジュール。1. A semiconductor substrate on which a wiring portion is formed, one or a plurality of semiconductor chips arranged on the wiring portion so that a circuit surface faces upward, and one end at a central portion of an upper surface of the semiconductor chip. A semiconductor chip module configured to include a heat sink with which the parts are in contact with each other, and a cap having a hole for exposing the other end of the heat sink to the outside and including all the semiconductor chips.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3199554A JPH0547973A (en) | 1991-08-08 | 1991-08-08 | Semiconductor chip module |
| AU20775/92A AU657774B2 (en) | 1991-08-08 | 1992-08-04 | Semiconductor chip module and method for manufacturing the same |
| KR1019920014108A KR930005147A (en) | 1991-08-08 | 1992-08-06 | Semiconductor chip module and manufacturing method |
| CA002075593A CA2075593A1 (en) | 1991-08-08 | 1992-08-07 | Semiconductor chip module and method for manufacturing the same |
| EP19920113478 EP0528291A3 (en) | 1991-08-08 | 1992-08-07 | Semiconductor chip module and method for manufacturing the same |
| US08/232,346 US5525835A (en) | 1991-08-08 | 1994-04-22 | Semiconductor chip module having an electrically insulative thermally conductive thermal dissipator directly in contact with the semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3199554A JPH0547973A (en) | 1991-08-08 | 1991-08-08 | Semiconductor chip module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0547973A true JPH0547973A (en) | 1993-02-26 |
Family
ID=16409762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3199554A Pending JPH0547973A (en) | 1991-08-08 | 1991-08-08 | Semiconductor chip module |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH0547973A (en) |
| KR (1) | KR930005147A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6505329B1 (en) | 1999-05-31 | 2003-01-07 | Nec Corporation | Semiconductor device designing method and apparatus, and memory medium that is stored with macro information |
-
1991
- 1991-08-08 JP JP3199554A patent/JPH0547973A/en active Pending
-
1992
- 1992-08-06 KR KR1019920014108A patent/KR930005147A/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6505329B1 (en) | 1999-05-31 | 2003-01-07 | Nec Corporation | Semiconductor device designing method and apparatus, and memory medium that is stored with macro information |
Also Published As
| Publication number | Publication date |
|---|---|
| KR930005147A (en) | 1993-03-23 |
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