JPH0547103A - Device for forming control reference clock of composite rotating speed - Google Patents

Abstract

PURPOSE:To allow the shift of a control state without disturbing the rotating state of a motor by obviating the appearance of pulses exclusive of the period having both control reference clocks at the time of changing over from CAV control to CLV control. CONSTITUTION:The coincidence of the timing of the rise of the CAV control reference clock 2 and CLV control reference clock 3 inputted to a switch 1 is detected by monomulti 20, 21 and D flip-flop 22. The switch 1 is controlled by the signal 41 obtd. by synchronizing a changeover command 4 with a D flip-flop 23 by this detection signal C, by which the pseudo CLV control reference clock is obtd. from the output thereof. The pseudo CLV control reference clock which does not disturb the rotating state of the motor at the time of the shift from the CAV control to the CLV control is formed by the above- mentioned constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite rotation speed control reference clock generation device which combines constant angular speed rotation control and constant linear speed rotation control in order to increase the time required for recording information on a disc. ..

[0002]

2. Description of the Related Art In recent years, devices and media for recording images and music using optical disks have become quite popular. In such an optical disc, constant linear velocity (hereinafter referred to as CLV) rotation is used to lengthen the recording time. However, in order to accurately read the address signal indicating the position of the signal track when searching for a specific track, it is preferable that the number of horizontal synchronization signals of the video signal within one rotation is a constant number while crossing the tracks. Preferred for control. Therefore, in a specific area where the timings of the horizontal synchronizing signals are aligned on the adjacent tracks even though the CLV rotation is performed, the mode is temporarily switched to the uniform angular velocity rotation (hereinafter referred to as CAV), several tracks are recorded, and then the CLV is again performed.
A recording control method called pseudo CLV has been proposed in which recording is performed by rotation to improve the address reading accuracy of a plurality of specific areas.

In order to realize the above-mentioned pseudo CLV,
Depending on the recording position of the disc, the rotation control of the disc motor and the feed motor is CAV (constant angular velocity) control and CLV.
The (equal linear velocity) control needs to be alternately performed, and the pseudo CLV control reference clock as the rotation control reference clock of the disk motor and the feed motor is CAV control synchronized with the synchronizing signal of the recorded signal. It is generated by switching the CLV control reference clock having the frequency calculated from the reference clock, the recording position and the predetermined linear velocity.

A conventional pseudo CL will now be described with reference to the drawings.
The V control reference clock generation device will be described.

FIG. 3 is a block diagram showing the configuration of a conventional pseudo CLV control reference clock generation device. In FIG. 3, 1 is a switch, 2 is a CAV control reference clock, 3 is a CLV control reference clock, 4 is a switching command, and 6 and 7.
Is an input terminal of the switch 1, 8 is an output terminal of the switch 1, and 5 is a pseudo CLV control reference clock switched by the switch 1 and the switching command 4.

The conventional pseudo CLV configured as described above
The operation of the control reference clock generation device will be described below. First, the CAV control reference clock 2 and the CLV control reference clock 3 are input to the switch 1 input terminals 6 and 7, respectively, and the recording position of the disk is CAV or CL.
The switch 1 is operated by the switching command 4 whose state is determined by the means for determining whether it is V, one of them appears at the output terminal 8 of the switch 1, and the pseudo CLV control reference clock 5 is generated. ..

[0007]

However, in the above-described conventional structure, the timing chart of each part of FIG. 3 shows the timing chart of tA and tB of FIG. 4 from the rising of the CAV control reference clock 2 to the next. Cycle t2 from the rising edge of the pulse, and the cycle t3 from the rising edge of the CLV control reference clock 3 to the rising edge of the next pulse.
Since a pulse with a different cycle appears in the pseudo CLV control reference clock and the frequency does not change smoothly, the reference clock and the output signal of the rotation detector are compared on a one-to-one basis. In the motor control system that obtains the above, the rotation control state is disturbed, and the quality of the signal to be recorded is deteriorated.

An object of the present invention is to solve the above-mentioned conventional problems, and an object thereof is to provide a pseudo CLV control reference clock generation device in which the quality of recorded signals is not deteriorated by the disturbance of the rotation control state of the motor. Is.

[0009]

In order to achieve this object, a pseudo CLV control reference clock generator according to the present invention comprises a C
Immediately after the timings of rising (or falling) of the AV control reference clock and the CLV control reference clock match, the switch command is latched by the detection signal, and the switch command is set as a new switch command. The pseudo CLV control reference signal is obtained from the output terminal of the.

[0010]

According to the present invention, switching between the CAV control reference clock and the CLV control reference clock is achieved by the above-mentioned means.
Since it is performed immediately after the rising (or falling) of both clocks coincides with each other, the frequency transition is smoothly performed, and the pseudo CLV control reference clock in which the pulse of the cycle different from the cycle of both clocks is generated is generated. Since it does not appear, CAV to CLV (or CL
It is possible to generate a pseudo CLV control reference clock that does not disturb the rotation state of the motor when shifting from V to CAV).

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a pseudo CLV control reference clock generation device of the present invention, and FIG. 2 is a timing chart of each part of FIG. 1, in which 20 is a CAV control reference. The mono-multi is triggered by the rising edge of the clock 2 (2 in FIG. 2) and is set to output the positive pulse signal A (A in FIG. 2) having the pulse width TA, and 21 is the CLV control reference clock 3 ( It is a mono-multi that is set to output the negative pulse signal B (B in FIG. 2) triggered by the rising edge of 3) in FIG. 2 and having a pulse width TB. (Note that the TAs are set so that TA is larger than TB.) The outputs A and B of the monomultis 20 and 21 are input to the data input and clock input of the D flip-flop 22, respectively. And the Q output C of the D flip-flop 22
The state of (C in FIG. 2) is reversed because the CAV control reference clock 2 and CLV as shown in the portion surrounded by a dotted line in FIG.
Immediately after the rising timings of the control reference clocks 3 match, this signal C is input to the clock input of the D flip-flop 23.

On the other hand, if the switching command 4 is input to the data input of the D flip-flop 23 and its state changes at the timing shown in FIG. 2X, the Q output 41 of the D flip-flop 23 (41 in FIG. 2). 2 changes its state at the timing Y shown in FIG. 2, that is, the switching command 4 controls the switch 1 in synchronization with the Q output C of the D flip-flop 22.

Therefore, the timing at which the signal appearing at the output terminal 8 of the switch 1 is switched from the CAV control reference clock 2 to the CLV control reference clock 3 is the same as the timing shown in FIG. 2Y, and is output from the output terminal 8 of the switch 1. Signal 5, that is, a pseudo CLV control reference clock as shown by 5 in FIG. 2, can be obtained, and a pulse other than the cycle of both clocks appears when the CAV control reference clock is switched to the CLV control reference clock. It is possible to generate a pseudo CLV control reference clock without a clock.

[0015]

As described above, according to the present invention, C
It is generated by forming a detector for detecting immediately after the rising timings of the AV control reference clock and the CLV control reference clock match, and switching the switch by synchronizing the switching command with the output signal of this detector. Since pulses other than the periods of the CAV control reference clock and the CLV control reference clock do not appear in the pseudo CLV control reference clock, the frequency transition is performed smoothly, and the rotation control state of the motor is disturbed. It is possible to realize a pseudo CLV control reference clock generation device that is never performed.

Further, in the present embodiment, only the case of switching from the CAV control reference clock to the CLV control reference clock has been described, but the CLV control reference clock changes to the CAV.
The same effect can be obtained when switching to the control reference clock. Further, in this embodiment, a detector for detecting immediately after the rising timings of the CAV control reference clock and the CLV control reference clock match. Although an example has been described, the same effect can be obtained also in the case where a detector for detecting immediately after the falling timings coincide with each other is configured.

[Brief description of drawings]

FIG. 1 is a block diagram of a pseudo CLV control reference clock generation device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the pseudo CLV control reference clock generation device according to the embodiment of the invention.

FIG. 3 is a block diagram of a conventional pseudo CLV control reference clock generation device.

FIG. 4 is a timing chart for explaining the operation of a conventional pseudo CLV control reference clock generation device.

[Explanation of symbols]

 1 switch 20,21 mono-multi 22,23 D flip-flop

Claims (1)

[Claims] 1. A switch for switching between a constant angular velocity rotation control reference clock for controlling the rotation of a motor and a constant linear velocity rotation control reference clock, the rising edge (or falling edge) of the constant angular velocity rotation control reference clock. ) A first edge detector for pulsing and outputting a portion, and a second edge detector for pulsing and outputting a rising edge (or falling edge) portion of the constant linear velocity rotation control reference clock The output signal of the first edge detector is the output signal of the second edge detector, or the output signal of the second edge detector is the output signal of the first edge detector. A switching finger for switching between the constant angular velocity rotation control reference clock and the constant linear velocity rotation control reference clock having a first latch circuit for latching. A composite rotation speed, comprising a second latch circuit for latching a signal with the output signal of the first latch circuit, and using the output signal of the second latch circuit as a switching signal of the switch. Control reference clock generator.