JPH05326857A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05326857A
JPH05326857A JP12773292A JP12773292A JPH05326857A JP H05326857 A JPH05326857 A JP H05326857A JP 12773292 A JP12773292 A JP 12773292A JP 12773292 A JP12773292 A JP 12773292A JP H05326857 A JPH05326857 A JP H05326857A
Authority
JP
Japan
Prior art keywords
region
collector
well
oxide film
drive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12773292A
Other languages
Japanese (ja)
Inventor
Yasuyuki Tanabe
泰之 田辺
Ban Nakajima
蕃 中島
Kenji Miura
賢次 三浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP12773292A priority Critical patent/JPH05326857A/en
Publication of JPH05326857A publication Critical patent/JPH05326857A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device which is low in collector resistance and where an N-type buried layer is prevented from rising up, and a bipolar transistor is restrained from decreasing withstand voltage in by a method wherein a MOS well is diffused and a collector compensation region is provided through thermal diffusion. CONSTITUTION:After resist is removed, a collector compensation diffusion region 16 is formed in an ion implantation region by drive-in. Then, a P-type epitaxial layer left in a collector region is turned into an N well, and an N well 11 and a P well 12 are more diffused. An silicon oxide film is etched, then a pad oxide film 17 and a selection oxide film 18 are formed. Thereafter, the pad oxide film 17 is etched, a gate oxide film 18 and a polysilicon gate 20 are formed, and then a base region 21 and an emitter region 22 are formed in the base active region of an NPN bipolar transistor, and furthermore a source/drain region 23 of a MOS and a source/drain region 24 of a PMOS are formed to constitute a BiCMOS integrated circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はBiCMOS集積回路の
製造工程において、MOSトランジスタを形成するウェ
ルとNPNバイポーラトランジスタのコレクタ補償拡散
領域を形成する方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a well for forming a MOS transistor and a method for forming a collector compensation diffusion region of an NPN bipolar transistor in a manufacturing process of a BiCMOS integrated circuit.

【0002】[0002]

【従来の技術】従来、BiCMOS集積回路の製造工程
において、MOSトランジスタを形成するnウェルとp
ウェルをイオン注入で添加した不純物を高温長時間の熱
処理で深く拡散させて形成した後、素子分離のための選
択酸化を行い、次いでNPNバイポーラトランジスタの
コレクタ補償拡散領域をイオン注入と熱処理で形成して
いた。
2. Description of the Related Art Conventionally, in a manufacturing process of a BiCMOS integrated circuit, an n well and ap for forming a MOS transistor are formed.
The well added by ion implantation is deeply diffused by heat treatment at high temperature for a long time, and then selectively oxidized for element isolation, and then the collector compensation diffusion region of the NPN bipolar transistor is formed by ion implantation and heat treatment. Was there.

【0003】図4(a)〜図6(c)は従来のウェルと
コレクタ補償拡散領域の形成工程を示した断面図であ
る。図4〜図6により従来の製造方法を工程順に説明す
る。まず、p型シリコン基板1の表面に公知の技術によ
り選択的にn型埋込層2を形成したのちp型エピタキシ
ャル層3を形成し、エピタキシャル層3の表面に0.0
3μm程度の薄いシリコン酸化膜4を形成する(図4
(a))。
4 (a) to 6 (c) are sectional views showing a conventional process of forming a well and a collector compensation diffusion region. A conventional manufacturing method will be described in order of steps with reference to FIGS. First, the n-type buried layer 2 is selectively formed on the surface of the p-type silicon substrate 1 by a known technique, and then the p-type epitaxial layer 3 is formed.
A thin silicon oxide film 4 of about 3 μm is formed (FIG. 4).
(A)).

【0004】pMOSのnウェル領域を確定するために
公知の写真食刻法によりレジストパタン5を形成した
後、リンをイオン注入してエピタキシャル層3内にリン
イオン注入領域6を形成する(図4(b))。レジスト
パタン5を硫酸と過酸化水素水の混合液で溶解して除去
した後、nMOSのpウェル領域を確定するためのレジ
ストパタン7を同様に形成し、ボロンをイオン注入して
エピタキシャル層3内にボロンイオン注入領域8を形成
する(図4(c))。
After forming a resist pattern 5 by a known photo-etching method for defining the n-well region of the pMOS, phosphorus is ion-implanted to form a phosphorus ion-implanted region 6 in the epitaxial layer 3 (see FIG. 4 ( b)). After removing the resist pattern 5 by dissolving it in a mixed solution of sulfuric acid and hydrogen peroxide solution, a resist pattern 7 for defining the p-well region of the nMOS is similarly formed, and boron is ion-implanted in the epitaxial layer 3. A boron ion-implanted region 8 is formed (FIG. 4C).

【0005】次に、レジストパタン7を硫酸と過酸化水
素水の混合液で溶解して除去した後、NPNバイポーラ
トランジスタのコレクタ領域を確定するためのレジスト
パタン9を同様に形成し、リンをイオン注入してエピタ
キシャル層3内にリンイオン注入領域10を形成する
(図5(a))。レジストパタン9を硫酸と過酸化水素
水の混合液で溶解して除去した後、乾燥窒素雰囲気で1
100℃360分程度の熱処理条件でウェルドライブイ
ンしてリンイオン注入領域6からnウェル11を、ボロ
ンイオン注入領域8からpウェル12を、またリンイオ
ン注入領域10からコレクタnウェル13を形成する
(図5(b))。
Next, after removing the resist pattern 7 by dissolving it in a mixed solution of sulfuric acid and hydrogen peroxide solution, a resist pattern 9 for defining the collector region of the NPN bipolar transistor is similarly formed, and phosphorus is ionized. Implantation is performed to form a phosphorus ion implantation region 10 in the epitaxial layer 3 (FIG. 5A). After removing the resist pattern 9 by dissolving it in a mixed solution of sulfuric acid and hydrogen peroxide solution, the resist pattern 9 was dried in a nitrogen atmosphere.
Well drive-in is performed under a heat treatment condition of 100 ° C. for about 360 minutes to form phosphorus ion implantation regions 6 to n wells 11, boron ion implantation regions 8 to p wells 12, and phosphorus ion implantation regions 10 to collector n wells 13 (FIG. 5 (b)).

【0006】シリコン酸化膜4を緩衝フッ酸液等でウェ
ットエッチングした後、膜厚0.05μm程度のパッド
酸化膜17と膜厚0.15μm程度のシリコン窒化膜
(図2に開示せず)を形成した後、公知の技術により選
択酸化膜18を形成する(図5(c))。選択酸化のマ
スクとして使用したシリコン窒化膜(図に開示せず)を
熱リン酸等でエッチングした後、NPNバイポーラトラ
ンジスタのコレクタアクティブを開口するレジストパタ
ン25を形成し、リンをイオン注入してコレクタアクテ
ィブ内にリンイオン注入領域26を形成する(図6
(a))。
After wet etching the silicon oxide film 4 with a buffered hydrofluoric acid solution or the like, a pad oxide film 17 having a film thickness of about 0.05 μm and a silicon nitride film having a film thickness of about 0.15 μm (not shown in FIG. 2) are formed. After the formation, the selective oxide film 18 is formed by a known technique (FIG. 5C). After etching a silicon nitride film (not shown) used as a mask for selective oxidation with hot phosphoric acid or the like, a resist pattern 25 for opening the collector active of the NPN bipolar transistor is formed, and phosphorus is ion-implanted to collect the collector. A phosphorus ion implantation region 26 is formed in the active (FIG. 6).
(A)).

【0007】レジストパタン25を硫酸と過酸化水素水
の混合液で溶解して除去した後、乾燥窒素雰囲気で11
00℃90分程度の熱処理条件でドライブインしてコレ
クタ補償拡散領域27を形成する(図6(b))。その
後、パッド酸化膜17を緩衝フッ酸液等でウェットエッ
チングし、公知の技術によりゲート酸化膜19とポリシ
リコンゲート20を形成した後、NPNバイポーラトラ
ンジスタのベースアクティブ内にベース領域21とエミ
ッタ領域22を形成し、さらに、nMOSのソース/ド
レイン領域23とpMOSのソース/ドレイン領域24
を形成してBiCMOS集積回路が製造される(図6
(c))。
After removing the resist pattern 25 by dissolving it in a mixed solution of sulfuric acid and hydrogen peroxide water, the resist pattern 25 is removed in a dry nitrogen atmosphere.
The collector compensation diffusion region 27 is formed by driving in under heat treatment conditions of about 90 ° C. for 90 minutes (FIG. 6B). After that, the pad oxide film 17 is wet-etched with a buffer hydrofluoric acid solution or the like to form a gate oxide film 19 and a polysilicon gate 20 by a known technique, and then a base region 21 and an emitter region 22 are formed in the base active of the NPN bipolar transistor. And a source / drain region 23 of nMOS and a source / drain region 24 of pMOS.
To form a BiCMOS integrated circuit (FIG. 6).
(C)).

【0008】[0008]

【発明の解決しようとする課題】このように、従来の方
法ではMOSトランジスタの高温長時間のウェル拡散と
素子分離の選択酸化を終了してからNPNバイポーラト
ランジスタのコレクタ補償拡散を行っているため、バイ
ポーラトランジスタのコレクタ・エミッタ間耐圧やコレ
クタ・ベース間耐圧を高くするためにn型埋込層形成後
のエピ膜厚を厚くしさらにこのエピ膜厚に対応してコレ
クタ補償を深く拡散する場合は、n型埋込層やウェルに
対しては必要以上の過大な熱処理が加わり、nウェルと
pウェルとが接する境界の位置が変動したり、n型埋込
層がせり上がってバイポーラトランジスタのコレクタ・
エミッタ間耐圧やコレクタ・ベース間耐圧が低下すると
いった欠点があった。
As described above, in the conventional method, since the well diffusion of the MOS transistor at high temperature for a long time and the selective oxidation for element isolation are completed, the collector compensation diffusion of the NPN bipolar transistor is performed. To increase the collector-emitter breakdown voltage and collector-base breakdown voltage of the bipolar transistor, increase the epi film thickness after the n-type buried layer is formed, and further diffuse the collector compensation correspondingly to this epi film thickness. Excessive heat treatment is applied to the n-type buried layer and the well to change the position of the boundary where the n-well and the p-well are in contact with each other, or the n-type buried layer rises to cause a collector of the bipolar transistor.・
There is a drawback that the breakdown voltage between the emitter and collector-base is lowered.

【0009】また、pウェルに基板と異なる電位が印加
できるようにpウェルの下にn型埋込層が形成されてい
る場合は、n型埋込層のせりあがりにより、pウェル中
に形成されたnMOSのドレイン領域とn型埋込層間の
耐圧が低下するという欠点があった。また、コレクタ補
償は素子分離の選択酸化膜を形成した後に、コレクタア
クティブ領域内に選択的に不純物をイオン注入し熱拡散
して形成するため、コレクタアクティブ領域に依存した
領域に設けることになる。従って、コレクタ・ベース間
耐圧が所定の値になるようにコレクタ補償拡散領域とベ
ースアクティブとの横方向間隔を長く取ると、コレクタ
アクティブがベースアクティブから遠くなりコレクタ抵
抗が高くなるという欠点があった。
When an n-type buried layer is formed under the p-well so that a potential different from that of the substrate can be applied to the p-well, the n-type buried layer is raised to form in the p-well. However, the breakdown voltage between the drain region of the nMOS and the n-type buried layer is lowered. Further, the collector compensation is formed in a region depending on the collector active region because the impurity is selectively ion-implanted into the collector active region and thermally diffused after the selective oxide film for element isolation is formed. Therefore, if the lateral distance between the collector compensation diffusion region and the base active is made long so that the collector-base breakdown voltage becomes a predetermined value, the collector active becomes far from the base active, and the collector resistance becomes high. ..

【0010】本発明は従来の上記問題点を解決するため
になされたもので、n型埋込層のせりあがりやバイポー
ラの耐圧の低下を抑えた、コレクタ抵抗の低いNPNバ
イポーラを有する半導体装置を製造する方法を提供する
ことを目的とする。
The present invention has been made in order to solve the above-mentioned conventional problems, and provides a semiconductor device having an NPN bipolar with a low collector resistance, which suppresses the rise of the n-type buried layer and the decrease of the bipolar withstand voltage. It is intended to provide a method for manufacturing.

【0011】[0011]

【課題を解決するための手段】本発明は、MOSのウェ
ル拡散の最適熱処理条件を、NPNバイポーラトランジ
スタのコレクタ補償拡散の最適熱処理条件と残りの熱処
理条件の2つに分け、まず後者の条件でMOSのウェル
拡散を行った後、前者の条件でコレクタ補償拡散を行う
ことにより、MOSのウェル拡散とNPNバイポーラの
コレクタ補償拡散を共に最適条件で行うこと、また、コ
レクタ補償拡散を行った後に素子分離の選択酸化を行う
ことにより、コレクタアクティブ領域の位置に依らずに
コレクタ補償領域を設けることを最も主要な特徴とす
る。
According to the present invention, the optimum heat treatment condition for the well diffusion of a MOS is divided into the optimum heat treatment condition for the collector compensation diffusion of an NPN bipolar transistor and the remaining heat treatment condition. After performing the MOS well diffusion, the collector compensation diffusion is performed under the former condition so that both the MOS well diffusion and the NPN bipolar collector compensation diffusion are performed under the optimum conditions. The most main feature is to provide the collector compensation region regardless of the position of the collector active region by performing the selective selective oxidation.

【0012】従来の方法では、コレクタ補償の熱処理を
考慮せずにMOSのウェル拡散を行った後にコレクタ補
償の熱拡散を行っていた点と、素子分離の選択酸化後に
コレクタ補償拡散工程を行っていた点が異なる。
In the conventional method, the thermal diffusion for collector compensation is performed after the well diffusion of the MOS without considering the heat treatment for collector compensation, and the collector compensation diffusion step is performed after the selective oxidation for element isolation. The difference is that.

【0013】[0013]

【実施例】以下、本発明の実施例について図を用いて説
明する。図1(a)〜図3(c)は本発明の実施例を工
程順に説明した断面図である。まず、従来の方法と同様
にして、p型シリコン基板1の表面に選択的にn型埋込
層2、p型エピタキシャル層3、シリコン酸化膜4を形
成した後、公知の写真食刻法とイオン注入法により選択
的にMOSトランジスタのnウェルとpウェル、および
NPNバイポーラトランジスタのコレクタnウェルのイ
オン注入領域6、8、10を形成する(図1(a)〜図
2(a))。
Embodiments of the present invention will be described below with reference to the drawings. 1A to 3C are cross-sectional views illustrating an embodiment of the present invention in the order of steps. First, similarly to the conventional method, the n-type buried layer 2, the p-type epitaxial layer 3, and the silicon oxide film 4 are selectively formed on the surface of the p-type silicon substrate 1, and then the known photolithography method is used. Ion implantation regions 6, 8 and 10 of the n well and p well of the MOS transistor and the collector n well of the NPN bipolar transistor are selectively formed by the ion implantation method (FIGS. 1A to 2A).

【0014】次に、乾燥窒素雰囲気で1100℃270
分程度の熱処理条件でウェルドライブインしてリンイオ
ン注入領域6からnウェル11を、ボロンイオン注入領
域8からpウェル12を、またリンイオン注入領域10
からコレクタnウェル13を形成する(図2(b))。
NPNバイポーラトランジスタのコレクタ領域を確定す
るためのレジストパタン14を形成した後、リンをイオ
ン注入してコレクタnウェル領域13内にリンイオン注
入領域15を形成する(図2(c))。
Next, at a temperature of 1100 ° C. and 270 ° C. in a dry nitrogen atmosphere.
Well drive-in under heat treatment conditions of about 10 minutes, phosphorus ion implantation regions 6 to n wells 11, boron ion implantation regions 8 to p wells 12, and phosphorus ion implantation regions 10
Then, the collector n-well 13 is formed (FIG. 2B).
After forming a resist pattern 14 for defining the collector region of the NPN bipolar transistor, phosphorus is ion-implanted to form a phosphorus ion-implanted region 15 in the collector n-well region 13 (FIG. 2C).

【0015】レジストパタン14を硫酸と過酸化水素水
の混合液で溶解して除去した後、乾燥窒素雰囲気で11
00℃90分程度の熱処理条件でドライブインしてリン
イオン注入領域15からコレクタ補償拡散領域16を形
成する。コレクタ領域内に残存していたp型エピタキシ
ャル層3はドライブインの間にコレクタnウェルの拡散
が進んでコレクタnウェルに変わる。nウェル11とp
ウェル12もドライブインの間にさらに拡散が進む(図
3(a))。
After removing the resist pattern 14 by dissolving it in a mixed solution of sulfuric acid and hydrogen peroxide solution, the resist pattern 14 is removed in a dry nitrogen atmosphere.
The collector compensation diffusion region 16 is formed from the phosphorus ion implantation region 15 by driving in under the heat treatment condition of about 90 ° C. for about 90 minutes. The p-type epitaxial layer 3 remaining in the collector region is converted into the collector n-well by diffusion of the collector n-well during drive-in. n well 11 and p
The well 12 also diffuses further during drive-in (FIG. 3A).

【0016】シリコン酸化膜4を緩衝フッ酸液等でウェ
ットエッチングした後、膜厚0.05μm程度のパッド
酸化膜17と膜厚0.15μm程度のシリコン窒化膜
(図に開示せず)を形成した後、公知の技術により選択
酸化膜18を形成する(図3(h))。その後、パッド
酸化膜17を緩衝フッ酸液等でウェットエッチングし、
公知の技術によりゲート酸化膜19とポリシリコンゲー
ト20を形成した後、NPNバイポーラトランジスタの
ベースアクティブ内にベース領域21とエミッタ領域2
2を形成し、さらに、nMOSのソース/ドレイン領域
23とpMOSのソース/ドレイン領域24を形成して
BiCMOS集積回路が製造される(図3(c))。
After wet etching the silicon oxide film 4 with a buffered hydrofluoric acid solution or the like, a pad oxide film 17 having a thickness of about 0.05 μm and a silicon nitride film (not shown in the figure) having a thickness of about 0.15 μm are formed. After that, the selective oxide film 18 is formed by a known technique (FIG. 3H). After that, the pad oxide film 17 is wet-etched with a buffered hydrofluoric acid solution or the like,
After forming the gate oxide film 19 and the polysilicon gate 20 by a known technique, the base region 21 and the emitter region 2 are formed in the base active of the NPN bipolar transistor.
2 is formed, and further, the nMOS source / drain regions 23 and the pMOS source / drain regions 24 are formed to manufacture the BiCMOS integrated circuit (FIG. 3C).

【0017】コレクタ補償イオン注入後のドライブイン
は、エピタキシャル層の膜厚が薄い場合やコレクタ補償
の拡散深さを浅くしたい場合は、ウェルドライブインの
温度より低い温度で行ってもよい。 このような方法で
ウェルを形成すると、ウェルはウェルイオン注入後のド
ライブインとその後のコレクタ補償の熱拡散とを合わせ
た熱処理が最適条件となるように設定できる。また、コ
レクタ補償の拡散条件はp型エピタキシャル層の膜厚が
厚くてこれに対応して深く拡散させる場合でも、ウェル
やn型埋込層に対する熱処理が過大となることを防止し
ながら、最適条件にすることができる。さらに、コレク
タ補償拡散の後に素子分離の選択酸化を行うため、コレ
クタアクティブをコレクタ補償用のイオン注入領域より
もベースアクティブに近づけて設けることができ、コレ
クタ・ベース間耐圧を低下させることなくコレクタ抵抗
を下げることができる。
The drive-in after the collector compensating ion implantation may be performed at a temperature lower than the well drive-in temperature when the epitaxial layer is thin or the collector compensation diffusion depth is desired to be shallow. When the well is formed by such a method, the well can be set so that the heat treatment including the drive-in after the well ion implantation and the subsequent thermal diffusion for collector compensation is the optimum condition. In addition, the diffusion conditions for the collector compensation are the optimum conditions while preventing the heat treatment for the well and the n-type buried layer from being excessive even when the p-type epitaxial layer is thick and the corresponding deep diffusion is performed. Can be Furthermore, since the selective oxidation for element isolation is performed after collector compensation diffusion, the collector active can be provided closer to the base active than the ion implantation region for collector compensation, and the collector resistance can be reduced without lowering the collector-base breakdown voltage. Can be lowered.

【0018】[0018]

【発明の効果】以上説明したように、ウェルとコレクタ
補償の熱拡散がそれぞれ最適な条件で行えると共に低い
コレクタ抵抗を有するBiCMOS集積回路を製造する
ことができる。
As described above, it is possible to manufacture a BiCMOS integrated circuit having a well collector and thermal compensation for collector compensation under optimum conditions and having a low collector resistance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るMOSトランジスタを形成するウ
ェルとNPNバイポーラトランジスタのコレクタ補償拡
散領域を素子分離の選択酸化工程の前に形成する方法の
一実施例の工程の一部を工程順に示す断面図。
FIG. 1 is a cross-sectional view showing part of the steps of an embodiment of a method for forming a well forming a MOS transistor and a collector compensation diffusion region of an NPN bipolar transistor before a selective oxidation step for element isolation in the order of steps according to the present invention. Fig.

【図2】本発明に係るMOSトランジスタを形成するウ
ェルとNPNバイポーラトランジスタのコレクタ補償拡
散領域を素子分離の選択酸化工程の前に形成する方法の
一実施例の工程の一部を工程順に示す断面図。
FIG. 2 is a cross-sectional view showing part of the steps of an embodiment of a method of forming a well forming a MOS transistor and a collector compensation diffusion region of an NPN bipolar transistor before a selective oxidation step for element isolation in the order of steps according to the present invention. Fig.

【図3】本発明に係るMOSトランジスタを形成するウ
ェルとNPNバイポーラトランジスタのコレクタ補償拡
散領域を素子分離の選択酸化工程の前に形成する方法の
一実施例の工程の一部を工程順に示す断面図。
FIG. 3 is a cross-sectional view showing part of the steps of an embodiment of a method of forming a well forming a MOS transistor and a collector compensation diffusion region of an NPN bipolar transistor before a selective oxidation step for element isolation in the order of steps according to the present invention. Fig.

【図4】コレクタ補償拡散領域を選択酸化工程後に形成
する従来の方法の工程の一部を製造工程順に示した断面
図である。
FIG. 4 is a cross-sectional view showing, in the order of manufacturing steps, a part of steps of a conventional method for forming a collector compensation diffusion region after a selective oxidation step.

【図5】コレクタ補償拡散領域を選択酸化工程後に形成
する従来の方法の工程の一部を製造工程順に示した断面
図である。
FIG. 5 is a cross-sectional view showing, in the order of manufacturing steps, part of the steps of a conventional method for forming a collector compensation diffusion region after the selective oxidation step.

【図6】コレクタ補償拡散領域を選択酸化工程後に形成
する従来の方法の工程の一部を製造工程順に示した断面
図である。
FIG. 6 is a cross-sectional view showing, in the order of manufacturing steps, part of the steps of a conventional method for forming a collector compensation diffusion region after the selective oxidation step.

【符号の説明】[Explanation of symbols]

1 p型シリコン基板 2 n型埋込層 3 p型エピタキシャル層 4 シリコン酸化膜 5、7、9、14、25 レジストパタン 6、10、15、26 リンイオン注入領域 8 ボロンイオン注入領域 11 nウェル 12 pウェル 13 コレクタnウェル 16、27 コレクタ補償拡散領域 17 パッド酸化膜 18 選択酸化膜 19 ゲート酸化膜 20 ポリシリコンゲート 21 ベース拡散領域 22 エミッタ拡散領域 23 nMOSのソース/ドレイン領域 24 pMOSのソース/ドレイン領域 1 p-type silicon substrate 2 n-type buried layer 3 p-type epitaxial layer 4 silicon oxide film 5, 7, 9, 14, 25 resist pattern 6, 10, 15, 26 phosphorus ion implantation region 8 boron ion implantation region 11 n well 12 p-well 13 collector n-well 16, 27 collector compensation diffusion region 17 pad oxide film 18 selective oxide film 19 gate oxide film 20 polysilicon gate 21 base diffusion region 22 emitter diffusion region 23 nMOS source / drain region 24 pMOS source / drain region

フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 9170−4M H01L 27/06 321 C 9170−4M 321 E Continuation of the front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location 9170-4M H01L 27/06 321 C 9170-4M 321 E

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板もしくは半導体基板の主面上に
形成したエピタキシャル層にその主面側から、第1導電
型のウェル領域を形成するための第1導電型の不純物と
第2導電形のウェル領域を形成するための第2導電型の
不純物を選択的にイオン注入したのち熱処理して不純物
を拡散させる第1のドライブイン工程と、 バイポーラトランジスタのコレクタ補償拡散領域を形成
するための第1導電型の不純物を選択的にイオン注入し
たのち熱処理して不純物を拡散させる第2のドライブイ
ン工程と、を含む半導体装置の製造方法において、前記
第1のドライブイン工程の熱処理条件を前記第2のドラ
イブイン工程の熱処理条件と合わせて、ウェル領域形成
に最適な拡散条件となるようにし、前記第2のドライブ
イン工程の熱処理条件をコレクタ補償拡散領域を形成す
るための最適条件としたことを特徴とする半導体装置の
製造方法。
1. An impurity of the first conductivity type and a second conductivity type for forming a well region of the first conductivity type from a main surface side of a semiconductor substrate or an epitaxial layer formed on the main surface of the semiconductor substrate. A first drive-in step of selectively ion-implanting a second conductivity type impurity for forming a well region, followed by heat treatment to diffuse the impurity, and a first drive-in step for forming a collector compensation diffusion region of a bipolar transistor. A second drive-in step of selectively ion-implanting conductivity type impurities and then performing a heat treatment to diffuse the impurities, the heat treatment condition of the first drive-in step is set to the second drive-in step. The heat treatment conditions for the second drive-in step are adjusted so that the optimum diffusion conditions for forming the well region are combined with the heat treatment conditions for the second drive-in step. A method of manufacturing a semiconductor device, characterized in that optimum conditions for forming a data compensation diffusion region are set.
JP12773292A 1992-05-20 1992-05-20 Manufacture of semiconductor device Pending JPH05326857A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12773292A JPH05326857A (en) 1992-05-20 1992-05-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12773292A JPH05326857A (en) 1992-05-20 1992-05-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05326857A true JPH05326857A (en) 1993-12-10

Family

ID=14967324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12773292A Pending JPH05326857A (en) 1992-05-20 1992-05-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05326857A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100319872B1 (en) * 1994-08-25 2002-11-07 삼성전자 주식회사 Manufacturing Method of BiCMOS Semiconductor Device with Improved Reliability
JP2014187275A (en) * 2013-03-25 2014-10-02 Seiko Epson Corp Semiconductor device manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100319872B1 (en) * 1994-08-25 2002-11-07 삼성전자 주식회사 Manufacturing Method of BiCMOS Semiconductor Device with Improved Reliability
JP2014187275A (en) * 2013-03-25 2014-10-02 Seiko Epson Corp Semiconductor device manufacturing method

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