JPH053183A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH053183A
JPH053183A JP3153650A JP15365091A JPH053183A JP H053183 A JPH053183 A JP H053183A JP 3153650 A JP3153650 A JP 3153650A JP 15365091 A JP15365091 A JP 15365091A JP H053183 A JPH053183 A JP H053183A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
bumps
bump
protective film
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3153650A
Other languages
Japanese (ja)
Other versions
JP2701589B2 (en
Inventor
Michitaka Urushima
路高 漆島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3153650A priority Critical patent/JP2701589B2/en
Publication of JPH053183A publication Critical patent/JPH053183A/en
Application granted granted Critical
Publication of JP2701589B2 publication Critical patent/JP2701589B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To enable a semiconductor substrate to be enhanced in mechanical strength and lessened in thickness by a method wherein a protective film is provided to the semiconductor substrate to cover its surface including the side faces of bumps provided to pad electrodes, and the upside of the protective film is set level with those of the bumps so as to enable the upsides of the bumps to be exposed. CONSTITUTION:Pad electrodes 11 electrically connected to the outside are provided onto a semiconductor substrate 4 where semiconductor elements are formed, a metal film of Ti or the like is formed on the surface of the substrate 4 including the pad electrodes 11, the pad electrodes 11 are selectively plated with Au or the like making the metal film serve as a plating electrode, then the metal film is removed, and bumps 10 are formed. Then, a protective film 12 of epoxy resin or the like is applied onto all the surface of the substrate 4 including the bumps 10 as thick as 200mum and then cured. In succession, the semiconductor substrate 4 is rendered as thin as 200mum or so by grinding its rear side, and furthermore the protective film 12 is etched back to be as thin as 20mum or so to make the upsides of the bumps 10 exposed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置及びその製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

【0002】[0002]

【従来の技術】従来の半導体装置の製造方法は、まず、
図3(a)に示すように、半導体素子が形成された半導
体基板4の上に外部との電気的接続行なうためのパッド
電極11を選択的に形成する。
2. Description of the Related Art A conventional semiconductor device manufacturing method is as follows.
As shown in FIG. 3A, a pad electrode 11 for electrically connecting to the outside is selectively formed on the semiconductor substrate 4 on which the semiconductor element is formed.

【0003】次に、図3(b)に示すように、パッド電
極11を含む半導体基板4の表面にTi,Cr,Cu等
の金属膜14を堆積した後、フォトリソグラフィー技術
及びめっき法を用いてパッド電極11上の金属膜14の
上に選択的に、Au,Cu,Pb−Sn等のバンプ10
を形成する。
Next, as shown in FIG. 3B, after depositing a metal film 14 of Ti, Cr, Cu or the like on the surface of the semiconductor substrate 4 including the pad electrode 11, the photolithography technique and the plating method are used. Bumps 10 of Au, Cu, Pb-Sn, etc. are selectively formed on the metal film 14 on the pad electrodes 11.
To form.

【0004】次に、図3(c)に示すように、バンプ1
0をマスクとして金属膜14をエッチング除去して半導
体装置を構成していた。
Next, as shown in FIG. 3C, the bump 1
The metal film 14 was removed by etching using 0 as a mask to form a semiconductor device.

【0005】このようなバンプを有する半導体装置を実
装する方法の一つにフリップチップがある。これは図4
(a)に示すように、実装基板15のボンディングパッ
ド13とPb−Sn等からなる、バンプ10とを半田熔
融することにより接続する。次いで、半導体素子の保護
のために、エポキシ樹脂等の樹脂層17で被覆する。
Flip chip is one of the methods for mounting a semiconductor device having such bumps. This is Figure 4
As shown in (a), the bonding pad 13 of the mounting substrate 15 and the bump 10 made of Pb-Sn or the like are connected by melting by soldering. Then, a resin layer 17 such as an epoxy resin is coated to protect the semiconductor element.

【0006】また、同様にバンプを有する半導体基板4
を実装する方法として、フィルムキャリア方式がある。
これは、図4(b)に示すように、バンプ10と、フィ
ルムキャリアテープ上のインナーリード6を熱圧着法又
は共晶法を用いて接続(Inner Lead Bon
ding)する。次に、半導体基板4表面に信頼性の向
上及び機械的保護を目的として、例えば、エポキシ樹脂
等の樹脂層17を滴下して、半導体チップ表面を樹脂封
止する。次いで、電気選別用パッド9を用いて電気検査
及びバーンインテストを行なう。さらに、実装基板に実
装する場合は、所定寸法にアウターリード7を切断し、
成形した後、実装基板15のボンディングパッド13と
アウターリード7とをボンディングして実装する。
Further, a semiconductor substrate 4 having bumps similarly.
There is a film carrier method as a method of mounting.
As shown in FIG. 4B, this is done by connecting the bump 10 and the inner lead 6 on the film carrier tape by thermocompression bonding or eutectic method (Inner Lead Bond).
ding). Next, for the purpose of improving reliability and mechanical protection, a resin layer 17 such as an epoxy resin is dropped on the surface of the semiconductor substrate 4 to seal the surface of the semiconductor chip with resin. Then, an electrical inspection and a burn-in test are performed using the electrical selection pad 9. Furthermore, when mounting on a mounting board, the outer lead 7 is cut into a predetermined size,
After molding, the bonding pad 13 of the mounting substrate 15 and the outer lead 7 are bonded and mounted.

【0007】[0007]

【発明が解決しようとする課題】上述した半導体装置
は、フリップチップ方式の実装後半導体素子の保護とし
て形成する樹脂層が実装基板と半導体基板の間に完全に
充填するのが非常にむずかしく、さらにこれを確認する
ことが難しい。又、従来の半導体装置は半導体基板の厚
さが500μm,樹脂層の厚さが100〜300μm
で、全体として600〜800μmの厚さを有してい
る。電子装置の軽量化・薄型化に伴なって、これるの半
導体装置の更なる薄型化が要求されている。すなわち、
800μm程度の厚さをさらに薄くする必要がある。そ
のために、半導体基板を研削する方法があるが、割れ等
の破損に至ることが多い。また樹脂厚についても、半導
体素子表面を完全に被覆するためには、ある一定量の樹
脂を滴下する必要があり薄型化に限界があった。
In the above-described semiconductor device, it is very difficult for the resin layer formed as a protection of the semiconductor element after flip-chip mounting to completely fill between the mounting substrate and the semiconductor substrate. It is difficult to confirm this. In the conventional semiconductor device, the semiconductor substrate has a thickness of 500 μm, and the resin layer has a thickness of 100 to 300 μm.
Therefore, it has a thickness of 600 to 800 μm as a whole. Along with the weight reduction and thickness reduction of electronic devices, further reduction in thickness of such semiconductor devices is required. That is,
It is necessary to further reduce the thickness of about 800 μm. Therefore, there is a method of grinding a semiconductor substrate, but it often results in damage such as cracking. Also, regarding the resin thickness, in order to completely cover the surface of the semiconductor element, it is necessary to drop a certain amount of resin, and there is a limit to thinning.

【0008】[0008]

【課題を解決するための手段】本発明の半導体装置は、
半導体基板上に設けたパッド電極と、前記パッド電極上
に設けたバンプと、前記バンプの側面を含む表面を被覆
し且つ上面を前記バンプの上面と同一平面として前記バ
ンプの上面を露出させた保護膜とを有する。
The semiconductor device of the present invention comprises:
Protection by covering the pad electrode provided on the semiconductor substrate, the bump provided on the pad electrode, and the surface including the side surface of the bump and exposing the upper surface of the bump with the upper surface flush with the upper surface of the bump With a membrane.

【0009】本発明の半導体装置の製造方法は、半導体
素子を設けた半導体基板上に外部接続用のパッド電極を
設け前記パッド電極上に金属層を選択的に堆積してバン
プを形成する工程と、前記バンプを含む表面に保護膜を
形成する工程と、前記半導体基板の裏面を研削して前記
半導体基板の厚さを薄くする工程と、前記保護膜を研削
して前記バンプの上面を露出させる工程とを含んで構成
される。
A method of manufacturing a semiconductor device according to the present invention comprises a step of forming pad electrodes for external connection on a semiconductor substrate having a semiconductor element and selectively depositing a metal layer on the pad electrodes to form bumps. A step of forming a protective film on the surface including the bump, a step of grinding the back surface of the semiconductor substrate to reduce the thickness of the semiconductor substrate, and a step of grinding the protective film to expose an upper surface of the bump. And a process.

【0010】[0010]

【実施例】次に、本発明について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

【0011】図1(a)〜(c)は、本発明の一実施例
の製造方法を説明するための工程順に示した半導体チッ
プの断面図である。
1 (a) to 1 (c) are cross-sectional views of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

【0012】まず、図1(a)に示すように、従来例と
同様の工程により半導体素子を形成した半導体基板4上
に、外部との電気的接続を行なうためのパッド電極11
を形成し、パッド電極11を含む表面に例えば、Ti,
Cr,Cu等の金属膜(図示せず)を形成し、次いで、
金属膜をめっき電極として選択的にパッド電極11上に
例えばAu,Cu,Pb−Sn等をめつきした後金属膜
を除去してバンプ10を形成する。なお、このバンプ形
成は、めっき法の他に、特開昭49−52973号公報
に記載されているように、Au,Pb−Sn等からなる
ワイヤーをワイヤーボンディング法を使用して、ボール
形成し、ボールをパッド上に接合後ボールのみを残し、
ワイヤーを切断することによってバンプを形成する方法
や、熔融半田中に浸漬してパッド電極上のみに半田バン
プを形成する方法等の従来のバンプ形成法を利用するこ
とができる。
First, as shown in FIG. 1A, a pad electrode 11 for making an electrical connection to the outside is formed on a semiconductor substrate 4 on which a semiconductor element is formed by a process similar to the conventional example.
On the surface including the pad electrode 11, for example, Ti,
A metal film (not shown) of Cr, Cu or the like is formed, and then,
The bumps 10 are formed by selectively depositing Au, Cu, Pb-Sn or the like on the pad electrode 11 using the metal film as a plating electrode and then removing the metal film. In addition to the plating method, the bump is formed by ball-forming a wire made of Au, Pb-Sn, etc. by a wire bonding method, as described in JP-A-49-52973. After joining the ball on the pad, leaving only the ball,
A conventional bump forming method such as a method of forming a bump by cutting a wire or a method of immersing the wire in molten solder to form a solder bump only on a pad electrode can be used.

【0013】次に、図1(b)に示ように、バンプ10
を含む半導体基板4上全面に、例えばエポキン樹脂等の
保護膜12を200μmの厚さに塗布し、硬化させる。
Next, as shown in FIG. 1B, the bump 10
A protective film 12 of, for example, Epokin resin is applied to a thickness of 200 μm on the entire surface of the semiconductor substrate 4 including, and is cured.

【0014】次に図1(c)に示すように、半導体基板
4の裏面を研削して半導体基板の厚さを200μm程度
まで薄くし、さらに保護膜12を樹脂厚が20μm程度
になるまでエッチバックしてバンプ10の上面を露出さ
せる。なお、半導体基板4の放熱性を考慮して、あらか
じめ、ボールバンプを2重、3重に形成する等によりバ
ンプ10の高さを高くしておき、強度を保ために、樹脂
厚を100μm程度に厚くし、半導体基板4を50μm
程度に薄くしていても良い。
Next, as shown in FIG. 1C, the back surface of the semiconductor substrate 4 is ground to reduce the thickness of the semiconductor substrate to about 200 μm, and the protective film 12 is etched until the resin thickness reaches about 20 μm. Back up to expose the upper surface of the bump 10. In consideration of the heat dissipation of the semiconductor substrate 4, the height of the bumps 10 is increased in advance by forming the ball bumps in double or triple, and the resin thickness is about 100 μm in order to maintain the strength. The semiconductor substrate 4 to 50 μm
It may be thin to some extent.

【0015】図2(a),(b)は本発明の半導体装置
の実装状態を示す断面図である。
2 (a) and 2 (b) are sectional views showing a mounted state of the semiconductor device of the present invention.

【0016】図2(a)はフリップチップ法による実装
例で、露出したバンプ10上又は、実装基板15のボン
ディングパッド13上に設けた第2のバンプ16を介し
て半導体装置を実装する。
FIG. 2A shows an example of mounting by the flip chip method, in which the semiconductor device is mounted through the exposed bumps 10 or the second bumps 16 provided on the bonding pads 13 of the mounting substrate 15.

【0017】ここで、バンプ16の形成法は、半導体基
板上にバンプを形成した場合と同様に、めっき法、ボー
ルバンプ法があるが、その他に、「日経マイクロデバイ
ス」1989年、7月号、43〜65頁に記載されてい
るように、Auバンプの上にAgペースト等の導電性ペ
ーストを更に塗布する方法や、導電性樹脂を印刷や滴下
法により形成する方法等があり、従来のバンプ形成法を
利用して、容易に実施できる。また、バンプの代りに微
小なピンやリードを用いることもできる。次に、接続の
方法、例えば、露出バンプ10と第2のバンプ16の組
み合わせが、半田−半田の場合は、熔融によって接続
し、Au−Auの場合は、異方導電性シートを用いて接
続し、導電性接着剤の場合は、硬化によって接続する等
バンプ材料により適切な接続方法を選択する。
The bumps 16 can be formed by the plating method or the ball bump method as in the case of forming the bumps on the semiconductor substrate. In addition, the "Nikkei Microdevice", July, 1989 issue. , Pages 43 to 65, there is a method of further applying a conductive paste such as an Ag paste on the Au bump, a method of forming a conductive resin by printing or a dropping method, and the like. This can be easily performed by using the bump forming method. Also, minute pins or leads can be used instead of bumps. Next, a connection method, for example, when the combination of the exposed bump 10 and the second bump 16 is solder-solder, connection is performed by melting, and in the case of Au-Au, an anisotropic conductive sheet is used for connection. However, in the case of a conductive adhesive, an appropriate connection method is selected depending on the bump material such as connection by curing.

【0018】図2(b)は、フィルムキャリアテープを
利用した実装例で、保護膜12に露出したバンプ10上
又は、インナーリード部に第2のバンプ16を形成し、
インナーリードボンディングを例えば熱圧着法等で実施
する。次いで、実装基板15上のボンディングパッド1
3でアウターリード部7と、アウターリードボンディン
グを例えば、熱圧着法で実施する。なおバンプ16の形
成方法は、フリップチップの場合と同様に行なう。更
に、バンプ16を形成せずに直接リードを露出したバン
プ10にボンディングすることも可能である。また、露
出したバンプ10の上に直接ワイヤーボンディングする
ことにより、従来のワイヤーボンディング半導体装置用
の半導体基板としても、利用することができる。
FIG. 2B shows a mounting example using a film carrier tape, in which the second bump 16 is formed on the bump 10 exposed on the protective film 12 or on the inner lead portion.
Inner lead bonding is performed by, for example, a thermocompression bonding method. Next, the bonding pad 1 on the mounting substrate 15
In 3, the outer lead portion 7 and the outer lead bonding are performed by, for example, a thermocompression bonding method. The method of forming the bumps 16 is the same as that of the flip chip. Further, it is also possible to directly bond the lead to the exposed bump 10 without forming the bump 16. Further, by directly wire-bonding on the exposed bump 10, it can be used as a semiconductor substrate for a conventional wire-bonding semiconductor device.

【0019】[0019]

【発明の効果】以上説明したように本発明は、半導体基
板厚を、従来に比べ、さらに薄くすることが可能となる
ため、薄型及び軽量型の半導体装置の製造が可能とな
る。又、保護樹脂の形成が容易でかつ、薄くできる。さ
らに従来のフリップチップ法で実装後、実装基板全面に
樹脂を被覆する場合は、基板実装後不良発生時の個別単
位の交換が困難であったが、本発明では、個別に、樹脂
封止及び実装できることから、個別単位の交換が可能と
いう効果も有する。
As described above, according to the present invention, the thickness of the semiconductor substrate can be further reduced as compared with the conventional one, so that a thin and lightweight semiconductor device can be manufactured. Further, the protective resin can be formed easily and can be made thin. Further, when the entire surface of the mounting board is covered with resin after mounting by the conventional flip-chip method, it is difficult to replace individual units when a defect occurs after mounting on the board. Since it can be mounted, it also has an effect that individual units can be exchanged.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の製造方法を説明するための
工程順に示した半導体チップの断面図。
FIG. 1 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a manufacturing method according to an embodiment of the present invention.

【図2】本発明の半導体装置の実装状態を示す断面図。FIG. 2 is a cross-sectional view showing a mounted state of the semiconductor device of the invention.

【図3】従来の半導体装置の製造方法を説明するための
工程順に示した半導体チップの断面図。
FIG. 3 is a cross-sectional view of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor device.

【図4】従来の半導体装置の実装状態を示す断面図。FIG. 4 is a cross-sectional view showing a mounted state of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

4 半導体基板 6 インナーリード 7 アウターリード 10,16 バンプ 11 パッド電極 12 保護膜 13 ボンディングパッド 14 金属膜 15 実装基板 17 樹脂層 4 Semiconductor substrate 6 inner lead 7 Outer leads 10,16 bumps 11 Pad electrode 12 Protective film 13 Bonding pad 14 Metal film 15 Mounting board 17 Resin layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に設けたパッド電極と、前
記パッド電極上に設けたバンプと、前記バンプの側面を
含む表面を被覆し且つ上面を前記バンプの上面と同一平
面として前記バンプの上面を露出させた保護膜とを有す
ることを特徴とする半導体装置。
1. A pad electrode provided on a semiconductor substrate, a bump provided on the pad electrode, a surface including a side surface of the bump, and an upper surface of the bump that is flush with an upper surface of the bump. A semiconductor device having a protective film that exposes.
【請求項2】 半導体基板の厚さが保護膜の厚さより薄
い請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the semiconductor substrate is thinner than the protective film.
【請求項3】 半導体素子を設けた半導体基板上に外部
接続用のパッド電極を設け前記パッド電極上に金属層を
選択的に堆積してバンプを形成する工程と、前記バンプ
を含む表面に保護膜を形成する工程と、前記半導体基板
の裏面を研削して前記半導体基板の厚さを薄くする工程
と、前記保護膜を研削して前記バンプの上面を露出させ
る工程とを含むことを特徴とする半導体装置の製造方
法。
3. A step of providing a pad electrode for external connection on a semiconductor substrate provided with a semiconductor element, selectively depositing a metal layer on the pad electrode to form a bump, and protecting a surface including the bump. A step of forming a film, a step of grinding the back surface of the semiconductor substrate to reduce the thickness of the semiconductor substrate, and a step of grinding the protective film to expose the upper surface of the bump. Of manufacturing a semiconductor device.
JP3153650A 1991-06-26 1991-06-26 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2701589B2 (en)

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JPH0722461A (en) * 1993-06-23 1995-01-24 Nec Corp Coaxial flip chip connection structure and formation thereof
US5710062A (en) * 1993-06-01 1998-01-20 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same
EP0853337A4 (en) * 1996-07-12 2000-02-16 Fujitsu Ltd Method and mold for manufacturing semiconductor device, semiconductor device, and method for mounting the device
WO2001015223A1 (en) * 1999-08-23 2001-03-01 Rohm Co., Ltd. Semiconductor device and method of manufacture thereof
JP2001127186A (en) * 1999-10-25 2001-05-11 Oki Electric Ind Co Ltd Ball grid array package, method of manufacturing the same, and semiconductor device
JP2003031524A (en) * 2001-07-13 2003-01-31 Rohm Co Ltd Semiconductor device and method of manufacturing the same
JP2004158825A (en) * 2003-07-17 2004-06-03 Oki Electric Ind Co Ltd Manufacturing method of semiconductor device
US6791195B2 (en) 2000-04-24 2004-09-14 Nec Electronics Corporation Semiconductor device and manufacturing method of the same
US6870248B1 (en) 1999-06-07 2005-03-22 Rohm Co., Ltd. Semiconductor chip with external connecting terminal
US6881611B1 (en) 1996-07-12 2005-04-19 Fujitsu Limited Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device
EP1043772A3 (en) * 1999-04-09 2005-10-12 Oki Electric Industry Company, Limited Method for packaging and mounting semiconductor device and device obtained thereby
CN100452376C (en) * 1996-07-12 2009-01-14 富士通株式会社 Semiconductor device
CN100452329C (en) * 2003-12-02 2009-01-14 全懋精密科技股份有限公司 Semiconductor packing substrate for forming presoldering tin material and its preparation method
JP2012204589A (en) * 2011-03-25 2012-10-22 Disco Abrasive Syst Ltd Semiconductor device wafer bonding method
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JPS62136049A (en) * 1985-12-10 1987-06-19 Fuji Electric Co Ltd Manufacture of semiconductor device
JPH02153527A (en) * 1988-12-05 1990-06-13 Fujitsu Ltd Manufacture of semiconductor device

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JPH02153527A (en) * 1988-12-05 1990-06-13 Fujitsu Ltd Manufacture of semiconductor device

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US5710062A (en) * 1993-06-01 1998-01-20 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same
US5834340A (en) * 1993-06-01 1998-11-10 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same
US6046071A (en) * 1993-06-01 2000-04-04 Mitsubishi Denki Kabushiki Kaisha Plastic molded semiconductor package and method of manufacturing the same
JPH0722461A (en) * 1993-06-23 1995-01-24 Nec Corp Coaxial flip chip connection structure and formation thereof
EP1189270A3 (en) * 1996-07-12 2003-07-16 Fujitsu Limited Semiconductor device
EP0853337A4 (en) * 1996-07-12 2000-02-16 Fujitsu Ltd Method and mold for manufacturing semiconductor device, semiconductor device, and method for mounting the device
CN100452376C (en) * 1996-07-12 2009-01-14 富士通株式会社 Semiconductor device
US6881611B1 (en) 1996-07-12 2005-04-19 Fujitsu Limited Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device
US7314779B2 (en) 1999-04-09 2008-01-01 Oki Electric Industry Co., Ltd. Semiconductor device, manufacturing method for semiconductor device and mounting method for the same
EP1043772A3 (en) * 1999-04-09 2005-10-12 Oki Electric Industry Company, Limited Method for packaging and mounting semiconductor device and device obtained thereby
US7262490B2 (en) 1999-06-07 2007-08-28 Rohm Co., Ltd. Semiconductor chip with external connecting terminal
US6870248B1 (en) 1999-06-07 2005-03-22 Rohm Co., Ltd. Semiconductor chip with external connecting terminal
US7339264B2 (en) 1999-06-07 2008-03-04 Rohm Co., Ltd. Semiconductor chip with external connecting terminal
US7138298B2 (en) 1999-06-07 2006-11-21 Rohm Co., Ltd. Semiconductor chip with external connecting terminal
WO2001015223A1 (en) * 1999-08-23 2001-03-01 Rohm Co., Ltd. Semiconductor device and method of manufacture thereof
US7129110B1 (en) 1999-08-23 2006-10-31 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
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JP2001127186A (en) * 1999-10-25 2001-05-11 Oki Electric Ind Co Ltd Ball grid array package, method of manufacturing the same, and semiconductor device
US6791195B2 (en) 2000-04-24 2004-09-14 Nec Electronics Corporation Semiconductor device and manufacturing method of the same
JP2003031524A (en) * 2001-07-13 2003-01-31 Rohm Co Ltd Semiconductor device and method of manufacturing the same
JP2004158825A (en) * 2003-07-17 2004-06-03 Oki Electric Ind Co Ltd Manufacturing method of semiconductor device
CN100452329C (en) * 2003-12-02 2009-01-14 全懋精密科技股份有限公司 Semiconductor packing substrate for forming presoldering tin material and its preparation method
JP2012204589A (en) * 2011-03-25 2012-10-22 Disco Abrasive Syst Ltd Semiconductor device wafer bonding method
JP2014528644A (en) * 2011-09-30 2014-10-27 インテル・コーポレーション How to handle very thin device wafers

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