JPH05298606A - Rotary head type digital signal reproducing device - Google Patents

Abstract

PURPOSE:To prevent the abandonment of correct data by revising the block address signal to a prescribed value with an interpolation means when the error of the block address signal is detected and fetching a data symbol based on the value. CONSTITUTION:When no error is judged by a parity check circuit 15, the content of a block address latch circuit 16 is loaded on a counter 33 and whose output is outputted to an address generation circuit 19. On the other hand, whenever a block synchronizing signal is inputted from a synchronizing signal detection circuit 13, a count value is increased by +1. Then, when the error is judged by the check circuit 15, the content of the latch circuit 16 is not loaded on the counter 33 and the block address value at this time is interpolated as +1 of a former block value and outputted to the address generation circuit 19. Then, since a write signal is outputted to a storage circuit 21 by a write control circuit 40, the data is written in a position indicated by the interpolated address in the storage circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rotary head type digital signal reproducing apparatus used in a digital audio tape recorder using a rotary head.

[0002]

2. Description of the Related Art Digital audio tape record data, for example, has been commercialized as a rotary head type recording / reproducing apparatus. FIG. 5 is a diagram showing a tape format in a general rotary head type digital signal reproducing apparatus.
In the figure, 1 is a magnetic tape, 2A is a rotary magnetic head A.
Tracks recorded by 2B are rotary magnetic heads B
Tracks that are recorded by the tape 1 and are alternately formed obliquely with respect to the longitudinal direction of the tape 1. The heads A and B
Have different azimuth angles and are provided on the drum at intervals of about 180 °. One truck 2A
(2B) is divided into 196 data blocks, of which 128 blocks in the central portion are PCM areas in which audio data is recorded. The ATF areas at both ends of the PCM area are areas in which tracking signals are recorded, and in the conventional device, track control of the tracks 2A and 2B was performed using the tracking signals. Recently, as disclosed in Japanese Patent Application Laid-Open No. 62-140203, tracking control is not performed, and the heads A and B are scanned a plurality of times to read the reproduced signals on the tracks 2A and 2B twice or more and store them. A method called no-tracking has been developed in which data for one track is combined and reproduced by a means.

In order to realize the above-mentioned no-tracking control, a claim address indicating an address for each track and a block address indicating an address in the track are used, but they are recorded in the PCM area.

FIG. 6 is a diagram showing PCM data blocks and W ₁ and W ₂ formats in the tape format of FIG. In the figure, 3 is an 8-bit block synchronization signal, 4 is an 8-bit Main-ID (W ₁ ), 5 is an 8-bit block address (W ₂ ),
Reference numeral 6 is parity data for detecting errors of W ₁ and W ₂ and is composed of 8 bits. 7 is 256 PCM data consisting of audio data and Cl code for error detection
It is composed of bits (32 symbols).

The Main-ID 4 has a format ID (FI) when the block address 5 is an even block.
D), identification information of ID1 to ID7 and the frame address are recorded, and the identification information includes a sampling frequency, the number of channels, and the like. The same frame address is given to the tracks 2A and 2B.

FIG. 8 is a block diagram showing a reproducing circuit in a conventional rotary head type digital signal reproducing apparatus. In the figure, 10 is an input terminal for a reproduced signal, and 11 is a phase locked loop (PLL) circuit for obtaining a synchronous clock for the reproduced signal. Reference numeral 12 is a demodulation circuit that demodulates data subjected to 8-10 modulation, 13 is a circuit that detects the block synchronization signal 3, and 14 is an operation of each unit based on signals from the PLL circuit 11 and the block synchronization signal detection circuit 13. A clock generation circuit for generating a clock, and 15 is a Main
A parity check circuit for detecting an error in the ID4 and block address 5 from the parity data 6, 16 for a latch circuit for holding a block address, 17 for a latch circuit for holding a frame address, 21 a storage circuit composed of RAM or the like. , 19 is a circuit for generating an address of the memory circuit 21, and 20 is a circuit for controlling a write address to the memory circuit 21 in accordance with a data error detection. 22 is the C
A circuit for detecting an error in audio data using the l code, and 23 is a shift register for sending the audio data to the error detection circuit 22 symbol by symbol.
Is also connected to. Reference numeral 24 is an error correction circuit, 25 is a circuit for interpolating uncorrectable data, and 26 is a D / A converter.

Next, the operation will be described. Input terminal 10
The reproduced signal further input is demodulated by the demodulation circuit 12 through the PLL circuit 11 and is sent to the subsequent stage for every one data symbol. At this time, the PLL circuit 11 is based on the block synchronization signal 3 detected by the synchronization signal detection circuit 13.
The clock generation circuit 14 generates an operation clock for each unit by the synchronous clock generated in step. The block address 5 in the data of each block is latched by the block address latch circuit 16 after the block sync signal 3 is detected by the sync signal detection circuit 13, and at the same time, in the parity check circuit 15, Main-ID 4 (W ₁ ) and the block address ( W ₂ ) 5 error detection is performed. The frame address in the Main-ID 4 shown in FIG. 6 is latched by the frame address latch circuit 17 when the parity check circuit 15 determines that there is no error and the block address latch circuit 16 latches an even block.
Based on the contents of the block address latch circuit 16 and the frame address latch circuit 17, the address generation circuit 19 generates an address to the storage circuit 21. On the other hand, if the parity check circuit 15 detects an error as a result of the error detection, the determination result is input to the write control circuit 20 and a write inhibit signal is sent to the memory circuit 21. Therefore, data write is inhibited. It Further, when it is determined that there is no error, the determination result is written in the memory circuit 21 and treated as a rewrite flag indicating that the content of the memory circuit 21 has been changed.

Next, the PCM data 7 is divided into an even number and an odd number as shown in FIG. 7, and the audio data in the PCM data 7 is subjected to error detection by using a Cl code. In this operation, P output by the demodulation circuit 12
The CM data 7 is input to the shift register 23, and its output is sent to the error detection circuit 22 symbol by symbol. The error detection result is written in the storage circuit 21 together with the audio data. However, since the reproduction signal is read twice or more in the reproducing apparatus using the non-tracking method, the data of the same address may be written in the storage circuit 21 at least twice. In the above case, the write control circuit 20 reads the rewrite flag and the error detection result added to the data at the write address position indicated by the address generation circuit 19 in the memory circuit 21 before writing the audio data, The memory circuit 21 is instructed to perform such an operation.

When there is no rewrite flag, the write control circuit outputs a write signal regardless of the error detection result.

When the rewrite flag is present, the write control circuit outputs a write signal only when there is an error as a result of the error detection.

Therefore, the memory circuit 21 is always replaced with the data determined to have no error as a result of the error detection. However, at the time when the content of the memory circuit 21 is error-corrected, the rewriting flag is not present or the data added as an error as a result of the error detection is added as error data by the error correction circuit 24. Corrected. At this time, the uncorrectable data is subjected to interpolation processing such as average value interpolation and pre-hold using the correct data before and after in the interpolation circuit 25, and then converted into an analog signal in the D / A converter 26. ..

[0012]

In the conventional device described above, the data determined to be error-free by the parity check circuit 15 is stored in the storage circuit 2 by the write control circuit 20.
Writing data to 1 is prohibited. Therefore, even data determined to have no error as a result of error detection in the error detection circuit 22 is discarded. Therefore, in the case where the no-tracking control is performed as described above, the data is read twice, and only the correct data is selected and reproduced, even if it is determined from the above that the error detection result is no error,
If the parity check circuit 15 determines that there is an error, the data is not written. Therefore, there is a problem that the error correction processing in the error correction circuit 24 is burdened by an increase in residual error data during error correction processing of the contents of the storage circuit 21.

The present invention has been made in order to solve the above-mentioned problems. The error detection result of the error detection circuit 22 determines that there is no error, and the parity check circuit 15 determines that the data is error. In the case of occurrence of the error, the object is to obtain a rotary head type digital signal reproducing device for determining the write address for the memory circuit 21.

[0014]

According to a first aspect of the present invention, in a reproducing apparatus for reproducing a recording medium having a plurality of blocks composed of a plurality of data symbols on a recording track, an error of a block address signal for each block. A first error detecting means for detecting the error, a second error detecting means for detecting an error in the data symbol for each block, and a case where no error is detected in the error detecting by the first error detecting means, Holding means for holding the block address signal, means for interpolating the block address signal based on the content of the holding means when it is determined in the error detection by the first error detecting means that there is an error, Based on the block address signal interpolated by the interpolating means, the data symbol is stored in the storing means, and the second symbol is stored.
In this configuration, an interpolation flag indicating that the block address signal is interpolated is added to the error detection result of the storage means.

A second aspect of the present invention is an apparatus for scanning the recording medium at a speed multiple times that at the time of recording to reproduce the same signal a plurality of times, and detecting an error in the block address signal for each block. First error detecting means, second error detecting means for detecting an error in the data symbol for each block, and holding means for holding the error detection results of the first and second error detecting means, A control means is provided for selecting and fetching the data symbol in the storage means based on the contents held in the holding means and the error detection results of the first and second error detecting means.

A fourth invention of the present invention is, in a reproducing apparatus for reproducing the recording medium, an error detecting means for detecting an error of a block address signal for each block, and a result of error detection by the error detecting means, A holding unit that holds the block address signal that is determined to have no error, a measuring unit that measures the number of blocks in which an error has been detected when the error detecting unit continuously detects an error, and a measuring unit of the measuring unit. An adding means for adding the measured value and the block address signal held in the holding means; an interpolating means for interpolating the block address signal determined to be erroneous by the error detecting means based on the addition result of the adding means; Interpolation block evaluation means for comparing the contents of the holding means and the addition means to evaluate the interpolation result of the interpolation means is provided.

Further, in the fourth invention of the present invention,
In a reproducing apparatus for reproducing the recording medium, first error detecting means for detecting an error in a block address signal for each block, and the block address signal detected as no error as a result of error detection by the error detecting means. Means for holding
The second error detecting means for detecting an error in the data symbol and the second error detecting means determine that the data symbol in the unit block composed of the plurality of blocks is error-free, and When the block address signal of No. 1 is judged to be erroneous by the first error judging unit, an interpolating unit for interpolating the erroneous block address signal based on the contents of the holding unit is provided.

[0018]

The block address signal determined to be correct by the first error detecting means in the first aspect of the present invention is held in the holding means, and the block address signal in which an error is detected is interpolated by the interpolating means. Then, the data symbol is taken into the storage means by the interpolation means, and the interpolation flag is added to the error detection result of the second error detection means.

The control means in the second aspect of the present invention selects the data symbol to be stored in the storage means from the error detection results of the first and second error detection means based on the contents of the holding means. ..

In a third aspect of the present invention, when the error detecting means determines that the block address signal is in error, the measuring means calculates the number of consecutively erroneous block address signals, The contents of the holding means and the measurement result of the measuring means are added by the adding means, and the interpolating means interpolates the block address signal determined to be erroneous from the addition result of the adding means.
The interpolation block evaluation means evaluates the interpolation result.

In a fourth aspect of the present invention, when the first address detecting means detects an error in the block address signal in the unit block, the second error detecting means detects no error. In this case, the block address signal in which the error is detected is interpolated by the interpolation means based on the contents of the holding means.

[0022]

EXAMPLES Example 1. FIG. 1 is a block diagram showing a signal portion of a rotary head type digital reproducing apparatus in Embodiments 1 to 4 of the present invention. In the figure, the description of the same parts as those of the conventional example is omitted. Reference numeral 18 denotes an address interpolation circuit which interpolates the contents of the block address latch circuit 16 when it is determined as an error as a result of error detection in the parity check circuit. The output of the address interpolation circuit 18 is the address generation circuit 1
9 and is configured so that a write address to the storage circuit 21 is generated by the interpolated address. FIG. 2 shows the contents of the interpolation circuit 18, where 30 is a terminal for inputting an error detection result output in the parity check circuit 15, 31 is a terminal for inputting the contents of the block address latch circuit 16, and 32 is a sync signal detection. Terminals for inputting the block synchronization signal 3 from the circuit 13, 3
Reference numeral 3 is a counter, and 34 is a terminal for outputting the count value of the counter 33 to the address generation circuit 19. Also, FIG.
40 is a write control circuit.

Next, the operation will be described. When the parity check circuit 15 determines that there is no error in the error detection result, the detection result is input from the input terminal 30 to the counter 33, which serves as the load input of the contents of the input terminal 31 to the counter 33. That is, if there is no error, the contents of the block address latch circuit 16 are loaded into the counter 33 from the above, and the output is output from the output terminal 34 to the address generation circuit 19. On the other hand, since the input terminal 32 is connected to the clock input of the counter 33, the count value is incremented by +1 each time the block synchronization signal 3 is input from the synchronization signal circuit 13. Therefore, when the parity check circuit 15 determines that there is an error from the above, the content of the block address latch circuit 16 is not loaded into the counter 33, and the block address value in this case is interpolated as the value of the previous block + 1 and the address generation circuit. Is output to. Although the counter with a load is used in the above embodiment, generally, a holding means such as a latch for holding the contents of the block address latch 16 only when the parity check circuit 15 determines that there is no error, and the holding means. If the interpolating circuit is configured by an interpolating unit including an adder or a subtracter that interpolates the contents of the above with the block synchronization signal 3 or another reference signal to a predetermined value, the same operation as the counter 33 can be performed. it can.

When the interpolating operation is performed by the interpolating circuit, the parity check circuit 15 does not input the rewriting flake shown in the conventional example to the memory circuit 21, so that the error correcting circuit 24 stores the memory circuit. Among the contents of 21, the data at the position indicated by the address is processed as erroneous, and the block address is interpolated, so that the reliability of the data is not lost.

Next, since the write control circuit 40 outputs a write signal to the storage circuit 21, the storage circuit 2
In 1, audio data is written at the position indicated by the interpolated address. However, as shown in the above-mentioned conventional example, when the error detection circuit 22 determines that there is an error in the data, the error detection result is also added to the storage circuit 21 as described above.

Example 2. Further, as shown in the above-mentioned conventional example, when the data is read twice or more, the second embodiment of the present invention will be described with reference to FIG. Incidentally, the same parts as in the conventional example are omitted. Reference numeral 40 denotes a write control circuit, which reads the above-mentioned rewrite flag and the above-mentioned error detection result that have been added together with data from the memory circuit 21 to the position indicated by the address generation circuit 19, and writes to the memory circuit 21 based on their contents. It is configured to output a signal. Thereafter, the presence or absence of the rewrite flag is prioritized over the presence or absence of the error detection result, and the following operation is performed.

If there is no rewrite flag and if there is a data error in the error detection result, a write signal is unconditionally output, the audio data is written to the storage circuit 21, and the rewrite flag is added to the parity check circuit 15 when there is no error. If the error detection circuit 22 has an error, the error detection result is added. Thereafter, the correction circuit 22 has the above-mentioned rewrite flag, and if there is no data error in the above error detection result, the correction circuit 22 processes as correct data.

When there is no rewriting flag and there is no data error in the error detection result, and when the parity check circuit 15 determines that there is no error, a write signal is output and the audio data is written to the memory circuit 21.
Add the rewrite flag. At this time, the error detection circuit 2
When it is determined that there is a data error in 2, the content of the storage circuit 21 is rewritten and the error detection result is also added, so that the error correction circuit 22 processes it as error data at the time of correction. However, erroneous data will be written in the portion where there is no data error. From the above, the state in which there is no rewrite flag means that the memory circuit 21 has not accessed the address at all, or the address is a predetermined value. Since the case where the data is written after being interpolated into the value, the reliability is low even if there is no data error, and there is a possibility that a miss error or an erroneous correction may be induced in the correction processing stage in the error correction circuit 22. Because there is. Furthermore, even if there is a data error, if the write address is correct, unless the data symbol is completely error, the possibility of being corrected increases if the above correction process is repeated a plurality of times. It is also proposed to give priority to the accuracy of the address rather than the priority.

Only when the rewrite flag is present, when there is a data error in the error detection result, the parity check circuit 15 determines that there is no error, and when the error detection result in the error detection circuit 22 determines that there is no data error. A write signal is output, audio data is written to the storage circuit 21, and a rewrite flag is added.

When the rewrite flag is present and there is no data error in the error detection result, the write is unconditionally prohibited and neither the rewrite flag nor the error detection result is added.

As described above, in the present invention, →→→
The contents of the storage circuit 21 are rewritten with more reliable data in this order, and the load of the correction processing in the error correction circuit 22 is reduced.

Example 3. FIG. 1 is a block diagram showing a signal processing portion of a rotary head type digital signal reproducing apparatus in Embodiments 1 to 4 of the present invention. In the figure, the description of the same parts as those in the conventional example will be omitted. 18 is the result of error detection in the parity check circuit, when it is determined that there is an error,
An address interpolation circuit that interpolates the contents of the block address latch circuit 16. Reference numeral 40 is a write control circuit that controls writing of data to the storage circuit 21.

FIG. 3 shows the contents of the address interpolation circuit 18, wherein 31 is a terminal for inputting the contents of the block address latch 16, 30 is a terminal for inputting an error detection result in the parity check circuit 15, and 32 is a synchronization. A terminal for inputting the block synchronization signal 3 from the detection circuit 13;
Is a latch for temporarily storing the block address input from the input terminal 31 when it is determined that there is no error in the error detection result input from the input terminal 30. Three
A counter 8 is reset when the result of the error detection is determined to be no error, and is counted by the block synchronization signal 3 input from the input terminal 32. 39 is an adder for adding the contents of the latch 37 and the counter 38, 4
2 is an interpolation number determination circuit, 41 is a comparator, and the output of the selector 42 is output from the output terminal 34 of the address generation circuit 19
The output of the comparator 41 is output from the output terminal of 35 to the write control circuit 40, and the output of the interpolation number determination circuit 42 is output from the output terminal of 36 to the write control circuit 40.

Next, the operation will be described. When the parity check circuit 15 determines that there is no error, the determination result output is input to the input terminal 30 and the counter 38
Is reset and the contents of the block address latch 16 input from the input terminal 31 are stored in the latch 37. Below, when the block synchronization signal 3 of the next block is detected, the detection signal is input from the input terminal 32 and the counter 3
8 is counted up, but after that, the operation of the next stage differs depending on the error detection result in the parity check circuit 15, so these will be described separately.

If there is no error in the above, the input terminal 3
Since the determination result output of the block A is input from 0, the address of the block A which is the content of the block address latch circuit 16 is stored in the latch 37. At this time, since the counter 38 is reset, its value is 0, the output of the adder 39 becomes the same value as the latch 37, that is, the address of the block A, which is output from the output terminal 34 and input to the address generation circuit 19. It The value of the latch 37 and the value of the adder 39 are compared by the comparator 41, but since they are the same value, the rewrite flag shown in the above-mentioned conventional example is written to the memory circuit 21 from the output terminal 35 to the write control circuit. Instructions are given. Further, the interpolation number determination circuit 42 inputs the reset value of the counter 38, determines that there is no interpolation, and outputs the result from the output terminal 36.

Next, the case where the address of the block A is input to the latch 37 and the next block B is determined to be an error as a result of the error detection of the parity check circuit 15 will be described. When the reset signal of the counter 38 is not input from the input terminal 30 and the block synchronization signal 3 of the block B is input from the input terminal 32, the value of the counter 38 becomes +1 and the adder 39 latches 37.
And the value of block B = block A + 1, and the value of block B is +1 interpolated and output from the output terminal 34. Further, the value of the latch 37 and the value of the adder 39 are compared by the comparator 41 and become different values from the above,
The instruction signal for adding the rewrite flag is not output from the output terminal 35. In other words, the memory circuit 21 processes the address as if it were interpolated. On the other hand, in the interpolation number determination circuit 42, the value of the counter 38 is input and the number of interpolations 1 is output from the output terminal 36.

1 if the error is continuously determined.
The counter 38 counts up for each block, and the value of the counter 38 and the value of the latch 37 are added by the adder 39 and output from the output terminal 34 as an interpolation address. The interpolation number determination circuit 42 outputs the interpolation number from the output terminal 36.
After the above operation, when the parity check circuit 15 determines that there is no error, the latch 37 is updated with the new block address value block C output from the block address latch 16 and the counter 38 is reset. Therefore, the block C is output from the adder 39,
A signal for adding the rewrite flag is output from the comparator 41 to the output terminal 35. At this time, the counter 3
8 is reset, and the interpolation count determination circuit 42 indicates that the interpolation count value up to that time has reached 0.
Instruct to. In the above case, when it is instructed that the write control circuit 40 has become 0, the write control circuit 40 compares whether the value obtained by adding 1 to the address at the time when it becomes 0 and the interpolated address immediately before becoming 0 are equal. .. If they match, the interpolation address is correct, and the data at the position corresponding to the part where the rewrite flag is not added from the address traced back the previous number of interpolations to the address immediately before becoming 0. On the other hand, the storage circuit 21 is instructed to write the rewrite flag. With the configuration as described above, since the address is interpolated with respect to the data determined to have no data error by the error detection circuit 22, the rewrite flag is not added and the error correction circuit 24
Are prevented from being processed as error data.

Due to the occurrence of the burst error, address interpolation is continuously generated, and when the number of interpolations is larger than a predetermined threshold value, the operation of adding the rewrite flag is prohibited. Control circuit 40
The reliability of the address comparison operation is improved.

Example 4. FIG. 1 is a block diagram showing a signal processing portion of a rotary head type digital signal reproducing apparatus in Embodiments 1 to 4 of the present invention. In the figure, the description of the same parts as those in the conventional example will be omitted. Reference numeral 18 is an address interpolation circuit, 40 is a writing control circuit, and 22 is an error determination circuit. FIG. 4 is a diagram showing a fourth embodiment of the present invention, so to speak, showing the contents of the address interpolation circuit 18 and the error correction circuit 22, in which 45 is a parity check circuit 15.
When it is determined that there is no error in, the terminal for inputting the determination result, 46 is a terminal for inputting the contents of the block address latch circuit 16, 47 is a latch, and 48 is a terminal for inputting the demodulated PCM data 7. Reference numeral 49 is an even symbol error determination circuit that detects a data error using even symbol data of the PCM data 7 for two blocks shown in FIG.
Reference numeral 50 is an odd symbol error judgment circuit for detecting a data error using the odd symbol data of the PCM data 7, 51 is an even and odd symbol error judgment circuit 4 at the time when the block synchronization signal 3 is detected for each block.
A determination circuit that determines that there is no data error when both of the error detection results of 9 and 50 are error-free, 52 is a comparator that compares the output of the determination circuit with the content of the latch 47 to which a predetermined value is added, Reference numeral 53 is a selector, and 54 and 55 are output terminals.

Next, the operation will be described. When the block A is reproduced and the result determined by the parity check circuit 15 that there is no error is input from the input terminal 45, the address of the block A which is the content of the block address latch 16 is input from the input terminal 46 to the latch 47. To be done. In the selector 53, the above determination result is input to the input terminal 45,
Selected to output the value of latch 47, output terminal 54
Is input to the address generation circuit 19. Therefore, the data is written in the position indicated by the address of the block A in the memory circuit 21, and the rewrite flag shown in the conventional example is also added.

When the parity check circuit 15 determines that there is an error in the next block B, the determination result is not input from the input terminal 45, so the value of the latch 47 is not updated, and the selector 53 causes the comparator to operate. The value of 52 is output to the output terminal 54. On the other hand, the demodulated data is input from the above from the input terminal 48, and
In the even-numbered symbols of the data of the two blocks shown by, the even-numbered symbol error determination circuit 49 detects a data error, and in the odd-numbered symbols, the odd-numbered symbol error determination circuit 50 detects a data error. The above-mentioned data error judgment is performed by the input terminal 48.
As a result, as shown in FIG. 7, the PCM data 7 is input in the order of even-numbered blocks and odd-numbered blocks, and when the final symbol data P ₇ of odd-numbered blocks is input, it is possible to determine whether or not there is an error, and the result is output. It The determination circuit 51 then determines that there is no error in both the data error determination results of both the even and odd symbol error determination circuits 49 and 50. Therefore, when the address of the previous block block A input to the latch 47 is input to the A input of the comparator 52, if it is an even number, or if the determination circuit 51 determines that there is no error, it is shown in FIG. Due to the data structure, the address value of the block B is an odd number and the address value of the block A is +1. Therefore, in the above case, the value of the latch 47 is incremented by 1 in the comparator 52, output to the selector 53, and output from the output terminal 54 to the address generation circuit 19. Further, since the output terminal 55 outputs the instruction signal for adding the rewrite flag to the write control circuit 40, the data is written in the memory circuit 21 and the rewrite flag is also added.

Next, when the address value of the previous block, block A, input to the latch 47 is an odd number, the latch 4
The value of 7 is incremented by 1 in the comparator 52, output to the selector 53, and output from the output terminal 54 to the address generation circuit 19. Therefore, the output address value of the block B takes an even value obtained by adding 1 to the address value of the block A, but at the time when the input of the even symbol data ends, the determination circuit 51
In this case, since no error determination is made, the instruction signal for adding the rewrite flag is not output from the comparator 52 to the output terminal 55. Therefore, only data is written in the memory circuit 21. Next block, block C
Is input, the parity check circuit 1
If there is no error as a result of the error detection in 5, the address value of the block C is input to the latch 47. Since the value of the latch 47 is odd again at this point, the comparator 52 compares the values before and after the latch 47 is updated and is +2. An instruction signal for adding a rewrite flag to the data in the memory circuit 21 corresponding to the address B is output from the output terminal 55 to the write control circuit 40. However, when the latch 47 is not updated as described above and the values before and after the update are the same in the comparator 52 or when the output of the determination circuit 51 has an error, the instruction signal is not output to the output terminal 55.
As described above, when there is an error in the address value of one of the blocks that have been coded for error correction in units of two blocks, it is determined that there is no error as a result of data error detection. If so, the other address is interpolated based on the address value of the block having no error.

[0043]

In the first embodiment according to the first aspect of the present invention, means is provided for holding the block address value when there is no error as a result of the block address error determination, and when there is an error. By providing the interpolation means for changing the content of the above holding means to a predetermined value,
If there is no error in the data and the block address is incorrect, the address is interpolated by the above-mentioned interpolating means and taken into the storage means, so that correct data can be prevented from being discarded, and the address can be interpolated. Since the error detection signal is added when the data is written in the storage means, when the data in the storage means is error-corrected,
Although there is an error detection signal at the above interpolation address position, the data is processed as being in a correct state, so correction is performed in both correction based on the error detection signal (erasure correction) and correction not using the error detection signal (error correction). This has the effect of reducing the burden on the user.

Embodiment 2 according to the second invention of the present invention
In this case, the rotary head is scanned multiple times and the data is
When reading more than once, the first detection result and the second and subsequent detection results are compared with the block address error detection means, the data error detection means, the block address error detection result, and the data error detection result. Since a means for deciding whether to write the data in the storage means is provided,
By reading the same data twice or more, the contents of the storage means can be rewritten to more error-free data, and when the error correction of the storage means, the data with higher reliability remains, so that the burden of error correction is increased. There is an effect that it can be reduced.

Embodiment 3 according to the third invention of the present invention
In the block address error detecting means, a means for holding the block address determined to be error-free as a result of the detection by the error detecting means, and a means for measuring the number of error of the block address thereafter on the basis of the error-free detection. Further, since the address interpolating circuit having the holding means and the means for adding the measurement values of the measuring means is provided, the addresses can be interpolated when the block addresses are continuously incorrect, so that the addresses are input to the storage means in between. If the correct block address is input to the holding means after the continuous error of the block addresses, the means for comparing the added value of the adding means with the content of the holding means is provided. Based on the comparison result, it is determined whether or not the continuous interpolation of the above addresses is correct, and if not, an error detection signal is added to the storage means. Since it is configured to, address erroneous when error correction by the interpolated correction, there is an effect that prevents also combined false detection errors.

Embodiment 4 according to the fourth invention of the present invention
, A first error determination means for detecting an error in a block address, a holding means for holding the block address when the first error determination means determines that there is no error, and an error with a plurality of blocks as one unit block. When the detection encoding is performed and the second error determining means for detecting an error in the data in the unit block and the first error determining means detect an error and the block address is in error, When the second error determining means determines that the data has no error, an interpolating means for interpolating the block address determined as the error based on the contents held in the holding means is provided, and therefore the unit When it is determined that there is no error in the data in the block, at least one block address in the unit block is held in the holding unit. Then, since another block address can be interpolated, the data can be taken into a predetermined position indicated by the block address in the storage means, and correct data can be efficiently obtained. This has the effect of reducing the burden of error correction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a signal processing portion of a rotary head type digital signal reproducing apparatus according to embodiments 1 to 4 of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram showing Embodiment 3 of the present invention.

FIG. 4 is a diagram showing Embodiment 4 of the present invention.

FIG. 5 is a diagram showing a tape format in a general rotary head type digital signal reproducing apparatus.

FIG. 6 is a diagram showing PCM data blocks and W ₁ and W ₂ formats in the tape format of FIG. 5;

FIG. 7 is a diagram showing a configuration of audio data and a Cl code.

FIG. 8 is a block diagram showing a reproducing circuit in a conventional rotary head type digital signal reproducing device.

[Explanation of symbols]

 15 parity check circuit 16 block address latch circuit 18 address interpolation circuit 19 address generation circuit 21 storage circuit 22 error determination circuit 33, 38 counter 37, 47 latch 39 adder 40 write control circuit 41, 52 comparator 42 interpolation number determination circuit 51 Judgment circuit 53 Selector

Claims (4)

[Claims] 1. A reproducing apparatus for reproducing a recording medium having a plurality of blocks of a plurality of data symbols on a recording track, the first error detecting means for detecting an error of a block address signal for each block, and the block. Second error detecting means for detecting an error in the data symbol for each time; holding means for holding the block address signal when it is determined that there is no error in the error detection of the first error detecting means; If it is determined that there is an error in the error detection of the error detection means of No. 1, the means for interpolating the block address signal based on the content of the holding means, and the block address signal interpolated by the interpolation means , The data symbol is taken into the storage means, and the block address signal is interpolated in the error detection result of the second error detection means. And an interpolation flag indicating that the error is stored in the storage means, and the error correction result is corrected by using the error detection result of the second error detection means and the interpolation flag. Rotating head type digital signal reproducing device. 2. A structure in which a recording medium having a plurality of blocks of a plurality of data symbols on a recording track is scanned by a rotary head at a speed multiple times that at the time of recording to reproduce the recording track a plurality of times. In the reproduced device, first error detecting means for detecting an error in the block address signal for each block, second error detecting means for detecting an error in the data symbol for each block, and the first and second Holding means for holding the error detection result of the second error detecting means, the contents held in the holding means, and the data stored in the storing means based on the error detection results of the first and second error detecting means. A rotary head type device characterized in that it comprises control means for selecting and loading symbols and is constructed so that error correction in the storage means is carried out based on the contents of the holding means. Digital signal reproduction device. 3. A reproducing apparatus for reproducing a recording medium having a plurality of blocks composed of a plurality of data symbols on a recording track, an error detecting means for detecting an error of a block address signal for each block, and an error of the error detecting means. As a result of the detection, holding means for holding the block address signal determined to have no error, the error detecting means, when errors are continuously detected, measuring means for measuring the number of blocks in which an error is detected, Addition means for adding the measured value of the measuring means and the block address signal held in the holding means, and the block address signal determined to be erroneous by the error detecting means based on the addition result of the adding means are interpolated. The interpolation block is provided with interpolation block evaluation means for comparing the contents of the holding means and the addition means to evaluate the interpolation result of the interpolation means. When the clock evaluation means has an error in the interpolation result of the interpolation means, the data symbol corresponding to the interpolated block address signal is made to be an error. apparatus. 4. A reproducing apparatus for reproducing a recording medium having a plurality of blocks of a plurality of data symbols on a recording track, the plurality of blocks being one unit, and the data symbols being encoded for error detection. In the above, first error detecting means for detecting an error in the block address signal for each block, holding means for holding the block address signal detected as having no error as a result of error detection by the error detecting means, The second error detecting means for detecting an error in the data symbol and the second error detecting means determine that the data symbol in the unit block is error-free, and the block address signal in the unit block is the first address. When the error determining means of No. 1 determines an error, the interpolation means for interpolating the erroneous block address signal based on the contents of the holding means. A rotary head type digital signal reproducing apparatus having a stage so that when at least one block address signal in the unit block is held in a holding means, another block address signal can be interpolated. ..