JPH05265405A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To overcome the limit of gradation control resulting of an error due to the output deviation of a data driver and to improve the display quality by detecting and storing the output deviation of the data driver, and subtracting the value from a video signal and correcting the video signal. CONSTITUTION:In a period of vertical synchronism (non-display period of video signal) wherein a signal for display is stopped, a reference voltage VR is selected by a switch means 4 to put the data driver 2 in operation, and the difference between the selection output obtained from the data driver through a demultiplexer means 3 and a reference voltage is measured (by offset quantity measuring means 5), whose measurement data are stored as correction data in a memory means 6. In a display period which is not the vertical synchronism period, the correction data are taken out of the memory means 6 and the voltage quantity corresponding to the correction data is subtracted from the arriving video signal (corrective operation). Therefore, the offset voltage that the data driver can be set to zero (0) in principle and a multi-gradational display can be made.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a liquid crystal display device (LC
The present invention relates to D), and particularly relates to improvement of display quality of the LCD. LCDs are expected to replace conventional CRTs and are expected to develop into large-scale markets. Among these, especially thin film transistors (TFTs)
Since an LCD using a film transistor is capable of high quality display in principle, it is expected to become the mainstream of high quality and high definition color display.

[0002]

2. Description of the Related Art In an LCD using a TFT, the TFT is used as a switching element, and an analog voltage signal (information) proportional to the magnitude of a video signal is written through the TFT corresponding to the liquid crystal capacity of each pixel. The image is displayed. FIG. 6 shows a circuit configuration of a liquid crystal display device as a conventional example.

In the illustrated example, the number of pixels is shown as 4 × 4 for simplification of description, but in reality, the number of pixels is 64.
About 0 × 480 is a typical example, and the number of pixels is three times as large as this for color display. In the figure, LCD indicates a liquid crystal display section (liquid crystal panel), of which P11 to P
Reference numeral 44 represents a minimum display unit called a pixel. Each of the pixels P11 to P44 is arranged at the intersection of the plurality of data lines X1 to X4 and the plurality of gate lines Y1 to Y4, and transmits the voltage information on the corresponding data line when the corresponding gate line is selected. It is composed of a transfer gate transistor (TFT) and a liquid crystal capacitor for storing information transmitted through the corresponding transistor.
This liquid crystal capacitor has a size of about 1 pF in the case of a color of 640 × 480 pixels on a 10.4 inch liquid crystal panel, for example. Video information from a video source such as a personal computer is C
As in the case of RT, it is a typical example that it is given as a horizontal synchronizing signal HS, a vertical synchronizing signal VS, a clock CK and a video signal VG. In the case of color display, the video signal VG is composed of three signals of red (R), green (G) and blue (B), but in the example of FIG. 6 it is shown for monochrome display for simplification of description. is there.

In order to write a video signal to each pixel, data for each line is applied to the data lines X1 to X4 from the data driver DD ', while only one of the gate lines Y1 to Y4 is sequentially operated by the TFT. As the voltage to turn on,
A video signal is written in the liquid crystal capacitance through the TFT. CO
Reference numeral NT denotes a controller for controlling the entire liquid crystal display device, which generates various control signals for writing the video signal VG in response to the horizontal synchronizing signal HS, the vertical synchronizing signal VS and the clock CK.

The data driver DD 'is composed of a two-stage sample and hold circuit driven by the shift register SR1. First stage sample and hold circuit (switches S11 to S14 and holding capacitors C1 to C)
In 4), the video signal VG is sequentially sampled by the signals (S11 to S14) from the shift register SR1. 1
When the sampling to the sample-hold circuit of the second stage is completed, the held signal is transferred to the sample-hold circuit of the second stage (switches S21 to S24 and holding capacitors C5 to C8).
The switches S21 to S24 are simultaneously turned on by the control signal T2 from. As a result, the holding signal is written in the capacitors C5 to C8 and output to the data lines X1 to X4. On the other hand, the first stage sample and hold circuit
Give up to hold the video signal of the next data line.
B1 to B8 denote buffer drivers for stably outputting the sampled and held signals to the next stage.

On the other hand, the gate driver GD includes a shift register SR2 which operates in response to the clock CK2 and the activation signal T3 from the controller CONT, and a corresponding gate line Y1 based on the output of the shift register.
.. to Y4, and binary drivers D1 to D4. Further, the video signal VG is composed of two-stage addition amplifiers A1 and A2 (including resistors R1 to R3 and R5).
Through the data driver DD '.

[0007]

In order to realize a display that replaces a high quality CRT, a so-called "full color" is used.
Need to be able to display. A typical example of the number of colors required in the case of full color is 16.77 million colors. To this end, 256 levels of gradation control are required for each of R, G and B. That is, by combining the colors R, G, and B, 256 × 256 × 256 = 16,77
It is possible to represent 7,216 colors.

FIG. 7 shows the relationship between the liquid crystal transmittance and the control voltage. As shown in the figure, since a control voltage of about 2V to 6V is required for 0% to 100% transmittance, 4/256 ≈ 4256 to control this in 256 steps.
It becomes 15 mV. This means that the accuracy of the control voltage by the data driver DD 'needs to be within 15 mV. However, in reality, the output deviation of the data driver DD ′, which is the key to this, is about 200 mV at present. There are two main causes for this error.

One is due to the offset voltage of the operational amplifier (op amp) used in the data driver DD '. It is said that this is caused by the fact that the operational amplifier is composed of a MOS transistor for high integration and the threshold voltage (Vth) which is an important characteristic thereof is unstable. The other is due to the so-called charge offset unique to the sample and hold circuit. This is said to be caused by current leakage from the control signal side of the analog switch used in the sample and hold circuit, which changes the charge held in the holding capacitor.

The charge offset will be described below with reference to FIG. The charge / offset voltage of the sample-hold circuit shown in the figure is the capacitance CG1, which is the control voltage between the gate and drain of the analog switch when the analog switches Q1 and Q2 are turned off.
This is caused by changing the holding charges of the holding capacitors CA and CB through CG2. Specifically, the value is [CG1 / (CG1 + CA)] × (V1 + V2)
Or [CG2 / (CG2 + CB)] × (V1 + V2)
It is represented by. The actual value of the charge offset, which is a problem, is not the absolute value but the variation between the elements. The actual variation value is about 200 mV including the offset voltage of the operational amplifiers A11 and A12. As a data driver, reducing these values is a major design goal, but it is extremely difficult with the current technology to fundamentally reduce the output deviation.

In FIG. 8, QA is a control signal VC.
1 is a transistor for controlling ON / OFF of the analog switch Q1 in response to 1, a transistor for controlling ON / OFF of the analog switch Q2 in response to the control signal VC2, and + V1 is for turning on the switches Q1 and Q2. The voltage for turning off, -V2, shows the voltage for turning off the switches Q1 and Q2.

The present invention was created in view of the above problems in the prior art, and can overcome the limitation of gradation control due to an error caused by an output deviation in a data driver, and contribute to improvement of display quality. An object is to provide a liquid crystal display device.

[0013]

In order to solve the above problems, the present invention detects an output deviation of a data driver, temporarily stores the value, and subtracts the value from a video signal (correction operation) to obtain the value. The video signal is corrected.
Therefore, the liquid crystal display device of the present invention has a plurality of display elements Pij arranged in a matrix along a plurality of data lines and a plurality of gate lines, as shown in the principle configuration diagram of FIG. 1, and is selected. A liquid crystal display unit 1 for writing and displaying a video signal from a corresponding data line to a display element, and sample-holding an input signal and outputting the plurality of held values to the corresponding data line, respectively. A data driver 2 having a multiplexer means 3 for selectively outputting any one of a plurality of held values;
A switch means 4 for selecting either the video signal VG or the reference voltage VR and connecting it to a plurality of input terminals of the data driver, and an offset between the output of the data driver selected and output by the multiplexer means and the reference voltage. Means 5 for measuring the amount, memory means 6 for storing data indicating the measured offset amount as correction data, and at least the clock driver CK and the vertical synchronizing signal VS in response to the data driver, the switch means and the memory means. And a control means 7 for performing various controls for writing and displaying the video signal.

[0014]

According to the above-described structure, during the vertical synchronization period (video signal non-display period) during which the display signal is paused,
The reference voltage VR is selected by the switch means 4 to operate the data driver 2, the difference between the selected output obtained from the data driver through the multiplexer means 3 and the reference voltage is measured (offset amount measuring means 5), and the measurement is performed. The data is stored in the memory means 6 as correction data. Then, during the display period which is not the vertical synchronization period, the correction data is taken out from the memory means 6 and the voltage amount corresponding to the correction data is subtracted from the incoming video signal (that is, correction calculation).

As a result, the offset voltage possessed by the data driver can be set to zero (0) in principle, and eventually, multi-gradation display can be performed. Details of other structural features and operations of the present invention will be described using embodiments described below with reference to the accompanying drawings.

[0016]

FIG. 2 shows a circuit configuration of a liquid crystal display device according to a first embodiment of the present invention. The following is a supplementary explanation of the principle configuration diagram of FIG. In addition, in FIG.
The same reference numerals as those shown in FIG. 6 represent the same components, and the description thereof will be omitted.

In the configuration of FIG. 2, the data driver DD
In order to select the output of each driver inside and generate the offset voltage, the internal operation must be exactly the same as when sampling the video signal VG. Therefore, even when the analog switch SB is turned on and the reference voltage VR is used as its input, the start signal T1 of the shift register SR1 is generated and the clock CK is generated.
1 is input to operate the shift register SR1. However, since one vertical synchronization period is short, it is not possible to calculate the output offset voltage for all the data drivers in one vertical synchronization period.
It is a reasonable way to do it during the vertical synchronization period.

Therefore, the counter CT1 is set to 1 to determine which output of the data driver DD the offset voltage is to be collected.
Step once in the frame and specify the signal through the decoder DC. At the same time, the counter CT1 is also used for addressing the offset voltage when the offset voltage is A / D converted and collected in the memory MEM. Memory MEM
The contents of is designated by the two counters CT1 and CT2, and this switching is performed by applying the switching signal T5 to the switch SW. The counter CT2 is used to extract the correction value in the memory MEM when the video signal VG arrives and correction is required. As a result, the correction data in the memory MEM is converted into an analog signal by the D / A converter DAC, subtracted (that is, correction calculation) from the video signal VG, and supplied to the data driver DD. The counter CT2 is reset to zero (0) by the clear signal T6, and is given by the clock CK3 in a cycle synchronized with the video signal.

In this way, as a result of correcting the offset voltage of the data driver DD in the video signal VG, the output deviation can be eliminated. At this time, naturally, the analog switch SA is turned on and the analog switch SB is turned off. Now, in order to turn on the analog switch SB and measure the offset voltage of the data driver DD, the reference voltage VR is input to the data driver DD through this switch SB, and the data driver DD is operated in the same manner as in the display period to set the reference voltage VR. The operation of sampling and holding the voltage signal VR is performed. That is, the output voltage when the input is VR is obtained, and the differential amplifier A3 performs the operation of calculating the difference between the value and the reference voltage VR, and the output is A / D converted. Then, the value is stored in the memory MEM.

Since the number of analog drivers provided is not one but the number of data lines, analog switches S1 to S4 for selecting only one of the outputs are provided in the data driver, and the output is set to 1 Collected and output as a multiplexer. The selection of the analog switch is performed by applying the output of the counter CT1 to the decoder DC and turning on only one of the switches S1 to S4.

FIG. 3 shows a circuit configuration of a liquid crystal display device according to a second embodiment of the present invention. The difference from the embodiment of FIG. 2 is that after the calculation for calculating the offset amount with respect to the reference voltage VR is performed, the correction value in the memory MEM is output to the up / down counter CT3, and the D / A converter D
The result of D / A conversion through AC1 is compared with the analog data corresponding to the offset amount, and as a result,
If the value in the memory MEM is large, the value of the counter CT3 is decreased by 1 count, and if the value is small, the value of the counter CT3 is increased by 1 count, and then the value is stored in the memory MEM again. That is the point to do The analog comparator CP1 is used for this comparison.

According to the present embodiment, in addition to the effect obtained in the embodiment of FIG. 2, even if a malfunction due to noise occurs,
There is an advantage that it can have a kind of filter function of being within the error of 1 bit. FIG. 4 shows a circuit configuration of a liquid crystal display device according to the third embodiment of the present invention. The difference from the embodiment of FIG. 2 is that the calculation for correction during the display period of the video signal VG is performed as a digital value, and therefore the video signal VG is first digitized by the A / D converter ADC. To do. In this case, the analog switch SC is turned on and the analog switch SD is turned off based on the switching signal T7 from the controller CONT. On the other hand, during the non-display period of the video signal VG (that is, the vertical synchronization period), the analog switch SC is turned off and the analog switch SD is turned on.

FIG. 5 shows a circuit configuration of a liquid crystal display device according to a fourth embodiment of the present invention. The difference from the embodiment of FIG. 2 is that a parallel digital signal (output of the counter CT1) from outside the data driver DD is used as an instruction for sequentially designating outputs in the data driver DD (that is, address designation of the analog multiplexer). Counter CT4 provided inside the data driver DD instead of
This is done by the output signal of. Like the counter CT1, the counter CT4 is supplied with the clear signal T8 and the stepping clock CK4, and thereby operates so as to be completely synchronized with the counter CT1.

The embodiment of FIG. 5 has the advantage that the number of pins of the data driver DD involved in the addressing of the analog multiplexer can be reduced (to two in the example shown).

[0025]

As described above, according to the present invention, the limitation of the gradation control due to the error caused by the output deviation in the data driver is overcome, whereby the display of multiple gradations (that is, the improvement of the display quality) is achieved. Can be realized.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a liquid crystal display device of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a circuit configuration of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a circuit configuration of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a circuit configuration of a liquid crystal display device as an example of a conventional type.

FIG. 7 is a graph showing the relationship between liquid crystal transmittance and control voltage.

FIG. 8 is a circuit diagram for explaining a problem in the device of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Liquid crystal display part 2 ... Data driver 3 ... Multiplexer means 4 ... Switch means 5 ... Offset amount measuring means 6 ... Memory means 7 ... Control means A3 ... Differential amplifier (amplifier) CK ... Synchronous clock of video signal CONT ... Controller CT1 , CT2 ... Counter DC ... Decoder DD, DD1 ... Data driver HS ... Horizontal synchronization signal LCD ... Liquid crystal panel MEM ... Memory Pij ... Display element (pixel) SA, SB, S1 to S4 ... Switch SW ... Changeover switch VG ... Video signal VR … Reference voltage VS… Vertical sync signal

Claims (9)

[Claims] 1. A display device having a plurality of display elements (Pij) arranged in a matrix along a plurality of data lines and a plurality of gate lines, and a video signal from a data line corresponding to a selected display element. A liquid crystal display unit (1; LCD) for writing and displaying, and an input signal is sampled and held, and a plurality of held values are output to the corresponding data lines, and any one of the plurality of held values is selectively output. A data driver (2; DD, DD1) provided with multiplexer means (3; S1 to S4, DC) for selecting a plurality of data drivers by selecting either a video signal (VG) or a reference voltage (VR). Switch means (4; SA, SB) connected to the input terminal, output of the data driver selected and output by the multiplexer means, and the reference A means (5; A3) for measuring an offset amount with respect to the pressure, a memory means (6; MEM) for storing data instructing the measured offset amount as correction data, at least a clock (CK) and a vertical synchronization signal In response to (VS), control means (7; CONT, CT1, CT) for performing various controls for writing and displaying the video signal on the data driver, switch means and memory means.
2, SW), and operating the data driver by selecting the reference voltage by the switch means during the non-display period of the video signal,
Correction data indicating a difference between the selected output obtained from the data driver through the multiplexer means and the reference voltage is stored in the memory means, and the correction data is taken out during the display period of the video signal to obtain the video signal. A liquid crystal display device characterized by performing a correction calculation. 2. The multiplexer means comprises a plurality of analog switches (S1 to S4) respectively connected between a plurality of output terminals of the data driver and an input terminal of the offset amount measuring means, and the plurality of analog switches. 2. The liquid crystal display device according to claim 1, further comprising a decoder (DC) for sequentially selecting the addresses based on the address information. 3. The liquid crystal display device according to claim 2, wherein the address information supplied to the decoder is composed of a plurality of parallel digital signals. 4. The step-up clock (CK)
4. The liquid crystal display device according to claim 3, further comprising a first counter (CT1) responsive to 4), wherein the plurality of parallel digital signals are formed by the output of the first counter. 5. The step-up clock (CK)
3) and a second counter (CT2) which responds to the clear signal (T6), and either the output of the second counter or the output of the first counter by the switching signal (T5) to select the memory. Switch means (SW) for inputting to the means, and when the output of the first counter is selected, the correction data indicating the offset amount is stored in the memory means, and the output of the second counter is output. 5. The liquid crystal display device according to claim 4, wherein the correction data is retrieved from the memory means when is selected. 6. The data driver (DD1) further has a counter (CT4) responsive to a stepping clock (CK4) and a clear signal (T8) from the control means, and the multiplexer means is provided by the output of the counter. 3. The liquid crystal display device according to claim 2, wherein address information is formed for the decoder of. 7. Comparing correction data corresponding to the output of the data driver read from the memory means with data indicating an offset amount obtained from the offset amount measuring means during a non-display period of the video signal. Further comprising: an analog comparator (CP1) for performing the above; and counter means (CT3) for changing the count value based on the judgment output of the analog comparator, and the contents changed by the counter means are stored again in the memory means. 3. The method according to claim 2, wherein
The liquid crystal display device according to item 1. 8. A D / A converter (DA) for converting the correction data extracted from the memory means into an analog signal.
C, DAC1), and an operational amplifier (A2) for outputting the operation output value to the switch means in response to the output of the D / A converter and the video signal, and analog operation by the operation amplifier The liquid crystal display device according to claim 2, wherein the correction calculation of the video signal is performed by the following. 9. A switching signal (T
7), switch means (SC, SD) for selecting either the video signal (VG) or the output signal of the offset amount measuring means (A3), and the signal selected by the switch means is digitized. Further comprising an A / D converter (ADC) for outputting to the memory means, and correcting the video signal by digital operation based on the output digital data of the A / D converter and the correction data extracted from the memory means. The liquid crystal display device according to claim 2, wherein a calculation is performed.