JPH05218003A - Forming method for film for thin film transistor - Google Patents
Forming method for film for thin film transistorInfo
- Publication number
- JPH05218003A JPH05218003A JP1919592A JP1919592A JPH05218003A JP H05218003 A JPH05218003 A JP H05218003A JP 1919592 A JP1919592 A JP 1919592A JP 1919592 A JP1919592 A JP 1919592A JP H05218003 A JPH05218003 A JP H05218003A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- silicon semiconductor
- plasma
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Chemical Vapour Deposition (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、薄膜トランジスタ（Ｔ
ＦＴ）におけるアモルファスシリコン膜や多結晶シリコ
ン膜といったシリコン半導体膜と、これに積層されるゲ
ート絶縁膜（ＳｉＮｘ等）のプラズマＣＶＤ法による形
成方法に関する。The present invention relates to a thin film transistor (T
The present invention relates to a method of forming a silicon semiconductor film such as an amorphous silicon film or a polycrystalline silicon film in FT) and a gate insulating film (SiNx or the like) laminated thereon by a plasma CVD method.
【０００２】[0002]
【従来の技術】薄膜トランジスタにおけるシリコン半導
体膜やこれに積層されるゲート絶縁膜は、プラズマＣＶ
Ｄ法により形成されることが多い。この場合、それら膜
を形成するための原料ガスのプラズマ化は、所定周波数
の高周波電力を連続的に印加する連続放電によってい
る。2. Description of the Related Art A silicon semiconductor film in a thin film transistor and a gate insulating film laminated thereon are plasma CVs.
It is often formed by the D method. In this case, the raw material gas for forming the films is made into plasma by continuous discharge in which high frequency power of a predetermined frequency is continuously applied.
【０００３】[0003]
【発明が解決しようとする課題】しかし、このような連
続放電によるプラズマＣＶＤにより得られるシリコン半
導体膜やゲート絶縁膜はその表面粗度が３０Å〜５０Å
程度と平坦度がきわめて悪く、そのため、シリコン半導
体膜とこれに接するゲート絶縁膜の界面の平坦度が悪く
なり、その結果、ソース・ドレイン間の電子移動度が低
くなり（０．３ｃｍ2 ／Ｖ・Ｓ以下）、最終製品トラン
ジスタの性能が満足できるものでなくなるという問題が
あった。However, the surface roughness of a silicon semiconductor film or a gate insulating film obtained by plasma CVD by such continuous discharge is 30Å to 50Å.
The degree and flatness are extremely poor, so that the flatness of the interface between the silicon semiconductor film and the gate insulating film in contact therewith becomes poor, and as a result, the electron mobility between the source and the drain becomes low (0.3 cm 2 / V・ There was a problem that the performance of the final product transistor was not satisfactory.
【０００４】そこで本発明は、薄膜トランジスタ（ＴＦ
Ｔ）用のシリコン半導体膜及びこれに接するゲート絶縁
膜の界面の平坦度を向上させ、それによってＴＦＴにお
けるソース・ドレイン間の電子移動度を大きくさせ得る
プラズマＣＶＤ法による薄膜トランジスタ用の膜形成方
法を提供することを目的とする。Therefore, the present invention provides a thin film transistor (TF).
A film forming method for a thin film transistor by a plasma CVD method, which can improve the flatness of the interface between a silicon semiconductor film for T) and a gate insulating film in contact with the silicon semiconductor film, thereby increasing electron mobility between a source and a drain in a TFT. The purpose is to provide.
【０００５】[0005]
【課題を解決するための手段】本発明者は、前記連続放
電による原料ガスのプラズマ化によると、気相反応が律
促となり、反応種が基板から離れた位置から基板へ向け
降り注ぐことになるため、成膜表面粗度が大きくなって
しまうことに着目し、さらに研究を進め、パルス変調を
かけた高周波、換言すれば断続を繰り返す高周波を印加
すると、従来の気相反応だけでなく、基板表面及び（又
は）それに近い位置での反応（以下「表面反応」とい
う）も起こり、これによって、成膜表面粗度が小さくな
ることを見出し、本発明を完成した。The inventor of the present invention, when the raw material gas is turned into plasma by the continuous discharge, facilitates the gas phase reaction, and the reactive species flow down from the position away from the substrate toward the substrate. Therefore, paying attention to the fact that the film formation surface roughness becomes large, further research is carried out, and if a pulse-modulated high frequency, in other words, a high frequency that repeats intermittent is applied, not only the conventional gas phase reaction but also the substrate A reaction (hereinafter referred to as "surface reaction") on the surface and / or at a position close to the surface also occurs, and it was found that the film-forming surface roughness is reduced by this, and the present invention was completed.
【０００６】すなわち本発明は、薄膜トランジスタ用の
シリコン半導体膜及びゲート絶縁膜をプラズマＣＶＤ法
により形成し、前記それぞれの膜形成にあたり該膜形成
のための原料ガスのプラズマ化を、パルス変調をかけた
高周波電力の印加により行うことを特徴とする薄膜トラ
ンジスタ用の膜形成方法を提供するものである。前記パ
ルス変調の条件としては特に限定はないが、前記両膜界
面の平坦度を向上させる観点から、例えば４００〜１０
００Ｈｚの条件が考えられる。That is, according to the present invention, a silicon semiconductor film and a gate insulating film for a thin film transistor are formed by a plasma CVD method, and in forming each of the above films, plasma conversion of a raw material gas for forming the film is pulse-modulated. The present invention provides a method for forming a film for a thin film transistor, which is characterized in that high frequency power is applied. The condition of the pulse modulation is not particularly limited, but from the viewpoint of improving the flatness of the both film interfaces, for example, 400 to 10
A condition of 00 Hz can be considered.
【０００７】[0007]
【作用】本発明方法によると、薄膜トランジスタ用のシ
リコン半導体膜及びこれに積層されるゲート絶縁膜は、
プラズマＣＶＤ法により順次、且つ、各膜の原料ガスを
パルス変調をかけた高周波電力の印加でプラズマ化する
ことにより形成される。パルス変調をかけた高周波電力
の印加、換言すれば断続的な高周波電力の印加によりプ
ラズマの発生、停止が繰り返されるので、基板又はその
上に先に形成された膜から離れた位置で反応種が生成さ
れる気相反応が起こるほか、プラズマ停止時に原料ガス
が基板表面又はその上に先に形成された膜の表面及び
（又は）その近くまで達し、引き続きこれがプラズマ化
されることで反応種がそれら表面及び（又は）その近く
で生成される表面反応も進み、その結果、表面粗度の小
さい膜が形成されることになり、シリコン半導体膜とこ
れに接するゲート絶縁膜の界面の平坦度は良好となる。According to the method of the present invention, the silicon semiconductor film for the thin film transistor and the gate insulating film laminated thereon are
It is formed by plasma CVD method sequentially and plasma-converting the raw material gas of each film by applying high frequency electric power which is pulse-modulated. Since generation and stop of plasma are repeated by the application of pulse-modulated high-frequency power, in other words, intermittent application of high-frequency power, reactive species are generated at a position distant from the substrate or the film previously formed thereon. In addition to the generated gas-phase reaction, when the plasma is stopped, the source gas reaches the surface of the substrate or the surface of the film previously formed on the substrate and / or near the surface of the substrate gas. Surface reactions generated on those surfaces and / or in the vicinity thereof also proceed, and as a result, a film having low surface roughness is formed, and the flatness of the interface between the silicon semiconductor film and the gate insulating film in contact therewith is It will be good.
【０００８】[0008]
【実施例】以下、本発明の実施例を図面を参照して説明
する。図１は本発明方法の実施に使用するプラズマＣＶ
Ｄ装置の一例の概略断面を示している。図示の装置は、
真空チャンバ１、該チャンバに電磁弁２１を介して接続
した真空ポンプ２、チャンバ１内に設置した電極３、
４、チャンバ１に電磁弁６１を介して接続した成膜用ガ
ス源５を備えている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a plasma CV used for carrying out the method of the present invention.
The schematic cross section of an example of D apparatus is shown. The device shown is
A vacuum chamber 1, a vacuum pump 2 connected to the chamber via a solenoid valve 21, an electrode 3 installed in the chamber 1,
4. A film forming gas source 5 connected to the chamber 1 via an electromagnetic valve 61 is provided.
【０００９】電極３は接地電極であり、これには成膜温
度調節用のヒータ３１が付設されている。電極４は高周
波電極であり、それ自体既に知られているマッチングボ
ックス８を介して高周波電源７から高周波電圧が印加さ
れる。高周波電源７は、任意の高周波パルス変調が可能
な高周波信号発生器７１及び高周波増幅器（ＲＦパワー
アンプ）７２を有しており、所定周波数の高周波（図２
の（Ａ）図参照）に所望のパルス変調をかけた高周波電
力（図２の（Ｂ）図参照）を印加できるように構成して
ある。The electrode 3 is a ground electrode, and a heater 31 for adjusting the film forming temperature is attached to this. The electrode 4 is a high frequency electrode, and a high frequency voltage is applied from a high frequency power supply 7 through a matching box 8 which is already known per se. The high frequency power supply 7 has a high frequency signal generator 71 capable of performing arbitrary high frequency pulse modulation and a high frequency amplifier (RF power amplifier) 72, and has a high frequency of a predetermined frequency (see FIG. 2).
(See (A) of FIG. 2) can be applied with high-frequency power (see FIG. 2B) of desired pulse modulation.
【００１０】以上説明した装置によると、本発明方法は
次のように実施される。シリコン半導体膜及びゲート絶
縁膜のうち前者を先に形成する場合、後者を先に形成す
る場合のいずれも考えられる。いずれにしても、これら
膜は順次形成される。最初の膜を形成するにあたって
は、先ず、成膜すべき基板９を電極３上に設置する。し
かるのち、チャンバ１内を電磁弁２１の開成とポンプ２
の運転にて所定圧まで真空引きし、成膜用ガス源５から
最初の成膜用原料ガスをチャンバ内に導入し、且つ、チ
ャンバ内を所定成膜真空度に維持する。また、基板９を
ヒータ３１にて所定成膜温度に制御する。次いで、電源
７にてこのガスにパルス変調された高周波電圧を印加し
て該ガスをプラズマ化させ、基板９上に成膜させる。同
様にして、次の原料ガス源を準備し、そのガスを用いて
次の膜を形成する。かくしてシリコン半導体膜とゲート
絶縁膜の積層が形成される。According to the apparatus described above, the method of the present invention is carried out as follows. Either of the case of forming the former of the silicon semiconductor film and the gate insulating film first or the case of forming the latter first can be considered. In any case, these films are sequentially formed. In forming the first film, first, the substrate 9 to be formed is placed on the electrode 3. Then, in the chamber 1, the solenoid valve 21 is opened and the pump 2 is opened.
In the above operation, the vacuum is evacuated to a predetermined pressure, the first film forming source gas is introduced from the film forming gas source 5 into the chamber, and the inside of the chamber is maintained at the predetermined film forming vacuum degree. Further, the substrate 9 is controlled by the heater 31 to a predetermined film forming temperature. Next, a pulse-modulated high-frequency voltage is applied to this gas by the power source 7 to turn the gas into plasma, and a film is formed on the substrate 9. Similarly, the next source gas source is prepared, and the next film is formed using the gas. Thus, a stack of the silicon semiconductor film and the gate insulating film is formed.
【００１１】前記最初の成膜中、原料ガスには、パルス
変調された高周波電力が印加されるので、基板から離れ
た位置での気相反応だけでなく基板表面及び（又は）そ
れに近い位置での表面反応もあり、従って基板への成膜
は基板表面から離れた位置からの反応種の降り注ぎによ
るだけでなく、表面反応によるゆるやかな反応種の供給
によってもなされ、全体として成膜表面はそれだけ平坦
となる。また、この膜の上に形成される次の膜も先の平
坦な膜表面への気相反応による反応種の供給と表面反応
によるきめ細かい反応種の供給により形成されるので、
最初の膜とその上に形成される次の膜の界面の平坦度は
きわめて良好となる。Since pulse-modulated high-frequency power is applied to the source gas during the first film formation, not only the gas phase reaction at a position distant from the substrate but also at the substrate surface and / or a position close to it. Therefore, the film formation on the substrate is performed not only by pouring the reactive species from a position distant from the substrate surface but also by slowly supplying the reactive species by the surface reaction. It becomes flat. Further, since the next film formed on this film is also formed by supplying the reactive species by the gas phase reaction to the flat film surface and the fine reaction species by the surface reaction,
The flatness of the interface between the first film and the next film formed thereon becomes extremely good.
【００１２】よってシリコン半導体膜、ゲート絶縁膜の
いずれが先で、いずれがあとに形成される場合でも、両
者の界面平坦度はきわめて良好となり、両者はよく密着
する。従って、このような膜を用いた最終ＴＦＴトラン
ジスタでは、ソース・ドレイン間の電子移動度は従来に
比べ高いものとなる。以上説明した方法により、次の具
体的条件で１００ｍｍ角のガラス基板（コーニング７０
５９）上にアモルファスシリコン（ａ−Ｓｉ）半導体膜
とＳｉＮｘゲート絶縁膜の積層膜を形成したところ、後
に掲げる結果を得た。Therefore, no matter which of the silicon semiconductor film and the gate insulating film is formed first and which is formed later, the interface flatness between the two becomes extremely good and the two adhere well. Therefore, in the final TFT transistor using such a film, the electron mobility between the source and the drain is higher than in the conventional case. By the method described above, a 100 mm square glass substrate (Corning 70) was prepared under the following specific conditions.
59) When a laminated film of an amorphous silicon (a-Si) semiconductor film and a SiNx gate insulating film was formed on 59), the following results were obtained.
【００１３】成膜真空度：１００〜６００ｍＴｏｒｒ
（但し、ここでは５００ｍＴｏｒｒ） 高周波電源：１３．５６ＭＨｚ、１０００Ｗ パルス変調：５００Ｈｚ 電極３、４の面積：７００ｍｍ×７００ｍｍ ガラス基板温度：ａ−Ｓｉ膜形成時 ３００℃ ＳｉＮｘ膜形成時 ３５０℃ 成膜ガス：ａ−Ｓｉ膜については ＳｉＨ4 ５０ｃｃｍ Ｈ2 １５０ｃｃｍ ＳｉＮｘ膜については ＳｉＨ4 ５０ｃｃｍ ＮＨ3 １５０ｃｃｍ Ｎ2 ５０ｃｃｍ （結果）注：以下において（ ）内はパルス変調をか
けない従来方法の結果 上記結果から分かるように、本発明方法によると、従来
法に比べ、成膜の表面粗度は大きく低下し、ＴＦＴにお
ける電子移動度は約３倍に増加している。Deposition degree of film formation: 100 to 600 mTorr
(However, 500 mTorr here) High frequency power supply: 13.56 MHz, 1000 W Pulse modulation: 500 Hz Area of electrodes 3, 4: 700 mm x 700 mm Glass substrate temperature: a-Si film formation 300 ° C SiNx film formation 350 ° C deposition gas : For a-Si film SiH 4 50ccm H 2 150ccm For SiNx film SiH 4 50ccm NH 3 150ccm N 2 50ccm (Result) Note: The results in the conventional method without pulse modulation in () below. As can be seen from the above results, according to the method of the present invention, the surface roughness of the film formed is greatly reduced and the electron mobility in the TFT is increased by about 3 times as compared with the conventional method.
【００１４】[0014]
【発明の効果】以上説明したように本発明によると、薄
膜トランジスタ（ＴＦＴ）用のシリコン半導体膜及びこ
れに接するゲート絶縁膜の界面の平坦度を向上させ、そ
れによってＴＦＴにおけるソース・ドレイン間の電子移
動度を大きくさせ得るプラズマＣＶＤ法による薄膜トラ
ンジスタ用の膜形成方法を提供することができる。As described above, according to the present invention, the flatness of the interface between the silicon semiconductor film for a thin film transistor (TFT) and the gate insulating film in contact therewith is improved, whereby electrons between the source and drain in the TFT are improved. A film forming method for a thin film transistor by a plasma CVD method capable of increasing the mobility can be provided.
【図１】本発明方法の実施に使用するプラズマＣＶＤ装
置の一例の概略構成図である。FIG. 1 is a schematic configuration diagram of an example of a plasma CVD apparatus used for carrying out the method of the present invention.
【図２】図（Ａ）はパルス変調をかけない従来高周波
の、図（Ｂ）はパルス変調をかけた本発明に係る高周波
の概略を示す図である。FIG. 2A is a diagram showing an outline of a conventional high frequency without pulse modulation, and FIG. 2B is a diagram showing an outline of a high frequency according to the present invention with pulse modulation.
１ 真空チャンバ ２ 真空ポンプ ２１ 電磁弁 ３ 接地電極 ３１ ヒータ ４ 高周波電極 ５ 成膜用原料ガス源 ６１ 電磁弁 ７ 高周波電源 ７１ 高周波信号発生器 ７２ ＲＦパワーアンプ ８ マッチングボックス 1 Vacuum Chamber 2 Vacuum Pump 21 Electromagnetic Valve 3 Grounding Electrode 31 Heater 4 High Frequency Electrode 5 Source Gas Source for Film Formation 61 Electromagnetic Valve 7 High Frequency Power Source 71 High Frequency Signal Generator 72 RF Power Amplifier 8 Matching Box
Claims (1)
及びゲート絶縁膜をプラズマＣＶＤ法により形成し、前
記それぞれの膜形成にあたり該膜形成のための原料ガス
のプラズマ化を、パルス変調をかけた高周波電力の印加
により行うことを特徴とする薄膜トランジスタ用の膜形
成方法。1. A silicon semiconductor film and a gate insulating film for a thin film transistor are formed by a plasma CVD method, and in forming each of the films, a raw material gas for forming the film is converted into plasma and pulse-modulated high frequency power is applied. A method for forming a film for a thin film transistor, which is performed by applying a voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4019195A JP2581371B2 (en) | 1992-02-04 | 1992-02-04 | Film forming method for thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4019195A JP2581371B2 (en) | 1992-02-04 | 1992-02-04 | Film forming method for thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05218003A true JPH05218003A (en) | 1993-08-27 |
| JP2581371B2 JP2581371B2 (en) | 1997-02-12 |
Family
ID=11992569
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4019195A Expired - Fee Related JP2581371B2 (en) | 1992-02-04 | 1992-02-04 | Film forming method for thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2581371B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8343857B2 (en) | 2010-04-27 | 2013-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of microcrystalline semiconductor film and manufacturing method of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02129377A (en) * | 1988-11-08 | 1990-05-17 | Nec Corp | Plasma vapor growth method |
-
1992
- 1992-02-04 JP JP4019195A patent/JP2581371B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02129377A (en) * | 1988-11-08 | 1990-05-17 | Nec Corp | Plasma vapor growth method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8343857B2 (en) | 2010-04-27 | 2013-01-01 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of microcrystalline semiconductor film and manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2581371B2 (en) | 1997-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7754294B2 (en) | Method of improving the uniformity of PECVD-deposited thin films | |
| JP4018625B2 (en) | Multi-stage CVD method for thin film transistors | |
| US6037017A (en) | Method for formation of multilayer film | |
| WO2000044033A1 (en) | Method and apparatus for film deposition | |
| US7521341B2 (en) | Method of direct deposition of polycrystalline silicon | |
| JP2008124111A (en) | Method for forming silicon thin film by plasma cvd method | |
| JP2002060945A (en) | Deposition of teos oxide using pulse rf plasma | |
| TW307027B (en) | Process for reducing circuit damage during pecvd in single wafer pecvd system | |
| US20100062585A1 (en) | Method for forming silicon thin film | |
| JPH05218003A (en) | Forming method for film for thin film transistor | |
| JP3388651B2 (en) | Method of forming insulating film | |
| JPH10265212A (en) | Production of microcrystal and polycrystal silicon thin films | |
| JPH07142400A (en) | Plasma treating method and its apparatus | |
| JPH0142125B2 (en) | ||
| JPH05217908A (en) | Forming method for film transistor | |
| JPH02166283A (en) | Formation of insulating film | |
| JPH09263948A (en) | Formation of thin film by using plasma, thin film producing apparatus, etching method and etching device | |
| JPS63233549A (en) | Thin film formation | |
| US12021152B2 (en) | Process to reduce plasma induced damage | |
| JP2795781B2 (en) | Method of forming impurity layer | |
| JP3615919B2 (en) | Plasma CVD equipment | |
| JP3380922B2 (en) | Method of forming silicon oxide film | |
| JPH05218005A (en) | Forming method for insulating film of thin film | |
| JPH08979B2 (en) | Plasma CVD method and apparatus | |
| JPS62238370A (en) | Device for cvd by plasma |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19961001 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081121 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081121 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091121 Year of fee payment: 13 |
|
| LAPS | Cancellation because of no payment of annual fees |