JPH05110083A - Field effect transistor - Google Patents

Abstract

PURPOSE:To restrain a drain current from decreasing in quantity when a FET is micronized. CONSTITUTION:Grooves 39 are provided onto an element forming region 42 of a FET 28 extending in parallel with the lengthwise direction of a gate, and a gate oxide film 32 and a gate electrode 34 are successively provided onto the element forming region 42 where the grooves 39 are provided. A source region 36 and a drain region 38 are arranged so as to sandwich the gate electrode 34 between them, and the element forming region 42 is provided. The source region 36 and the drain region 38 are of impurity-containing regions which are formed by adding impurities to the element forming region 42 using the gate electrode 34 as a mask. The surface part of the element forming region 42 where grooves are provided becomes longer in a direction which crosses a direction in which a drain current flows than a case where grooves are not provided, and therefore an effective gate length is enhanced.

Description

Detailed Description of the Invention

[0001]

This invention relates to the structure of field effect transistors.

[0002]

2. Description of the Related Art Currently, VLSI (Very Large)
As a basic element that constitutes the Scale Integration, a field effect transistor (Metal Oxide Semiconductor) having a MOS structure is used.
r Field Ef-fect Transisto
r: referred to as MOSFET) is widely used. Hereinafter, a structure of a conventional MOSFET will be schematically described with reference to the drawings. For details of the MOSFET manufacturing method and the element structure, see, for example, Document 1: Ultra-high-speed MOS device, Baifukan, February 10, 1986, p117-1.
See 25.

FIGS. 10A and 10B show a conventional MOSF.
FIG. 10A is a cross-sectional view and a plan view schematically showing the configuration of a main part of the ET, and FIG. 10A shows a cross section taken along line AA of FIG. 10B. In the figure, the MOS included in the VLSI
Focusing on the FET1 element, the configuration of the main part thereof is shown.

As shown in FIGS. 10A and 10B, F
The ET 10 includes a substrate 12, a gate oxide film 16, a gate electrode 18, a source region 20 and a drain region 22. A field oxide film 24 is provided on the substrate 12 for electrically separating the FET 10 included in the VLSI and the other elements, and a window 26 exposing the element formation region 14 of the substrate 12 is formed in the field oxide film 24. Set up. And window 2
A gate oxide film 16 and a gate electrode 18 are sequentially provided on the element formation region 14 exposed through the layer 4. Further, the source region 20 and the drain region 22 are provided in the element formation region 14 so as to be adjacent to one and the other side portions of the gate electrode 18. In the figure, the source region 20 and the drain region 22 are indicated by dots.

[0005]

However, the above-mentioned conventional MOSFET has some problems in increasing the degree of integration of LSI. Hereinafter, this point will be described.

In order to increase the degree of integration of the LSI, it is sufficient to miniaturize the MOSFET which is its constituent element and reduce its occupied area.
It is necessary to reduce the gate width W and the gate length L (see FIG. 10) of the FET. The reduction of the gate length L brings about an advantage that the electric field strength between the source and the drain is strengthened so that the drain current is increased and the operation speed is improved. However, since the drain current increases / decreases in proportion to the gate width W,
The reduction of the gate width W brings about the reduction of the drain current and therefore cancels the increase of the drain current due to the reduction of the gate length L. Therefore, it was not always possible to effectively increase the drain current by reducing the gate length L.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a field effect transistor having a structure capable of preventing a decrease in drain current due to miniaturization.

[0008]

In order to achieve this object, a field effect transistor of the present invention comprises an underlayer made of a semiconductor material, and a gate oxide film and a gate electrode sequentially provided on an element formation region of the underlayer. In a field effect transistor including a source region and a drain region provided in the element formation region so as to sandwich the gate electrode, a direction connecting the source region and the drain region to at least the region immediately below the gate electrode in the element formation region. It is characterized in that a groove is provided by extending it.

[0009]

According to such a structure, the groove extends in the direction connecting the source region and the drain region. Therefore, in the portion of the element forming region where the groove is provided, the element forming region in the direction intersecting with the drain current flowing direction is formed. The length P of the surface layer portion is longer than that in the case where no groove is provided, and thus the substantial gate width is increased. Moreover, even if the area of the element formation region in the plan view is kept constant, the length P increases as the number of grooves provided and / or the depth increases. The substantial gate width can be increased without increasing the area of the element formation region. In other words, when the field-effect transistor is miniaturized, even if the gate width is reduced in plan view, the substantial reduction in the drain width can be suppressed by taking the substantial gate width.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the drawings are merely schematic representations so that the present invention can be understood, and therefore the present invention is not limited to the illustrated examples.

FIG. 1 is a cutaway perspective view schematically showing the structure of a main part of an embodiment of the present invention. The FET 28 of this embodiment is a MOSFET mounted on an LSI, and FIG. 1 shows the main configuration thereof.

The FET 28 of this embodiment has a base 30, a gate oxide film 32 and a gate electrode 34, and a source region 36.
And a drain region 38 and a groove 39.

The base 30 is a base made of a semiconductor material of the first conductivity type, for example, a p-type Si substrate.
A field oxide film 40 is provided to separate the FET 28 mounted on the LSI from other electric circuit elements.
The field oxide film 40 has a window exposing the element formation region 42 of the base 30, and the gate oxide film 32 and the gate electrode 34 are sequentially provided on the element formation region 42. Then, the source region 36 and the drain region 38 are arranged so as to sandwich the gate electrode 34, and are provided in the element formation region 42. The source region 36 and the drain region 38 are regions formed by adding an impurity of a second conductivity type opposite to the first conductivity type, for example, an n-type impurity, to the element formation region 42.

Then, a groove 39 is provided in at least a region immediately below the gate electrode 34 in the element forming region 42 so as to extend in a direction connecting the source region 36 and the drain region 38. In this embodiment, a plurality of trenches 39 extend parallel to the length direction of the gate electrode 34 and are provided not only directly under the gate electrode 34 but also in the source region 36 and the drain region 38. By providing the groove 39 in the source region 36 and the drain region 38 as well, when the source region 36 and the drain region 38 are connected to the corresponding electrodes, respectively, the contact area between these regions and the electrode can be made large, and therefore these regions can be made larger. The contact resistance between the region and the electrode can be reduced.

Next, a method of manufacturing the FET 28 of this embodiment will be described with an example. 2 to 9 are explanatory views of the manufacturing process of this embodiment. 3 (A)-(B) and FIG.
4A to 9A are schematic cross-sectional views taken along the gate electrode width direction of the element formation region in the region corresponding to immediately below the gate electrode and its vicinity in the course of manufacturing the FET. Sectional views shown in FIGS. 2 and 4 to 9
Each of (B) is a plan view schematically showing a state of an element formation region and a portion in the vicinity thereof during manufacturing of the FET. Moreover, FIGS. 2 and 4A to 9B are a sectional view and a plan view at the same process stage.

In manufacturing the FET 28 of this embodiment, a base of the first conductivity type such as a p-type Si substrate is prepared as the base 30. Next, as shown in FIGS. 2A and 2B, a pad oxide film 44 is formed on the base 30. The pad oxide film 44 is, for example, SiO formed by a thermal oxidation method.
It is a _two- layered film and is formed for the purpose of stress relaxation during formation of the field oxide film 40. Then, on the pad oxide film 44,
A mask forming film 46 is laminated. The mask forming film 46 is made of a material that is not easily oxidized, and is formed by, for example, CVD (Chemi).
It is a Si ₃ N ₄ film formed by a cal vapor deposition method. Next, the mask forming film 4
A resist pattern 48 used for patterning this is formed on the substrate 6. The resist pattern 48 is formed in a region corresponding to the element formation region 42, preferably slightly wider than the element formation region 42.

Next, as shown in FIG. 3A, the mask forming film 46 is patterned using the resist pattern 48 as a mask to obtain a mask 50 made of the patterned mask forming film 46. At this time, only the mask forming film 46 is selectively patterned without patterning the pad oxide film 44. Then, impurities for channel stopper, for example, B ions are selectively added to the base 30 in the peripheral portion of the element forming region 42. In the figure, the region to which this ion is added is schematically indicated by a cross mark.

Next, as shown in FIG. 3B, the resist pattern 48 is removed, and then the underlayer 30 is selectively oxidized by using the mask 50 to form the field oxide film 4 on the underlayer 30.
Form 0. Since the mask 50 is hard to be oxidized, the base 3
The field oxide film 40 is selectively formed on the region not covered with the mask 50 of 0.

Next, as shown in FIGS. 4 (A) and 4 (B),
The mask 50 and the pad oxide film 44 are removed, and a window 52 is formed in the field oxide film 40. The base 30 in the element formation region 42 is exposed through the window 52.

Next, as shown in FIGS. 5 (A) and 5 (B),
A mask 54 for forming a groove is formed on the element forming region 42 exposed through the window 52. The mask 54 has a plurality of stripe-shaped windows 56 extending in the gate length direction. The groove forming portion of the element forming region 42 is exposed through the window 56 and the remaining portion is covered with the mask 54. After that, for example, by a conventionally known dry etching method, the groove forming portion of the element forming region 42 is selectively removed by etching, and the groove 39 is formed in the element forming region 42.
To form. After forming the groove 39, the mask 54 is removed.

In the illustrated example, the number of the grooves 39 provided is three and the length is 1/4 of the gate width in a plan view, but the number of the grooves 39 and the depth are determined according to the design. It can be changed arbitrarily. The effective gate width can be increased or decreased by increasing or decreasing the depth and / or number of the grooves 39. In order to increase the effective gate width, it suffices to provide the groove 39 in at least the region (channel region) directly under the gate electrode of the element formation region 42, but in the illustrated example, the groove 39 is formed as the source of the element formation region 42. It is provided so as to extend from the region to the drain region. By providing the groove 39 in the source region and / or the drain region, the contact resistance between the source region and / or the drain region and the corresponding electrode can be reduced.

Next, as shown in FIGS. 6A and 6B,
An oxide film 58 for forming a gate oxide film is formed in the element forming region 42 having the groove 39. The oxide film 58 is, for example, a SiO ₂ film having a film thickness of about 3 to ₂₀ nm formed by heating the element formation region 42 to about 900 ° C. and thermally oxidizing it. Next, an impurity for controlling the threshold voltage is added to the channel portion of the element forming region 42 by, for example, an ion implantation method. At this time, since impurities are added not only to the bottom portion of the groove 39 but also to the side wall portion, not only from the direction perpendicular to the main plane of the base 30 (in this example, the substrate surface of the Si substrate) but also to the main plane. Groove 39 from a plurality of diagonal directions
Impurities are preferably incident on the side wall portion. In the figure, the region into which this impurity has been implanted is schematically indicated by a white circle.

Next, as shown in FIGS. 7A and 7B,
A film for forming a gate electrode, for example, a polysilicon film 60 is laminated on the oxide film 58, and then a resist mask 62 is formed on the polysilicon film 60. The mask 62 covers the gate electrode formation portion of the polysilicon film 60 and exposes the remaining portion.

Next, as shown in FIGS. 8A and 8B,
The gate electrode forming portion of the polysilicon film 60 is left and the remaining portion is removed by etching to obtain the gate electrode 34 made of the remaining polysilicon film 60 and expose the field oxide film 40. Next, the portion of the oxide film 58 immediately below the gate electrode is left and the remaining portion is removed by etching to obtain the gate oxide film 32 of the remaining oxide film 58 and expose the trenches 39 of the source and drain regions of the element formation region 42. Let Then, the mask 62 is removed.

Next, as shown in FIGS. 9A and 9B,
The source region 3 of the element formation region 42 exposed through the window 52
6 and the drain region 38 are selectively doped with impurities such as As ions to complete the basic structure of the FET 28 as shown in FIG. When adding impurities, for example, using the gate electrode 34 and the field oxide film 40 as a mask, the impurities are added by the ion implantation method. Moreover, since impurities are added not only to the bottom of the groove 39 but also to the side wall, the base 3
Impurities are preferably incident on the side wall portion of the groove 39 not only from a direction perpendicular to the main plane of 0 (the substrate surface of the Si substrate in this example) but also from a plurality of directions oblique to the main plane. In FIG. 9B, the source region 36 and the drain region 38 to which impurities have been added are indicated by dots.

Next, though not shown, according to a conventionally known method,
Gate electrode 34, source region 36, and drain region 38
An intermediate insulating film is laminated thereon, and then contact holes exposing the source region 36 and the drain region 38 are formed in the intermediate insulating film. Next, a wiring electrode connected to the source region 36 and the drain region 38 via the contact hole is formed on the intermediate insulating film, and the wiring of the FET 28 is completed.

In this example, the groove 39 is extended in a direction parallel to the direction in which the gate length L (see FIG. 9B) is measured,
Since the number of grooves 39 provided is three and the depth thereof is ¼ of the gate width W1 (see FIG. 9B) when viewed in plan, the effective gate width W2 of the FET 28 is W2. Is W2 = W
1+ (W1 / 4) · 6 = 2.5 · W1. Therefore, even if the gate width W1 when viewed two-dimensionally is the same as the conventional size, the effective gate width W2 in this embodiment is 2.5 times the gate width W1 when viewed two-dimensionally. Therefore, the drain current amount can be increased to 2.5 times that of the conventional case, resulting in FE
The operating speed of T can be made faster than before. From a different point of view, when the drain current amount is the same as the conventional one and compared, the gate width W in the plan view in this embodiment is W.
1 can be reduced to 1 / 2.5 times that of the conventional one, which greatly contributes to LSI integration.

In addition, CMOS (Complementar)
In an LSI having a (yMOS) structure, it is important to individually optimize the drain current amount of each of the n-channel and p-channel MOSFETs so that the operating speed is maximized. In this embodiment, the present invention is applied to n channel M
Although the example applied to the OSFET has been described, if the present invention is applied to both the n-channel and p-channel MOSFETs included in the CMOS LSI, the operation can be performed by arbitrarily and appropriately designing the groove depth and the number of grooves. It becomes easy to optimize the drain current amount of each of the n-channel and p-channel MOSFETs so as to maximize the speed.

The present invention is not limited to the above-mentioned embodiment, and therefore, the shape of each component, the arrangement position,
The forming material, the forming method, the numerical conditions, the extending direction, the numerical conditions and the like can be arbitrarily changed.

[0030]

As is apparent from the above description, according to the field-effect transistor of the present invention, the groove extends in the direction connecting the source region and the drain region, so that the portion where the groove is provided in the element forming region is provided. Then, the length P of the surface layer portion of the element forming region in the direction intersecting with the direction in which the drain current flows becomes longer than that in the case where no groove is provided, and therefore the effective gate width increases. Therefore, according to the present invention, even if the gate width when viewed two-dimensionally is the same size as the conventional one,
Since the effective gate width can be made larger than the gate width when viewed two-dimensionally, the drain current amount can be increased as compared with the conventional case, and the operation speed can be made faster than the conventional case.

Further, even if the area of the element forming region in a plan view is kept constant, the length P increases as the number of grooves provided and / or the depth increases. In this case, the effective gate width can be increased without increasing the area of the element formation region. Therefore, according to the present invention, when the drain current amount is the same as the conventional one,
Since the gate width when viewed two-dimensionally can be reduced, the device structure can be made finer than before.

[Brief description of drawings]

FIG. 1 is a cutaway perspective view of a main part schematically showing the basic structure of an embodiment of the present invention.

FIGS. 2A and 2B are a cross-sectional view and a plan view of a main part, which schematically show a state during manufacturing in the same process step.

FIG. 3A and FIG. 3B are cross-sectional views of relevant parts schematically showing a state in the process of manufacturing in different process steps.

4A and 4B are a cross-sectional view and a plan view of a main part schematically showing a state in the process of manufacturing in the same process step.

5 (A) and 5 (B) are a cross-sectional view and a plan view of a main part schematically showing a state in the process of manufacturing in the same process step.

6 (A) and 6 (B) are a cross-sectional view and a plan view of a main part, which schematically show a state in the middle of manufacturing in the same process step.

7 (A) and 7 (B) are a cross-sectional view and a plan view of a main part, which schematically show a state in the process of manufacturing in the same process step.

8A and 8B are a cross-sectional view and a plan view of a main part, which schematically show a state in the process of manufacturing in the same process step.

9A and 9B are a main-portion cross-sectional view and a main-portion plan view that schematically show the manufacturing process in the same process step.

10A and 10B are a main-portion cross-sectional view and a main-portion plan view schematically showing the configuration of a conventional MOSFET.

[Explanation of symbols]

 28: FET 30: Underlayer 32: Gate oxide film 34: Gate electrode 36: Source region 38: Drain region 39: Groove 42: Element formation region

Claims (1)

[Claims] 1. An underlayer made of a semiconductor material, a gate oxide film and a gate electrode sequentially provided on an element formation region of the underlayer, and a source provided in the element formation region so as to sandwich the gate electrode. A field effect transistor comprising a region and a drain region, characterized in that a groove is provided in at least a region immediately below the gate electrode of the element formation region so as to extend in a direction connecting the source region and the drain region. Transistor.