JPH0478098A - Operating method for semiconductor memory device - Google Patents

Abstract

PURPOSE:To make a refresh characteristic satisfactory and to reduce the probability of causing a malfunction by turning a switching transistor to be in a nonconductive condition in a state in which the potentials of a bit line and a plate line are turned to the substrate potential and the equipotential of a semiconductor substrate, respectively. CONSTITUTION:After the performance of access to a memory cell 11 is operated, the driving signal transmitted from a word line 4 is stopped, and the switching transistor of the memory cell 11, for example, an MOS type transistor 17, is turned to be in the nonconductive condition. At that time, the potentials of a bit line 16 and a plate line 13 are turned to the substrate potential and the equipotential of the semiconductor substrate, respectively. Therefore, the potential of a storage node between a ferroelectrics condenser 18 and the switching transistor 17 is held to be the substrate potential and the equipotential of the semiconductor substrate even in the holding state of information stored in the memory cell 11. Thus, the refresh characteristic can be satisfactory and the probability of causing the malfunction can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to a method of operating a nonvolatile semiconductor memory device.

(Prior Art) Dynamic-Random Access Memory (DRAM)
) As the capacity and integration of semiconductor memory devices, such as those in For this reason, for example, in 4M bit DRAs, three-dimensional structures such as stacks and trenches are being used as capacitors in memory cells, but further integration is expected in the future. It is expected that the structure of memory cells will become increasingly complex.

For this reason, we are considering simplifying the structure of capacitors by using ferroelectrics with a large dielectric constant as dielectrics instead of silicon oxides and nitrides, which are conventionally used as dielectric materials. has been done. For example, the dielectric constant of lead zirconate titanate (PZT), which is a typical ferroelectric material, is 1000 or more, and in principle, a large amount of charge can be stored in a small area even with a Brenna structure. Therefore, it is expected that a semiconductor memory device using a ferroelectric material as a capacitor material will have a simple structure and be highly integrated. A ferroelectric capacitor with a planar structure is
It is sufficient to sandwich the upper and lower surfaces of a ferroelectric film deposited by sputtering, CVD, etc. with electrodes made of polysilicon, metal, or the like, and it can be formed through a relatively simple process.

Further, the production of nonvolatile RAM using ferroelectric capacitors is also being considered in Japanese Patent Application Laid-Open No. 63-201998. This takes advantage of the fact that ferroelectric materials have a hysteresis characteristic between the electric field and polarization, and in ferroelectric capacitors, even when the voltage is returned to zero, residual polarization is maintained depending on the direction of the applied voltage. .

Therefore, the direction of the charge remaining on the electrode is, for example, "0".
1'', digital information can be stored in the ferroelectric capacitor.

In a ferroelectric capacitor, there is a relationship between the applied voltage (2) and the accumulated charge Q as shown in FIG. 1st
3(a) is a Q-V curve observed below the Curie temperature (ferroelectric phase), and FIG. 3(b) is a Q-V curve observed above the Curie temperature (paraelectric phase). One such ferroelectric capacitor and MO6
Figure *14 shows a general example of a memory cell circuit formed by combining one type transistor. In addition, a partial circuit diagram of a semiconductor memory device in which one bit of information is written to and read from one memory cell is shown in the first part.
It is shown in Figure 5. In the memory cell shown in FIG.
A word line ML (
4) are coupled, the source and drain of the MOS transistor (17) are respectively coupled to the bit line BL (16) and one electrode of the ferroelectric capacitor (18), and the source and drain of the MOS transistor (17) are coupled to the bit line BL (16) and one electrode of the ferroelectric capacitor (18). The electrode is connected to the plate line PL (
13). Also, plate line PL (13)
and word line ML (4) are both nihit line BL (113)
It is formed perpendicular to. Furthermore, in the semiconductor memory device shown in FIG. 15, two bit lines BL (1) are connected to one sense amplifier S/A (20).
B-1) and BL (1B-2) form a bit line pair, with sense amplifier S/A (20) in between.
(20) are formed on both sides.

A memory cell array is constructed by arranging a plurality of columns having the same structure in the Y direction, with the structure shown in FIG. 15 as one column. 16 shows a circuit diagram of the memory cell array according to FIG. 16. FIG. That is, the word line WL (4) is coupled to the gate electrodes of MOS transistors 17) of a plurality of memory cells in the same row arranged in the Y direction, and further coupled to a word line decoder (19). Also, plate line PL (13
) is also coupled to the electrode of the ferroelectric capacitor (18) of the memory cell in the same row, and further coupled to the plate line decoder (28).

In semiconductor memory devices using ferroelectric capacitors, a memory cell can be constructed from one MOS transistor and one ferroelectric capacitor, making it suitable for increasing the capacity of semiconductor memory devices. . Also, the method of operation is
It has many things in common with DRAM, such as a flip-flop type sense amplifier amplifying the potential of the bit line and rewriting the memory cell's ferroelectric capacitor.
It is characterized by the fact that many of the circuit technologies of

Moreover, its superior features over DRAM include that it does not require a refresh operation in principle and is nonvolatile.

However, even in semiconductor memory devices using such ferroelectric capacitors, although the ferroelectric operation is not necessary in principle as described above, there are problems with refresh characteristics as detailed below, and in reality, DRAM A refresh operation similar to that of a DRAM is required, although the frequency may be different.

In other words, in the case of a DRAM, the problem is whether the charge accumulated in the capacitor of the memory cell is a leakage current that decreases over time. The path of leakage current is storage
The main routes include P-N junction leakage current between the node and semiconductor substrate, subthreaded current of access transistor, leakage current of parasitic field transistor, leakage current of capacitor dielectric film, etc. is the PN junction or leakage current. This is due to the P-
This is because carriers of electrons and holes are thermally generated within the depletion layer of the N junction, and the carriers are moved by the electric field applied to the depletion layer. Dl? In AM, the storage note is given different potentials, such as 5■ and 0■, depending on the amount of charge stored in the capacitor of the memory cell. Because leakage current causes the temperature to relax to a thermal equilibrium state over time, DRAM requires a refresh operation.

On the other hand, in a semiconductor 5-chip storage device using a ferroelectric capacitor, if the potentials at both ends of the ferroelectric capacitor can be kept at the same potential, the information stored in the memory cell will be retained and no refresh operation will be necessary. Become. However, similar to DRAM, when used by applying an iasmi potential to the semiconductor substrate for the purpose of reducing bit line capacitance, etc., and applying a reverse bias to the depletion layer between the source and train and the semiconductor substrate, , the potential of the storage note of the memory cell approaches the substrate potential over time, creating a potential difference across the ferroelectric capacitor. This is because electrons and holes thermally generated in the depletion layer receive electrostatic force from the electric field of the depletion layer, and are attracted to the source or drain and the substrate, respectively.

Therefore, even in semiconductor memory devices using such ferroelectric capacitors, DRAMs require refresh operations, although they may not be as frequent. Furthermore, in such semiconductor memory devices, like DRAMs, software There is a problem with malfunction caused by an error. In other words, a soft error is one in which the stored contents of a memory cell are destroyed by α particles emitted from a radioactive element such as uranium or thorium contained in trace amounts in a package or the like. α particles penetrate approximately several tens of microns into the semiconductor substrate,
Electron-hole pairs of about 200 fC are generated along the trajectory. The charges generated in this way inevitably flow to the storage node or bit line of the memory cell by diffusion or movement, thereby destroying the stored information.

In this way, soft errors destroy information stored in memory cells, causing malfunctions, and in turn significantly lowering the reliability of semiconductor memory devices. However, the conventional D
I? In AM, there is no way to completely eliminate such soft errors, and even in semiconductor memory devices using ferroelectric capacitors as described above, soft errors occur.
No method has hitherto been found to eliminate the error.

(Problem to be solved by the invention) -L As mentioned above, semiconductor memory devices using ferroelectric capacitors have until now required refresh operations like DRAMs, and malfunctions may occur due to soft errors. There was a problem. Furthermore, in such a semiconductor memory device, the refresh characteristics and reliability tend to deteriorate as the amount of charge accumulated in the ferroelectric capacitor decreases.In other words, the smaller the capacitance of the ferroelectric capacitor, the lower the Since such problems are serious, they have been an impediment to higher integration of semiconductor memory devices.

The purpose of the fraudulent invention is to solve these problems and provide a method for operating a semiconductor memory device that has good refresh characteristics, has a low probability of malfunctions, has low power consumption, and is highly reliable.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides memory cells formed on a semiconductor substrate, each including a ferroelectric capacitor and a switching transistor, which are arranged in a matrix, and one of the ferroelectric capacitors. the electrode is the source of the switching transistor,
In the method of operating a semiconductor memory device, the word is connected to a bit line via a drain, the other electrode of the ferroelectric capacitor is connected to a plate line, and the gate electrode of the switching transistor is connected to a word line. After transmitting a drive signal from the line to make the switching transistor conductive and accessing the memory cell by transmitting a drive signal from the plate line, the potentials of the bit line and plate line are set to the substrate potential of the semiconductor substrate. In this method of operating a semiconductor memory device, a drive signal transmitted from the word line is stopped to make the switching transistor non-conductive in a state where the potential is equal to that of the word line. That is, in the operating method of the semiconductor memory device of the present invention, after accessing the memory cell, when the drive signal transmitted from the word line is stopped and the switching transistor of the memory cell is rendered non-conductive, the bit line and It is characterized in that the potential of the plate line is equal to the substrate potential of the semiconductor substrate.

Furthermore, the present invention is a method of operating a semiconductor memory device in which the precharge potential of a bit line is made equal to the substrate potential of a semiconductor substrate. Further, in the present invention, the substrate potential is applied to the bit line from outside the semiconductor element.

By the power supply voltage generation means that supplies the power supply voltage to the plate line etc.
It is preferable to set it to cc5V or the like. In this case, even when precharging the bit line, if a voltage is supplied to the bit line precharge circuit using the power supply voltage generating means, the precharge potential of the bit line can be made equal to the substrate potential of the semiconductor substrate. You can make it happen.

In addition, in the present invention, in order to prevent the charge accumulated in the ferroelectric capacitor of the memory cell from being reversed and the information stored in the memory cell being lost other than during access, the switching transistor of the memory cell is set to a non-conducting state. It is desirable to maintain the potential of the plate line at the same potential as the substrate potential of the semiconductor substrate even after the semiconductor substrate is exposed.

Next, FIG. 1 shows a circuit diagram of an example of a memory cell array in a semiconductor memory device according to the present invention.

Further, FIG. 2 shows a circuit diagram of another example of such a memory cell array. As shown in FIGS. 1 and 2, the memory cell (11) of the semiconductor memory device of the present invention is composed of a ferroelectric capacitor (18) and a MOS transistor (17) as a switching transistor. One electrode of the dielectric capacitor (18) is the source of the MOS transistor (17).

bit line BL (1B-1) or BL via the drain
(1B-2) is connected to the ferroelectric capacitor (18)
The other electrode of M is connected to the plate line PL (13),
The gate electrode of the OS type transistor (17) is connected to the word line W.
Connected to L(4). Furthermore, in the memory cell array shown in FIG. 1, the memory cell (11) has one MOS transistor (17) and one ferroelectric capacitor (18
), and in the memory cell array shown in FIG. 2, the memory cell (11) consists of two MOS transistors (17-1, 17-2) and two ferroelectric capacitors (18- 1, 18-2). In the memory cell (11) as shown in FIG. 2, the two ferroelectric capacitors (18-1, 18-2) always maintain complementary polarization states. These memory cells (11) are arranged in a matrix, and are connected to the word line WL (4) or the bit lines (1B-1) and BL (lf3-1).
2), and the plate line PL (13) is perpendicular to the bit line BL.
(1B-1) and BL (1B-2) are formed in parallel.

In other words, memory cells such as those shown in FIGS. 1 and 2
In the array, word line WL (4) and plate line PL (13
) are orthogonal. Further, in the present invention, the configuration of the memory cell array is not particularly limited, and the 16th
Word line WL (4) and plate line PL as shown in the figure
A conventional memory cell array configuration in which (13) are formed in parallel is also acceptable. In addition, in the memory cell array shown in FIGS. 1 and 2, two bit lines BL (1, 8-1) and BL (1B-2) constituting a bit line pair or a plate line PL (13) These bit line pairs share the same sense amplifier. This is DR
The layout is similar to the folded bit line method in AM, or the open bit line method in DRAyI is used in the present invention.
Similar to the bit line method, a pair of bit lines sharing one sense amplifier can be formed on both sides of the sense amplifier. However, as described above, a bit line pair is preferably formed on both sides of a plate line, as in the folded bit line system.

Further, in the memory cell arrays shown in FIGS. 1 and 2, MOS transistors are used as switching transistors, but the present invention is not limited to this.
It is also possible to use an MIS type transistor or the like in which a nitride film is formed on the gate electrode portion.

(Function) In the present invention, after accessing a memory cell, a bit is used when the drive signal transmitted from the word line is stopped and the switching transistor of the memory cell, for example, an MO8 type transistor, is rendered non-conductive. The potentials of the line and plate line are equal to the substrate potential of the semiconductor substrate. Therefore, even in the retention state of information stored in memory cells,
The potential of the storage note between the ferroelectric capacitor and the switching transistor is maintained at the same potential as the substrate potential of the semiconductor substrate. In other words, since no electric field is applied to the depletion layer of the P'-N junction between the storage node and the semiconductor substrate, the generation of PN junction leakage current, which is the main cause of deterioration of the refresh characteristics of semiconductor storage devices, is suppressed. Ru. Note that in the semiconductor memory device according to the present invention, the switching transistor of the memory cell is CM
In the case of an OS type transistor, P
In order to suppress the occurrence of -N junction leakage current, is it necessary to make the potential of the bit line and plate line equal to the potential of the well in the semiconductor substrate? This includes the potential of the well in such cases.

Further, according to the present invention, the occurrence of soft errors can be suppressed, and the possibility of malfunction occurring in a semiconductor memory device can be significantly reduced. In other words, soft errors are caused by charges generated in the semiconductor substrate due to the entry of α particles flowing into the storage node or bit line, as described above. In the present invention, since the storage node and the semiconductor substrate are held at the same potential, the number of charges flowing into the storage node is reduced, and the occurrence of soft errors can be suppressed. Furthermore, in the present invention, by making the precharge potential of the bit line equal to the substrate potential of the semiconductor substrate, the number of charges flowing into the bit line when the bit line is placed in a floating state is reduced.・The occurrence of errors is further suppressed. Note that, as described above, in the case of a switching transistor of a memory cell or a CMOS type transistor, the substrate potential includes the potential of the well, and the same applies to the following.

Further, in the present invention, by applying a substrate potential to the semiconductor substrate using a power supply voltage generation means that supplies a power supply voltage from outside the semiconductor element, fluctuations in the substrate potential during operation of the semiconductor memory device can be suppressed. In other words, in a semiconductor memory device that uses the memory cells described above, as with DRAM, fluctuations in the substrate potential always accompany charging and discharging of bit lines and peripheral circuits, and in particular, the effects of charging and discharging of bit lines are ignored. I can't come.

This is because in such a semiconductor memory device, it is inevitable that the coupling capacitance at the PN junction between the source or drain coupled to the bit line and the semiconductor substrate increases to some extent. Therefore, in such a semiconductor memory device, a predetermined potential is always applied to the semiconductor substrate in order to keep the substrate potential constant. For example, conventional DR
In AM, a charge pump is formed in a semiconductor element as a substrate voltage generating circuit by combining a ring oscillator, a diode, a capacitor, etc. However, since such a substrate voltage generation circuit is a high impedance power supply, it has poor ability to follow changes in substrate potential.
It is difficult to maintain a constant substrate potential. On the other hand, in the above-mentioned power supply voltage generation means that supplies the power supply voltage from outside the semiconductor element, the impedance of the voltage source is low and the ability to follow changes in the substrate potential is good. It is possible to suppress fluctuations. Therefore, in the present invention, by using the power supply voltage generation means as a substrate voltage generation circuit, fluctuations in substrate potential can be reduced, so that leakage current such as P-N junction leakage current between a storage node and a semiconductor substrate can be reduced. occurrence is further suppressed, refresh characteristics are improved,
Prevention of malfunctions caused by soft errors is more effectively achieved.

Furthermore, in the semiconductor memory device according to the present invention, word lines and plate lines are formed orthogonally as shown in FIGS. It becomes possible to select the lines and the plate lines using different addresses, thereby significantly reducing the probability of soft errors occurring during operation. The reason for this will be explained in detail below.

In a semiconductor memory device having a memory cell array as shown in FIGS. 1 and 2, when accessing a memory cell (11), the word line WL (4) and the plate line PL (13) are They are selected one by one based on different addresses, in other words, row addresses and column addresses. Thus, only the only memory cell (11) coupled to the selected word line WL (4) and plate line PL (13) is driven, and the bit line BL (16-) coupled to the selected memory cell (11) is driven. 1) or BL (1, 62) only. Therefore, when reading data, it is only necessary to release the precharged state of the bit line pair from which information is to be extracted.

On the other hand, in a semiconductor memory device having a memory cell array as shown in FIG. (
11) is accessed. Therefore, in the selected row, information is taken out from the memory cells (11) of all columns to the bit line BL (1B-1) or the bit line (1B-2), so the information is sent to these memory cells (11). , all bit lines BL (16-1) or BL (1B
-2) The information extracted must be rewritten. That is, when reading, before selecting the word line νL (4) and the plate line PL (13), the precharge state of all bit line pairs is released, and the word line ML (4) and the plate line PL (13) are released from the precharge state. After selecting (13) and driving the memory cell (11), it is necessary to activate the sense amplifier S/A (20) for all columns and perform rewriting.

As described above, soft errors occur when charges generated due to the entry of α particles into the semiconductor substrate flow into storage nodes and bit lines.

Of these, the charge is on the bit line BL (1B-1) or BL
(1B-2), the soft error occurs when the bit line BL (1G-2) is read.
1) or BL (1B-2) transitions from the precharge state to the floating state, the sense amplifier S/A (
20) occurs until it is activated. Therefore, in a semiconductor memory device having a memory cell array as shown in FIG. 16, in which bit line pairs in all columns are released from the precharge state when reading is performed, soft errors occur in all columns. There is a risk.

On the other hand, in a semiconductor memory device having a memory cell array as shown in FIGS. 1 and 2, the word line WL (4) and the plate line PL (13
) by using different addresses, it becomes possible to drive only the target memory cell (11). Therefore, it is only necessary to release the precharged state of the bit line pair for the same column as the target memory cell (11), which significantly reduces the probability of soft errors occurring in such a semiconductor memory device. be able to.

Furthermore, in the present invention, if the word line and plate line are selected using different addresses as described above when accessing a memory cell, information is sent to the bit line from only the one memory cell connected to the selected word line and plate line. is retrieved and then rewritten. In other words, according to such an operating method, as in a semiconductor memory device having a memory cell array as shown in FIG. There's no need to do it. Therefore, fluctuations in the substrate potential that occur due to charging and discharging of the bit line pair are suppressed, and the reliability of the semiconductor memory device can be greatly improved.

Furthermore, in the semiconductor memory device of the present invention, when the memory cell is a switching transistor or a CMOS type transistor, a peripheral circuit is formed on a well different from the well in which the memory cell is formed, and the peripheral circuit is By applying a reverse bias electric field to the well formed with the diffusion layer, it is possible to reduce the parasitic capacitance in the peripheral circuit and realize high-speed operation.

(Example) The present invention will be explained in detail below using examples.

First, a memory cell assembly as shown in FIG. 1 was formed by the following process. In addition, Figures 3 and 4
The figures are a plan view and a longitudinal cross-sectional view, respectively, showing such a process.

First, a SiN film is formed on the surface of a P-type silicon substrate (1) as a semiconductor substrate, and then the Si\: film is patterned by photolithography and reactive ion etching, leaving an element area and a Sl film. After removing
The surface of the P-type silicon substrate (1) is thermally oxidized at about 1000° C. to form a field oxide film (2) with a thickness of about 8000 nm in the element isolation region, and the SiN film is removed. (3rd and 4th
Figure (a)) Furthermore, after forming an oxide film with a thickness of about 100'A on the element region and depositing a conductor such as polycrystalline silicon with a thickness of about 3000A on it by CVD, photolithography technology is applied. Then, patterning is performed using dry etching to form a gate oxide film (3) and a gate electrode (5).

(Fig. 3.4(b)) Note that this gate electrode (5) also serves as a word line of the memory cell array. Next, using the gate electrode (5) as a mask, ions such as As are implanted into the element region to form an n-type source (6-1) and a train (6-2). (Figures 3 and 4 (C)) Next,
SiO with a thickness of approximately 5000 A is deposited on the entire surface using CVD method etc.
After forming a first interlayer insulating film (9) made of a polycrystalline silicon or the like, a plate line (13) made of polycrystalline silicon or the like is placed in a predetermined region on the first interlayer insulating film (9) to also serve as a word line. It is formed perpendicular to the gate electrode (5). (Figures 3 and 4 (d
)) Such a plate line (13) is formed by, for example, sequentially depositing polycrystalline silicon to a thickness of about 1,500 thick and molybdenum silicide to a thickness of about 4,000 thick on the first interlayer insulating film (9). Formed by photolithography and reactive ion etching. Further, a second interlayer insulating film (14) made of boron phosphorus silicate (BPSG) or the like is formed on the entire surface using CVD method or the like, and after the surface is flattened by heat treatment, the second interlayer insulating film (14) is formed. Insulating film (14
) is coated with a ferroelectric film (12) made of PZT or the like with a thickness of about 5,000 by using RF sputtering or the like.
form. (Figures 3 and 4 (e)) In addition, the above-mentioned second
The heat treatment of the interlayer insulating film (14) may serve as ring gettering as well as planarization of the film, and between the second interlayer insulating film (14) and the ferroelectric film (12), 5rTi
A buffer layer or barrier layer made of O, MgO, etc. may be formed. In addition, when forming the ferroelectric film (12), the P-type silicon substrate (1) is
It is desirable to heat it to about 600°C. Subsequently, a third interlayer insulating film (51
), or in this case, a ferroelectric film (12
) and the third interlayer insulating film (51), a buffer layer or a barrier layer may be formed. Thereafter, a hole for the electrode of the ferroelectric capacitor is formed at a predetermined position using a reactive ion etching method, etc., and a conductor such as tungsten is buried in this hole using a tungsten CVD method using silane reduction. 2) and a second electrode (8) which is coupled to the plate line (13) are formed. At this time, the hole for the first electrode (A) is provided deeper than the hole for the second electrode (8), and the first electrode (7) is connected to the source (6-1) or drain (6-2). reached the second
The electrode (8) reaches the plate line (3). (Third,
(Fig. 4(f)) Furthermore, when forming holes for electrodes, if etchants with different etching rates are used for the first interlayer insulating film (9) and the plate line (13), the first holes with different depths can be formed.
It is also possible to open the hole for the second electrode (A) and the hole for the second electrode (8) at the same time.

Next, a fourth interlayer insulating film (about 100 mm thick) made of phosphorus silicate or the like is formed on the entire surface using a CVD method or the like.
53), a contact hole is formed in a partial region on the source (6-1) by reactive ion etching, and a predetermined area on the fourth interlayer insulating film (53) including the contact hole is formed. A bit line (13) with a thickness of about 6000 A made of Afi is placed in parallel with the plate line (13) in the region of
1G-1, 113-2) are formed. (Figure 3.4 (
g)) In such a memory cell array, the first
As shown in the figure, two bit lines (1B-1, 16-2) are formed symmetrically with respect to one plate line (1B-1, 16-2). , 16-2) constitute a bit line pair. Finally, a protective film on the entire surface (155)
form. (Fig. 4 (h)) The present invention provides a semiconductor that can write, hold, and read digital information in any memory cell by adding appropriate peripheral circuits to the memory cell array as described above. You can configure storage devices. FIG. 5 shows a semiconductor memory device according to -
Figure 2 shows a block diagram of aspects.

The semiconductor memory device shown in FIG. 5 includes a memory cell array as shown in FIG. 1, a word line decoder (19), a sense amplifier S/A (20), and a dummy cell D/C (2I
), dummy word line decoder (22), I10 connection circuit (23), precharge circuit (24), equalization circuit (25), plate line driver (55), and column address selection line decoder (36) are added as shown. This is what I did. In such a semiconductor memory device, a sense amplifier S/A (20), an I10 connection circuit (23), a precharge circuit (24), an equalization circuit (25), a plate line driver (55), and a plate line driver (55) are provided for each column. , and the column address selection line C5L (12), and are controlled by the signals transmitted by these two types of signal lines. Furthermore, circuit diagrams embodying such sense amplifier S/A (20), 110 connection circuit (23), precharge circuit (24), equalization circuit (25), and plate line driver (55) are shown in FIG. , Fig. 7, Fig. 8.

It is shown in FIGS. 9 and 10. In such a semiconductor memory device, a signal for driving the plate line driver (55) is transmitted through the plate line driver drive line (42).
) is connected to the plate line driver (
55). However, the plate line driver (55) is driven only when the above-mentioned signal is input via the plate line driver drive line (42), and the column address selection line C5L (32)
It is driven only when a higher H level signal is transmitted. Therefore, by selecting the column address selection line C3L (32) by the column address, the plate line driver (55) to be driven can be selected.

Further, in the semiconductor memory device shown in FIG. 31, the column address selection line C3L (32) is coupled to the column address selection line decoder (36), and the column address selection line C3L is connected to the column address selection line decoder (36).
The selection (32) is made. Furthermore, other peripheral circuits provided for each column as described above are also controlled by signals transmitted by two types of signal lines including the column address selection line C3L (32), so that the column address By selecting the selection line C9L (32) using a column address, it is possible to selectively drive.

Furthermore, in the semiconductor memory device shown in FIG. It is coupled to column address selection line C3L (32). Therefore, if the signal line for driving the peripheral circuits mentioned above is activated after the column address selection line C3L (32) is selected by the column address, only the peripheral circuits in the same column will be sequentially driven. can reduce access time,
The reduction in power consumption is significant.

At this time, the timing of the activation of these signal lines is controlled by the respective clocks. Note that in such a semiconductor memory device, even if the above-mentioned peripheral circuits are not particularly coupled to the same column address selection line C3L (32), peripheral circuits in the same column are connected to the column address selection line C3L (32) to which they are respectively coupled. If the same signal is input through (32), it is possible to select the peripheral circuits in the same column regarding the peripheral circuits. Furthermore, in the semiconductor memory device shown in FIG. 5, the precharge circuit (24) and the equalization circuit (25) are each coupled to different signal lines,
A signal is transmitted to 4) by the precharge circuit drive line PC (31''), and a signal is transmitted to the equalize circuit (25) by the equalize circuit drive line (35), and each is controlled separately. In the semiconductor memory device according to the present invention, both the precharge circuit and the equalization circuit may be coupled to the precharge circuit drive line PC (35), and these circuits may be driven simultaneously. It is also possible to connect all the plate lines to a plate line decoder and select the plate line by using the plate line decoder instead of providing the plate lines for each column.

Next, a method of operating the semiconductor memory device shown in FIG. 5 will be described in detail.

FIG. 11 is a waveform diagram showing the timing of each operation when writing and writing to such a semiconductor memory device. Demonstrate operation.

In this embodiment, during the operation of the semiconductor memory device, a potential of V 2 is constantly applied to the P-type silicon substrate from the outside by the power supply voltage generating means. In the present invention, if the memory cell M/C (1, 1>) of a semiconductor memory device has a structure in which a P-type source/train region is formed on an N-type silicon substrate, an N-type The substrate potential of the silicon substrate is set to V. Therefore, when writing to a semiconductor memory device related to C, it is first set to WE (write enable) or L level, and then CE (chip enable) or H level. This causes the semiconductor memory device to identify the following series of operations or a write cycle.When CB falls, the memory cell M/C (1, 1) to which writing is to be performed is lowered to the L level. address and write information are externally applied to the address pin and pin, respectively.Also, in the precharge state where CE is at the Hn level, the precharge potential of the bit line pair is set to V, and the bit line pair The potential of PL (13) is also held at V2.

S In this embodiment, a case will be described in which the fetching of addresses and the like from the outside is controlled by the control signal CE of one bin, but the present invention is not limited to this, and for example, row addresses and column addresses are An address multiplex method may be used in which the address information is divided into RAS and CAS, respectively.

When CB goes to L level, the column address selection line decoder (36) decodes the column address, selects one column address selection line C5L (32), and selects the selected column address selection line C3L (32). The potential increases from ■ to V. In addition, ss that was not selected
cc The potentials of all other column address selection lines C3L (32) are held at V2. Next, the precharge release signal φPC is sent from the precharge circuit section S flow line PC (31).
In addition, an equalization cancellation signal φEQ is input from the equalization circuit drive line (35) to the precharge circuit (24) and the equalization circuit (25), respectively, and precharging and equalization of the bit line pair are canceled only for the selected column. .

On the other hand, at almost the same time, the word line decoder (19) decodes the row address to select one word line WL (4) and transmits a drive signal from the word line WL (4). The MOS transistor of the memory cell M/C (11) coupled to the word line WL (4) becomes conductive. The timing for selecting the word line WL(4) may be before or after the precharge of the bit line pair is released as described above. Also, at this time, the potentials of the bit line pair and the plate line PL(13) are both S, so the ferroelectric No change in the polarization state of the capacitor occurs.

Also, in parallel with these operations, write information is taken into the buffer, and input/output lines l10 (34-1) and l10 (34-2),
In other words, the input/output line pair is charged with the potentials of ■ and ■.

ss cc Next, the input/output line connection signal φ is input from the input/output line connection signal line (37) to the 110 connection circuit (23), and the bit line pair and input/output line pair of the selected column are connected. Person 8 force line pair V, ■ electric SS
CC position is taken into the connected pair of focus lines. At this time,
The memory cell M/C (which is accessed by selecting the row address and column address and which performs writing)
11) Focus line BL (16-1) or BL connected to
When the potential of V is taken into (1B-2), the MOS transistor of the memory cell M/C (11) is in a conductive state at the potential of the plate line PL (13) or V. Information “■” is written immediately.

On the other hand, the bit line BL (1B-1) connected to the memory cell M/C (11) Matach BL (1,6-2>i:
V) Insertion of potential S In rare cases, after this, the plate line P of the selected column
Information is written when a drive signal is transmitted from L(13). That is, the plate line trino (drive line (4
2) The plate line driver drive signal φPL is input to the plate line driver (55), and the plate line driver (55) is driven for the selected column to increase the potential of the plate line PL (13) from V. . (After a certain period of time, plate line trino) Drive signal φP
When the input of L ends, the potential of the plate line PL (13) drops to ■. Since the MOS transistor in the memory cell M/C (11) to which data is written is in a conductive state, at this time the memory cell M/C (11) is in a conductive state.
In other words, in the write operation of this embodiment, the information written by accessing the memory cell M/C (11) as described above or "1" is written to 1). In either case, information related to the target memory cell M/C (11) is written.

Note that in the semiconductor memory device according to the present invention, when accessing the memory cell M/C (11) as described above, other memory cells in the same column as the accessed memory cell M/C (L 1 ) In M/C (11), Ctl-V, between both electrodes of the ferroelectric capacitor.

A potential difference of Cf+Cd (where Cd is the capacitance of the depletion layer between the P-type silicon substrate and the N-type diffusion region in the memory cell array, and Cr is the capacitance of the ferroelectric capacitor) is generated. Therefore, it is necessary to design the ferroelectric capacitor to be ferroelectric so that polarization reversal does not occur in such a ferroelectric capacitor.

Subsequently, in this embodiment, after accessing the memory cell M/C (11), first, the input/output line connection signal φ is
The input to the 110 connection circuit (23) of V,
■ The bit line pair with the potential of is input ss
cc It is separated from the output line pair and is further connected to the precharge circuit (2
The precharge signal φ and the equalize signal φEQ are respectively input to the equalizing circuit (25) and the equalizing circuit (25), and the bit line pair is precharged. At this time, the precharge potential of the bit line pair is 1, which is equal to the substrate potential applied to the SP type silicon substrate, and the potential of the plate line PL (13) is also V, S. Next, the word line WL (4) selected by the word line decoder (19) returns to the unselected state, and the MO of the memory cell M/C (11) coupled to the word line WL (4)
The S-type transistor becomes non-conductive. After this, CE becomes H level again, and the column address selection line decoder (3
Column address selection line C3L (3) selected by column address selection line C3L (3)
2) becomes unselected, and the input/output line pair is disconnected from the D buffer, and the potential becomes 11n.
A precharge state of 2V is entered, and the series of C write operations is thereby completed. In the present invention, by performing writing at the operation timing shown above,
The potential of the storage node after the write operation is completed can be made equal to the substrate potential of the semiconductor substrate. Furthermore, in the present invention, when retaining the information written by the above-described operation, the potential of the plate line is held at 2, and the potential of the picture electrode of the ferroelectric capacitor of the Memo S recell is made equal to the potential. desirable.

Further, FIG. 12 is a waveform diagram showing the timing of each operation when reading the semiconductor memory device shown in FIG. 5, and shows the read operation of the semiconductor memory device without referring to FIG. 12.

When reading, while WE is kept at H level, CE is lowered from H level to L level. This allows the semiconductor memory device to identify that the following series of operations is a read cycle. When CE goes to L level, one column address selection line C3L (32) is selected by the column address selection line decoder (36), and the selected column address selection line C8L ( The potential of 32) increases from V to V. Next, in the same manner as in the ss cc write operation, the precharge and equalization of the bit line pair are canceled, and almost simultaneously with these operations, one word line WL (4) becomes selected, and the corresponding word By transmitting a drive signal from the line WL(4), the MOS transistor of the memory cell M/C(l l ) coupled to the selected word line WL(4) becomes conductive.

Next, the plate line driver drive signal φPL is output from the plate line driver drive line (42) to the plate line driver (5).
5), the plate line driver (55) is driven for the selected column to boost the potential of the plate line PL (13) from V to ■, and the drive signal or ss
cc transmitted. As a result, the plate line PL(13)
and the information stored in the memory cell M/C (11) connected to the selected word line -°I, (4) or the focus line BL (161) or BL (1B-) connected thereto.
2>. Below, we will explain the case where such information is taken out to the bit line BL (1B-1). At this time, the potential of the bit line BL (16-1,) is stored in the memory cell M/C (11). Is there any information about it?”1
In the case of ``, it increases significantly, and in the case of ``0pa, it increases slightly.

Meanwhile, in parallel with this, a dummy word line decoder (22)
By selecting the dummy word line guard L (33-1, 33-2) and driving the dummy cell D/C (21), the potential of the bit line BL (16-2) changes to the bit line BL ( 1, 6-1>, the potential is intermediate between the potential when information of "1" is extracted and the potential when information of "0" is extracted.

Furthermore, as mentioned above, memory cell M/C(l I )
When the information stored in the bit line BL (16-1) is extracted and a potential difference is generated between the bit line pair, the sense amplifier activation lines ACT (49-1) and ACT (49-2) are activated.
), a sense amplifier activation signal φACT'φ is inputted to the sense amplifier S/A (20), and the sense CT amplifier S/A (20) in the selected column is activated. At this time, in order to perform high-speed sensing operation, the sense amplifier S/A (20)
In ACT, φ that activates the PMOS type flip-flop circuit is inputted before φ that activates the NMO5 type flip-flop circuit. As a result, the potential difference between the pair of bit lines is amplified by the sense amplifier S/A (20), and one potential becomes V
Then, the other potential is determined to be V.

CC88 Next, the input/output line connection signal φ is inputted from the input/output line connection signal line (37) to the I10 connection circuit (23), and is connected to the bit line pair whose potential difference is amplified by the sense amplifier S/A (20). The input/output line pair is connected, and information taken out to the bit line pair is transmitted to the input/output line pair. This information is then read out through the output buffer as the output signal D2. Furthermore, the connection between the ut bit line pair and the input/output line pair is disconnected after a certain period of time by terminating the input of the input/output line connection signal φ to the 110 connection circuit (23). The potential of the output line pair is held at V and Vss
cc.

Next, in the semiconductor memory device according to the present invention, after information is extracted from a predetermined memory cell M/C (11) by the above-described operation, rewriting to the memory cell M/C (11) is performed. , memory cell M/C (1,
If the information stored in 1) is 0, the bit line connected to the memory cell M/C (ll) is activated by activating the sense amplifier S/A (20) as described above. Since the potential of BL (16i) is determined to be V, and the potential of plate line PL (13) is held to V, CC, rewriting is performed at this time.

On the other hand, if the information stored in the memory cell M/C (11) is "l", then the input of the plate line driver drive signal φPL to the plate line driver (55) is finished, and the plate line driver drive signal φPL is input to the plate line driver (55). Rewriting is performed when the potential of line PL (13) is returned to V.sub.2. In other words, by such an operation, the memory cell M/C (11
) or °'l-"0'", the information stored in the memory cell M/C (11) is retained even after reading.

Furthermore, in the read operation according to the present invention, following access to the memory cell M/C (tt) as described above, first the sense amplifier activation signals φ and φ are sent to the sense amplifier S/A (20). The input ACT ACT is completed, the sense amplifier S/A (20) is returned to the inactive state, and then the precharge signal φPC and the equalize signal φEQ are input to the precharge circuit (24) and the equalize circuit (25), respectively. The bit line pair is precharged. At this time, the precharge potential of the bit line pair is V2, which is equal to the substrate potential applied to the P-type silicon substrate S2, and the potential of the plate line PL (13) is also 2. Next, the word line WL selected by the word line decoder (19)
(4) returns to the non-selected state, and the MOS transistor of the memory cell M/C (11) coupled to the word line WL(4) becomes non-conductive. After this, CB becomes H level again, and the column address selection line C3L (32) selected by the column address selection line decoder (36) becomes unselected, and the input/output line pair is disconnected from the Din buffer and the potential is lowered to V. The precharge state of cc is entered, and the series of read operations is thereby completed. In the present invention, by performing reading at the above-described operation timing, the potential of the storage note after the completion of the reading operation can be made equal to the substrate potential of the semiconductor substrate. Needless to say, even after performing such a read operation, the potential of the plate line PL (13) is maintained at V, and the potential of the picture electrode of the ferroelectric capacitor of the memory cell M/C (11) is made equal to the potential. In this state, the memory cell M/C
It is preferable to retain the information stored in (11).

In the operating method of the semiconductor memory device of the present invention as described above, the potential of the storage node is held at the same potential as the substrate potential of the semiconductor substrate after accessing the memory cell, and the potential of the storage node is maintained at the same potential as the substrate potential of the semiconductor substrate, and When the charged state is released and the bit line becomes a floating state, the potential of the bit line is also equal to the substrate potential. Therefore, there is less risk of charge diffusion and movement from the semiconductor substrate to the diffusion layer, which causes soft errors and deterioration of refresh characteristics. Further, fluctuations in substrate potential on the semiconductor substrate are small, and extremely stable operation can be performed.

[Effects of the Invention] As described in detail above, the method of operating a semiconductor memory device of the present invention provides good refresh characteristics, low probability of malfunction, low power consumption, and highly reliable read operation. A write operation is implemented. Further, according to the present invention, based on such improved reliability, a ferroelectric capacitor having a smaller capacitance than the ferroelectric capacitors used up to now can be used in the memory cell. Also, in the case of a switching transistor, for example, if it is a switching transistor or an MO5 type transistor, it is possible to make the depletion layer thinner and the channel shorter, and as a result, the switching transistor can be made smaller. Therefore, it becomes possible to promote higher integration of semiconductor memory devices.

Its industrial value is great.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a memory cell array according to the present invention, FIG. 2 is a circuit diagram showing another example of a memory cell array according to the present invention, and FIG. 3 is a circuit diagram showing a memory cell array according to the present invention. −
FIG. 4 is a plan view showing an example of a process for forming an array, FIG. 4 is a longitudinal sectional view showing an example of a process for forming a memory cell array according to the present invention, and FIG. 5 is an embodiment of a semiconductor memory device according to the present invention. 6 is a circuit diagram showing the configuration of the sense amplifier used in the present invention. FIG. 7 is a circuit diagram showing the configuration of the I10 connection circuit used in the present invention.
The figure is a circuit diagram showing the configuration of a precharge circuit used in the present invention, Figure 9 is a circuit diagram showing the configuration of an equalization circuit used in the present invention, and Figure 1O is a circuit diagram showing the configuration of a plate line driver used in the present invention. 11 is a waveform diagram showing the timing of each operation in the write operation according to the present invention, FIG. 12 is a waveform diagram showing the timing of each operation in the read operation according to the present invention, and FIG. Fig. 14 is a characteristic diagram showing the relationship between the voltage applied to the ferroelectric capacitor and the amount of charge stored, Fig. 14 is a circuit diagram showing the general configuration of a memory cell using a ferroelectric capacitor, and Fig. 15 is a A block diagram showing part of the layout of a semiconductor memory device equipped with the memory cells shown in FIG. 14, and FIG.
5 is a block diagram showing the layout of a semiconductor memory device including the memory cells shown in FIG. 4. FIG. 4...Word line, 11...Memory cell, 13...
Plate line, 16...Bit line, I7...MO5 type transistor, 18. Ferroelectric capacitor

Claims (4)

[Claims] (1) Memory cells consisting of a ferroelectric capacitor and a switching transistor formed on a semiconductor substrate are arranged in a matrix, and one electrode of the ferroelectric capacitor is connected to a bit line through the source and drain of the switching transistor. , the other electrode of the ferroelectric capacitor is connected to a plate line, and the gate electrode of the switching transistor is connected to a word line, in which a drive signal is transmitted from the word line. to make the switching transistor conductive, and after accessing the memory cell by transmitting a drive signal from the plate line, the potentials of the bit line and the plate line are made equal to the substrate potential of the semiconductor substrate. A method of operating a semiconductor memory device, comprising: stopping a drive signal transmitted from the word line to make the switching transistor non-conductive. 2. The method of operating a semiconductor memory device according to claim 1, wherein the precharge potential of the bit line is made equal to the substrate potential of the semiconductor substrate. (3) The semiconductor according to claim 1 or 2, wherein the semiconductor substrate is connected to power supply voltage generation means for supplying power supply voltage from the outside, and a substrate potential is applied to the semiconductor substrate by the power supply voltage generation means. How storage devices work. (4) Claim 1, 2 or 3, wherein the word line and plate line transmitting the drive signal are selected by different addresses when accessing the memory cell.
A method of operating the semiconductor storage device described above.