JPH0464106B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system.

[Conventional technology]

Conventionally, in a multiprocessor system, data transmission and reception between a main processor and a plurality of slave processors is controlled by a polling operation of a microprocessor provided in the main processor.

[Problem that the invention seeks to solve]

In such a multiprocessor system, the slave processor is provided with means for displaying the state in which data has been written to the transmission buffer and means for indicating the empty state of the reception buffer, so that the main processor The microprocessor in the main processor itself reads the transmission/reception status of the slave processor by scanning the two status display means. For this reason, in a multiprocessor system that includes many slave processors, when data is being transferred from the main processor to one of the slave processors, the main processor will determine whether or not there is any data to send to the next processor. Since nothing is shown to the slave processor, it may take some time to send or receive the next data. An object of the present invention is to provide a multiprocessor system that can smoothly transmit and receive data in any state.

[Means for solving problems]

In order to achieve the above object, the present invention provides a multi-processor system including one main processor and a plurality of slave processors connected to each other, in which a main processor is connected to one of the slave processors. a reception display means for displaying the end of the transfer data written to the reception buffer of the slave processor when transferring data and indicating that the slave processor has processed the transfer data; and a read result of the reception display means. a reception mode display means for displaying a mode indicating that there is still data to be transferred when the slave processor is unable to receive data; displays a request to send the data written to the main processor, and when the receive mode display means displays a mode indicating that there is still data to be transferred, displays a request to send the data to the main processor; transmission request display means for displaying a mode indicating a request to receive transfer data from the main processor when the reception mode display means displays a mode indicating that there is still transfer data; is provided in the slave processor.

〔Example〕

Next, embodiments of the invention will be described with reference to the drawings.

Referring to FIGS. 1, 2, and 3, the multiprocessor system in this embodiment has one
The main processor 100 and a plurality of slave processors 300, 301 to 30n are connected to each other by an input control signal line 21, an output control signal line 22, a bidirectional data bus 23, and a response signal line 24. It is connected via an address bus 25. The main processor 100 includes a microprocessor 11 and a polling control section 1 connected to the microprocessor 11 via a control bus 1A.
It consists of 2. As shown in detail in FIG. 2, the control bus 1A is connected to a microprocessor address bus 12A connected to an output selection section 124, an automatic scanning address bus 12F which is the output of the counter 122, and an automatic scanning address bus 12F in the polling control section 12. The automatic scanning control signal line 12B connected to the scanning start/stop control section 121 and the response detection section 12
It is connected to the response detection signal line 12D which is the output of No. 3. In addition, a plurality of slave processors 30
The response signal line 24 from 0, 301 to 30n is connected to the response detection section 123, and its output line, the response detection signal line 12D, is connected to the control bus 1A and the automatic scanning start/stop control section 121. Automatic scanning start/stop control section 121
is sent to the counter 122 via the clock supply line 12C,
It is also connected to the output selection section 124 via an address bus output selection signal line 12E. counter 122
The automatic scanning address bus 12F, which is the output of
~30n.

On the other hand, each slave processor 300, 30
1 to 30n are comprised of a transmission/reception control section 31, a transmission/reception buffer 32, a transmission/reception status display section 33, and a microprocessor 34, as shown in detail in FIG. Address bus 25 is address bus 3 connected to address comparison section 311 of transmission/reception control section 31.
1A and a data/mode control signal line 31B connected to the interface control section 312. Address comparison section 311 is connected to main processor 100 and interface control section 312 via response signal line 24 . Main processor 10
The input control signal line 21 and output control signal line 22 from 0 are connected to the interface section 312. The bidirectional data bus 23 also includes a transmission buffer 321, a reception buffer 322, and a transmission request display section 3.
31, transmission mode display section 332, reception display section 33
3, and is connected to the reception mode display section 334,
Bidirectional data bus 32C in the transmitting/receiving buffer 32
and a bidirectional data bus 33C in the transmission/reception status display unit 33, and are connected to the microprocessor 34 by a control bus 3E. Furthermore, the transmission buffer read signal line 3A, which is the output of the interface control unit 312, is connected to the transmission buffer 321.
The reception buffer write signal line 3B is the reception buffer 3
22, the transmission status display lead signal line 3C is connected to the transmission request display section 331 and the transmission mode display section 332.
The reception state display read/write signal line 3D is connected to a reception display section 333 and a reception mode display section 334, respectively. The control bus 3E includes a bidirectional data bus 32C inside the transmission/reception buffer 32 and a bidirectional data bus 33C inside the transmission/reception status display section 33.
, a transmission buffer write signal line 32A connected to the transmission buffer 321, a reception buffer read signal line 32B connected to the reception buffer 322,
Transmission request display section 331 and transmission mode display section 3
A transmission display read/write signal line 33A connected to 32 and a reception display read signal line 3 connected to reception display section 333 and reception mode display section 334.
3B.

Next, the operation of the multiprocessor system configured as described above will be explained.

For example, when data is transferred from the main processor 100 to the slave processor 300,
Microprocessor 1 of main processor 100
1 controls an automatic scan start/stop control section 121 of the polling control section 12 by an automatic scan control signal via a control bus 1A and a signal line 12B. This control section 121 is connected to the output selection section 124 by an address bus output selection signal via a signal line 12E.
The microprocessor address bus 12A is connected to the address bus 25. The microprocessor 11 also sends input control signals to the signal line 2.
Output via 1. As a result, the main processor 100 reads the status of the reception display section 333 of the slave processor 300. At this time, in the slave processor 300, the address comparison section 311 of the transmission/reception control section 31 outputs a response signal to the signal line 24. In addition, a reception status display read/write signal is output from the interface control unit 312 of the transmission/reception control unit 31 according to the data/mode control signal input to the signal line 31B and the input control signal from the signal line 21, and the bidirectional data bus 23, the data of the reception display section 333 of the status display section 33 is output. When the main processor 100 reads the status of the reception display section 333 and determines that the slave processor 300 can receive data, the main processor 100 sends address information to the bus 31A and data/mode control to the signal line 31B. An output control signal is output to the signal line 22, and data is output to the bidirectional data bus 23, respectively.
Data is written to the receive buffer 322 of the transmit/receive buffer 32. When data writing is completed, main processor 100 changes the data/mode control signal to set data indicating completion of data writing on reception display section 333. The microprocessor 34 of the slave processor 300 detects this write completion data, reads the write transfer data from the reception buffer 322, and then clears the reception display section 333, thereby completing the data transfer.

On the other hand, when transmitting data from the slave processor 300 to the main processor 100, the microprocessor 34 of the slave processor 300 writes the transmission data to the transmission buffer 321, and also writes data indicating a transmission request to the transmission request display section 331. Set. In the main processor 100, in cases other than data transfer with a specific slave processor, that is, the processor 300, the automatic scan start/stop control section 1 is activated by an automatic scan control signal.
21, switches the output selection section 124 by the address bus output selection signal, connects the automatic scanning address bus 12F to the address bus 25, and outputs a clock signal to the counter 122 at regular intervals via the clock supply line 12C. to start automatic scanning. When the automatic scanning address and the slave processor address match, a response signal is output from the address comparator 311 of the slave processor 300. This response signal is sent to the main processor 10.
0 is detected by the response detection unit 123 and connected to the signal line 12D.
A response detection signal is output. When the response detection signal is output, the output of the clock signal from the automatic scan start/stop control section 121 is stopped, and the automatic scan is stopped. Further, the microprocessor 11 recognizes the stop of automatic scanning based on the response detection signal, and transfers the contents of the counter 122, which is the response slave processor address, to the automatic scanning address bus 12F.
and the transmission request display section 331 of the slave processor 300 corresponding to the address, that is, the slave processor number, read via the control bus 1A.
Read the status of. In addition, the slave processor 30
The contents of the transmission buffer 321 of 0 are read and the data is received. As a result, the main processor 100 receives the transmission request display section 33 of the slave processor 300.
Clear 1.

Note that when data is transferred from the main processor 100 to the slave processor 300 described above, if the read result of the reception display section 333 is not received (for example, the previously sent data has not yet been received by the slave processor). etc.), the main processor 100 writes a mode indicating that there is transfer data in the reception mode display section 334.
After the microprocessor 34 of the slave processor 300 reads the data from the receiving buffer 322,
If the content of the reception mode display section 334 is read and the mode indicating that there is transfer data is read, the transmission request data is written in the transmission request display section 331, and the mode indicating the data reception request is written in the transmission mode display section 332. . And main processor 10
0 indicates that even if there is a transmission request from the slave processor 300 as a result of automatic scanning, if the mode is written in the transmission mode display section 332, the slave processor 300 requests reception without performing a data reception operation. Send data to.

The case where data is transmitted and received between the main processor 100 and the slave processor 300 has been described above.
The same applies to 1 to 30n.

〔Effect of the invention〕

As explained above, according to the present invention, even when the main processor wants to continuously transmit data and the reading result of the reception display means of the slave processor indicates that data cannot be received, the main processor can transmit and receive the next data. It can be done smoothly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the detailed structure of the polling control section in FIG. 1, and FIG. 3 is a block diagram showing the detailed structure of the slave processor in FIG. 1. It is. 100...Main processor, 300, 301
~30n...Slave processor, 11...Microprocessor, 12...Polling control unit, 1
A... Control bus, 21... Input control signal line, 22
... Output control signal line, 23 ... Bidirectional data bus, 24 ... Response signal line, 25 ... Address bus, 31 ... Transmission and reception control section, 32 ... Transmission and reception buffer, 33 ... Transmission and reception status display section, 34 ...Microprocessor, 3A...Transmission buffer read signal line, 3B...Reception buffer write signal line, 3C
...Transmission status display read signal line, 3D...Reception state display read/write signal line, 3E...Control bus, 12A...Microprocessor address bus, 12B...Automatic scan start/stop control signal line, 12C... ...Clock supply line, 12D...
Response detection signal line, 12E... Address bus output selection signal line, 12F... Automatic scanning address bus, 3
11...Address comparison unit, 312...Interface control unit, 31A...Address bus, 31B
...Data/mode control signal line, 321...Transmission buffer, 322...Reception buffer, 32A...
Transmission buffer write signal line, 32B...Reception buffer read signal line, 32C...Bidirectional data bus, 331...Transmission request display section, 332...Transmission mode display section, 333...Reception display section, 334...
...Reception mode display section, 33A...Transmission display read/write signal line, 33B...Reception display read signal line, 33C...Bidirectional data bus.

Claims (1)

[Claims] 1. In a multiprocessor system including one main processor and a plurality of slave processors connected to each other, when data is transferred from the main processor to any of the slave processors. , a reception display means for indicating the end of the transfer data written to the reception buffer of the slave processor and indicating that the slave processor has processed the transfer data; and a read result of the reception display means indicating that the data cannot be received. A reception mode display means for displaying a mode indicating that there is still data to be transferred when there is data to be transferred; Transmission request display means for displaying a data transmission request and displaying a transmission request to the main processor to transmit the transfer data when a mode indicating that there is still data to be transferred is displayed on the reception mode display means. and, when the reception mode display means displays a mode indicating that there is still transfer data, a transmission mode display means for displaying a mode indicating a request to receive transfer data from the main processor; A multiprocessor system characterized by the following: