JPH045213B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an ECC circuit diagnostic method for diagnosing an ECC circuit having a memory error check and correction function, so-called ECC function.

[Technical background of the invention]

Generally, this type of ECC circuit has not only the ECC function but also the ECC function.
It has a function of generating check bit C for ECC. Conventionally, this check bit C has been added to one word (all words) of memory data as shown in FIG. In this example, the configuration is 64 bits, and the check bit C is 8 bits. In the case of memory read access, one word of 64-bit memory data read from the memory array 11 under the control of the memory controller 10 and the 8-bit check bit C are transferred to the memory controller 1.
The signal is input to the ECC circuit 12 provided at 0.
The ECC circuit 12 performs well-known ECC operations based on this input information and outputs correct 64-bit memory data. The memory controller 10 is 1
ECC circuit 1 for word memory read access
The 64-bit memory data output from 2 is sent as is to the system bus 13, and 1/2 word (half word),
In the case of a 1/4 word or 1/8 word (1 byte) memory read access, memory data at the corresponding data bit position is sent to a predetermined zone position on the system bus 13. System bus 1
3 is transferred to the CPU 14 or input/output devices (hereinafter referred to as I/O) 15, 16, etc.

On the other hand, in the case of memory write access, for example 1
For word (64 bit) writing, ECC circuit 1
2 generates a check bit C for one word of write data transferred via the system bus 13. This write data and check bit C are written into the memory array 11 under the control of the memory controller 10. On the other hand, when writing 1/2 word (32 bits), for example, one word of memory data and check bit C are read out from the corresponding address position in the memory array 11 under the control of the memory controller 10. Next, 1/2 word of 1 word of memory data, which is the continuation data, and 1/2 word of write data transferred via system bus 13 are combined and sent to ECC circuit 12 as 1 word of write data. Given. ECC circuit 12
generates a check bit C for one word of written data after this synthesis. The subsequent operation is the same as in the case of writing one word.

[Problems with background technology]

In a system equipped with an ECC circuit like this,
During memory read access, the ECC function of the ECC circuit allows correct memory data to be transferred. However, in conventional systems, if a failure occurs in the ECC circuit itself, errors in the read data are not detected, resulting in the erroneous data being transferred to the CPU, etc.
In addition, during memory write access, if one word is not written, in order to write one word of data, the memory array must be accessed for memory read access and one word of memory data must be successively read out. However, it also had the disadvantage of long access times.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its object is to provide an ECC circuit diagnostic method that can diagnose an ECC circuit when accessing a memory of 1/m words and has the same error resolution.

Another object of the present invention is to provide an ECC circuit diagnostic method that can improve performance by eliminating the need to perform a 1-word memory read access prior to 1/m-word memory write access. .

[Summary of the invention]

In the present invention, instead of adding a check bit to one word of memory data as in the past,
Check bits are added in memory data units of 1/n (n is an integer of 2 or more) words.
Therefore, in the present invention, n memory arrays to which check bits are added in memory data units of 1/n words, and n units corresponding to each of these memory arrays are provided.
An ECC circuit is also provided. In such a configuration, for memory access of 1/m (m is an integer satisfying m≧n) words, n units of memory can be accessed.
Among the ECC circuits, the circuit that requires ECC operation is 1.
However, in the present invention, the remaining ECC circuits are also made to perform ECC operations for common 1/n words. If the above memory access is a memory read, the n ECC circuits diagnose and correct (error detection, error correction) the common 1/n words successively read from one of the n memory arrays. Let's do it. If all n ECC circuits are normal,
The error detection results of each ECC circuit are bound to be the same. Therefore, by comparing the operation results of each ECC circuit, for example, the error detection results, using the comparison section,
Can diagnose ECC circuits.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. Note that the same parts as in FIG. 1 are given the same reference numerals and detailed explanations are omitted. In the system shown in FIG. 2, 20 is a memory device, and one word is, for example, 64
Bit memory data is handled. 21 and 22 are memory arrays forming the memory device 20.
The memory array 21 stores the upper half word (1/2 word) of the 64-bit memory data per word, that is, bits 0 to 64 bits.
It is used to store 32 bits of bit 31, and memory array 22 is also used to store the lower half word (1/2 word), bits 32 through 63. That is, this embodiment is a case where n=2.
In addition to the half-word memory data, check bits C (7 bits) of the half-word memory data are added and stored in the memory arrays 21 and 22.

30 is a memory controller. The memory controller 30 connects the memory device 20 and the system bus 1
3, and controls memory access to the memory device 20. 31 and 32 are ECC circuits built into the memory controller 30. ECC31, 32 are memory arrays 21, 2
2. Bit 0 of the data zone of system bus 13
- Bits 31 and 32 to 63 are provided respectively. ECC circuits 31 and 32 perform check bit C generation, error detection, and error correction.
It has an ECC operation function. ECC circuit 31, 3
2 is controlled by the memory controller 30. 33 is a comparison section (hereinafter referred to as COMP). COMP33 is ECC circuit 31,3
The two ECC operation results (generated check bit C, signal indicating the presence or absence of a 1-bit error or multi-bit error as an error detection result) are compared to detect coincidence/mismatch.

Next, the operation of one embodiment of the present invention will be explained. The memory controller 30 is the CPU 14 or I/O 1
Memory access control is performed in response to memory access requests from 5 and 16. Assume now that this request is a one-word (all-word) read request for reading one word of memory data. Under the control of the memory controller 30, the upper half words (bits 0 to 64 bits) of the corresponding word (64 bits) are read from the memory array 21.
32 bits of bit 31) and check bit C (7 bits) added to the half word are read out.
Similarly, from the memory array 22, the lower half word (32 bits from bit 32 to bit 63) of the corresponding one word above and the check bit C (7
bit) is read out. The upper half word and its check bit C (39 bits) read from the memory device 20 (memory array 21) are input to the ECC circuit 31, and the lower half word read from the memory device 20 (memory array 22) is input to the ECC circuit 31. The half word and its check bit C (39 bits) are input to the ECC circuit 32. The ECC circuits 31 and 32 detect errors based on these input half words and their check bits C, perform error correction if necessary, and correct upper half words (32 bits) and lower half words (32 bits), respectively. bits). The memory controller 30 sends the upper half word output from the ECC circuit 31 to the bit 0 to bit 31 zone of the data zone of the system bus 13, while sending the lower half word output from the ECC circuit 32 to the system bus 13. It is sent to the zone of bit 32 to bit 63 of the data zone. Therefore, the operation when reading one word is almost the same as that of a conventional system equipped with one ECC that processes one word. 1
In the case of word reading, since the ECC circuits 31 and 32 process half a different word, the comparison result of the COMP 33 is ignored. Also,
The operation of COMP33 may be prohibited.

Next, the operation when reading the upper half word of one word of memory data will be explained. The memory controller 30 performs one-word reading even in the case of half-word reading (similar to the conventional memory controller 10). As a result, the memory controller 30
A desired upper half word and its check bit C read out from the memory array 21 and an undesired lower half word read out from the memory array 22 and its check bit C are inputted to the .

By the way, in systems that handle memory data where one word is 64 bits, in addition to single word (full word) access, 1/2 (half word) access, 1/4 access,
It is configured to allow 1/8 access. Generally, the zone positions where 1/2 word, 1/4 word, or 1/8 word memory data travel back and forth in the 64-bit data zone of the system bus are each uniquely determined. For this reason, one
A conventional memory controller with an ECC circuit is
Even if one word (full word) is not read, one word is read, the ECC circuit is operated for this one word, and 1/2 word 1/4 word of the desired bit position is output from the ECC circuit. It has a so-called zone control function that selects , or 1/8 word and sends it to a predetermined zone position on the system bus.
FIG. 3 shows an example of reading out upper half words regarding this zone control. That is, from the memory data of 64 bits per word (after error correction) read out from the memory device, the desired upper half word (bits 0 to 0) shown in the shaded area a in FIG.
bits 31 to 32) are selected by the memory controller. The selected upper half word is then sent to the lower 32 bit zone of the 64 bit data zone of the system bus, that is, the zone of bits 32 to 63 shown by the shaded area b in FIG. Therefore, the ECC circuit 3 corresponds to bits 0 to 31 of the data zone of the system bus 13.
In this embodiment, an ECC circuit 32 is provided corresponding to bits 32 to 63. In the case of half-word reading, the ECC circuit 32 is operated and the output of the ECC circuit 32 (half-word memory data) in the data zone of system bus 13.
It will be easily understood that it is necessary to send the signal to the positions from bit 31 to bit 63. At this time, the ECC circuit 31
There is no problem even if the ECC circuit 31 is in an idle state, but in this embodiment, the ECC circuit 31, which may be in an idle state, is also operated when reading an upper half word.
This is intended to perform self-diagnosis of the ECC circuits 31 and 32.

The desired upper half word inputted to the memory controller 30 (which is the output of the memory array 21) and its check bit C are sent to the memory controller 30.
The signal is input to both ECC circuits 31 and 32 under the control of 0. On the other hand, the undesired lower half word (which is the output of the memory array 22) and its check bit C are sent to the ECC circuit 32 as well as the ECC circuit 31.
input is also prohibited. This can be easily realized by providing a selector that selects either the upper half word or the lower half word and directs it to the ECC circuit 32. Note that the selector is omitted in FIG. 2. Memory controller 30 is ECC
Not only the circuit 32 but also the ECC circuit 31, which may originally be in the address state, is operated. This results in
ECC circuits 31 and 32 perform error detection based on the above upper half word and check bit C, which are the same data. As a result of error detection, the ECC circuits 31 and 32 output signals indicating the presence or absence of a 1-bit error or the presence or absence of a multi-bit error. COMP
33 compares the signals output from these ECC circuits 31 and 32 and detects coincidence/mismatch. In this case, the ECC circuits 31 and 32 perform error detection based on the same data as described above, so if both the ECC circuits 31 and 32 are normal,
COMP33 should perform match detection. That is, if a match is detected by COMP33, both ECC circuits 31 and 32 are normal;
If a discrepancy is detected by COMP33
It can be diagnosed that either the ECC circuit 31 or 32 is at fault. As a result of error detection, the ECC circuits 31 and 32 correct the erroneous bit if it is possible to correct the error and output it as correct half-word read data. The memory controller 30 sends the half-word read data output from the ECC circuit 32 to the zone positions of bits 32 to 63 of the 64-bit data zone of the system bus 13. In contrast,
The half-word read data output from the ECC circuit 31 is not sent to the zone positions of bit 0 to bit 31 on the system bus 13. This is a function that conventional memory controllers had for reading half words, that is, reading a whole word (one word) from the memory device, and this whole word (actually
A predetermined position from the entire word output from the ECC circuit (bit 0 if reading the upper half word)
~Bit 31, bit if lower half word reading
This can be easily achieved by using the zone control function that selects a half word from bit 32 to bit 63) and sends it to the zone position from bit 32 to bit 63 on the system bus.

By the way, the diagnosis of the ECC circuits 31 and 32 is not limited to the case of upper half word reading, but also the diagnosis of the memory array 2.
It is clear that 1/4 word reading or 1/8 word reading can be performed as long as only memory data within 1 is to be read. In this case, the memory controller 30 selects 1/4 of the predetermined position from among the upper half words output from the ECC circuit 32.
bits 48 to 63 of the data zone of system bus 13 for 1/4 word reading, and bit 56 for 1/8 word reading.
~ It will be sent to the zone position of bit 63.

Next, the operation when the memory access request is to write the upper half word will be explained. In this case, the memory array 21 corresponding to the upper half word is stored.
It will be easily understood that it is necessary to operate the ECC circuit 31 to generate the check bit C and to guide the half word to which the check bit C has been added to the memory array 21. At this time, there is no problem even if the ECC circuit 32 is in an idle state, but in this embodiment, the ECC circuit 32, which may originally be in an idle state, is also operated when writing an upper half word.
This is intended to perform self-diagnosis of the ECC circuits 31 and 32.

Bit 32 of data zone of system bus 13
The upper half word as write data transferred to the memory controller 30 via the zone position of bit 63 is input to both ECC circuits 31 and 32. The memory controller 30 is an ECC circuit 31
Of course, ECC can also be in an idle state.
The circuit 32 is also operated. As a result, the ECC circuits 31 and 32 generate check bits C for the above half word, which are the same data. The COMP 33 compares the check bits C generated by these ECC circuits 31 and 32 and detects a match/mismatch. If it is clear that they match, the ECC circuits 31, 3
2 is normal, and if they do not match, one of them is diagnosed as a failure. When the ECC circuits 31 and 32 generate check bit C, they add the check bit C to the half word and output it. The memory controller 30 writes the half word outputted from the ECC circuit 31 to which the check bit C is added to the designated address position of the memory array 21. In contrast,
No operation is performed to write the output of the ECC circuit 32. As is clear from this explanation, according to this embodiment, when writing the upper half word, the ECC circuit 31,
32 diagnoses can be made, and the complicated procedure of reading out a whole word (one word) at once and combining it with the half word to be written to write the whole word, as in the conventional example, is not necessary. Only one memory access is required. Note that it is clear that one memory access is sufficient for writing the lower half word.

By the way, in the above embodiment, when reading data,
Diagnosis of ECC circuits 31 and 32 is performed using memory array 2.
Although it has been explained that this is done when only the memory data in 1 is the target of reading,
The present invention can also be applied to a case where only memory data in the memory array 22 is to be read. However, for this purpose, the memory array 21
Means is provided to select either the upper half word and its check bits read from the memory array 22 or the lower half word and its check bits read from the memory array 22 and guide it to the ECC circuit 31, so that only the memory data in the memory array 22 is read. It is necessary to choose the latter if the

Further, in the above embodiment, the case where the memory device is composed of two memory arrays storing half-word memory data has been described, but for example, 1/4 memory data is stored.
It may be configured with four memory arrays that store word memory data or eight memory arrays that store 1/8 memory data. In this case,
It is necessary to use 4 or 8 ECC circuits. In addition,
In the present invention, an ECC circuit diagnostic function during writing is not necessarily required.

〔Effect of the invention〕

As detailed above, according to the ECC circuit diagnosis method of the present invention, when accessing memory for 1/m words,
ECC circuit diagnosis can be performed, improving error resolution.

Further, according to the present invention, when performing a memory write access of 1/m words, there is no need to perform a memory read access of one word prior to the access, thereby improving performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram for explaining zone control for upper half words. 10,30...Memory controller, 11,2
1, 22...memory array, 12, 31, 32...
...ECC circuit, 13...System bus, 33...
Comparison part (COMP).

Claims (1)

[Scope of Claims] A memory device consisting of n memory arrays to which check bits are added in units of 11/n (n is an integer of 2 or more) words, and a memory device provided corresponding to the n memory arrays,
The same number of ECC circuits are used to perform ECC operations on 1/n words, and when accessing memory for 1/m (where m is an integer satisfying m≧n) words, one target
means for performing an ECC operation on a common 1/n word in an ECC circuit other than the ECC circuit; and a comparison unit that compares the ECC operation results of each of the ECC circuits on the common 1/n word, An ECC circuit diagnosis method characterized in that the ECC circuit is diagnosed based on the comparison result of the comparison section when accessing the memory of 1/m words.