JPH04372793A - Memory circuit - Google Patents

Abstract

PURPOSE:To sharply reduce a power consumption by using a transfer gate which is driven and controlled respectively by a word line and a bit line. CONSTITUTION:An FF static memory cell constituted of (p) channel transistors(TR) Q1 and Q3, and (n) channel TR Q2 and Q4, is selected and driven through the series connection TR, that is, TR T1 and T3, and T2 and T4, of the transfer gate whose gate is respectively driven by a word line ML and an antibit line BL, and the word line ML and the bit line BL. Then, at the time of reading the memory cell, when the word line ML is turned to a high potential, and the bit line BL and the antibit line BL are turned to the high potential, the TR T1-T4 a returned to a conduction states, and operating currents are running through the memory cell. Then, as for the other non-selective memory cells connected with a selective word line ML, the bit line BL and the antibit line BL are held to be a low potential, the TR T3 and T4 are turned OFF, and the operating currents are not running through the memory cell. Thus, the power consumption can be sharply reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit used as a static RAM memory cell.

0002

2. Description of the Related Art FIG. 5 is a diagram showing an example of the configuration of a conventional static memory cell using a CMOS flip-flop circuit.

In the figure, a p-channel MOS is connected between a high potential DC constant voltage source Vdd and a low potential DC constant voltage source Vcc.
Transistor (hereinafter referred to as "p transistor")Q
1 and an n-channel MOS transistor (hereinafter referred to as “nMO
It's called "S". ) A flip-flop circuit is constructed by interconnecting the input/output terminals of a CMOS inverter connected to Q2 and a CMOS inverter connected to p transistor Q3 and n transistor Q4. The input/output terminals NA and NB of this flip-flop circuit and the bit lines BL and BL
The n-transistors T1 and T2 connected between the two transistors are driven by the word line WL and function as transfer gates.

In a memory cell having such a configuration, when the word line WL becomes a low potential, both n-transistors T1 and T2 become non-conductive, and the information (potential) set in the flip-flop circuit is held. Here, the word line WL
By raising the potential to a high potential, both n-transistors T1 and T2 become conductive, and an operating current I0 flows from the bit lines BL and BL to the low potential DC constant voltage source Vss in the memory cell, and the memory cell becomes selected and read. will be held.

Furthermore, when inverting (writing) information in a memory cell, by setting the word line WL to a high potential, both n-transistors T1 and T2 are made conductive, and only one of the bit lines BL and BL is set to a high potential. By doing so, the information set in the flip-flop circuit can be inverted. Here, by setting the word line WL to a low potential again and making both the n-transistors T1 and T2 non-conductive, the set information can be held regardless of the states of the bit lines BL and BL.

FIG. 6 is a block diagram showing an example of the overall configuration of a memory cell array in which such memory cells are arranged in rows and columns. In the figure, memory cells MS11 to MS1n are connected to word line WL0, and memory cells MSm1 to MSmn are similarly connected to word line WLm. Furthermore, bit lines BL1 and BL1 are connected to memory cells MS11 to MSm1, and bit lines BLn and BLn are similarly connected to memory cells MS1n to MSmn. Note that the bit lines BL1 and BL1 are in a complementary relationship. A word line drive circuit 61 controls each word line, and a bit line control circuit 62 controls each bit line.

[0007]

By the way, for example, when the word line WL0 is selected and becomes a high potential, the word line WL0
n memory cells MS11 to MS1 connected to L0
A current flows through n. Therefore, the current consumption I of the memory cell array becomes I=nI0, and as the number of memory cells (number of columns n) connected to one word line increases, the power consumption inevitably increases. Note that one memory cell is selected from among the memory cells connected to one word line by selecting each bit line.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory circuit that can reduce power consumption during read/write operations of memory cells constituting a static RAM.

[0009]

Means for Solving the Problems The invention according to claim 1 connects a transfer gate driven and controlled by a word line and a transfer gate driven and controlled by a bit line, and connects a transfer gate driven and controlled by a word line to a transfer gate driven and controlled by a bit line. A feature is that a bit line is connected to the selected flip-flop circuit.

The invention according to claim 2 provides a memory circuit comprising a flip-flop circuit serving as a memory element, and a first transfer gate controlling connection between the flip-flop circuit and a bit line by a word line, The present invention is characterized in that it includes second transfer gates whose gate terminals are driven and controlled by mutually opposite bit lines and which are connected in series to the first transfer gates.

The invention according to claim 3 provides a memory circuit comprising a flip-flop circuit serving as a memory element and a first transfer gate controlling connection between the flip-flop circuit and a bit line. The present invention is characterized in that it includes a second transfer gate that is drive-controlled, and that the first transfer gate is drive-controlled by mutually opposite bit lines via the second transfer gate.

0012

According to the first aspect of the invention, by selecting a memory cell using both a word line and a bit line, only one of the plurality of memory cells connected to the word line can be operated. Note that during selection, the bit line is used as a control line for memory cell selection.

According to the second aspect of the invention, the gate terminal of the first transfer gate is connected to the word line, and the gate terminal of the second transfer gate is connected to the bit line on the opposite side. Memory cells can be selected by both line and bit line logic.

According to the third aspect of the invention, a second transfer gate, the gate terminal of which is connected to the word line, is connected between the gate terminal of the first transfer gate and the mutually opposite bit line. This allows memory cells to be selected based on the logic of both word lines and bit lines.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing the structure of an embodiment of the invention as set forth in claim 2. In the figure, a word line WL, bit lines BL, BL, p transistors Q1, Q3 and n transistors Q2, Q4 forming a flip-flop circuit are shown.
, n-transistor T1 constituting the transfer gate,
T2 is similar to a conventional memory circuit.

The feature of this embodiment is that an n-transistor T3 whose drive is controlled by the bit line BL is connected between the bit line BL and the n-transistor T1, and an n-transistor T3 whose drive is controlled by the bit line BL is connected between the bit line BL and the n-transistor T2. It has a configuration in which an n-transistor T4 whose drive is controlled by a bit line BL is connected. That is, the n-transistors T1 and T2 whose drive is controlled by the word line WL are used as the first transfer gates, and the n-transistors whose drive and control are controlled by the bit lines BL and BL are the first transfer gates.
Transistors T3 and T4 are configured as second transfer gates, and bit lines BL and BL are shared as control lines for selecting memory cells.

First, the read operation of this memory cell will be explained. During standby, the word line WL is set to a low potential,
By setting both the bit lines BL and BL to a low potential, n
Transistors T1, T2, T3, and T4 are all rendered non-conductive, and no operating current flows through the memory cell. Also,
At the time of selection, the word line WL is set to a high potential, and the bit line BL is set to a high potential.
, BL are set to a high potential, all of the n-transistors T1, T2, T3, and T4 become conductive, and an operating current flows through the memory cell.

On the other hand, for memory cells in other columns connected to the same word line WL as the selected memory cell, n transistors T1 and T2 are connected to the word line WL at a high potential.
However, by keeping both bit lines BL and BL at a low potential, n-transistors T3 and T4 become non-conductive, and no operating current flows through the memory cell.

Next, the write operation of this memory cell will be explained. During standby, the word line WL is similarly set to a low potential, and the bit lines BL and BL are also set to a low potential, so that all n-transistors T1, T2, T3, and T4 are rendered non-conductive, and no operating current flows into the memory cell. does not flow. In addition, at the time of selection, by setting the word line WL to a high potential, the n-transistor T1 of the first transfer gate,
By turning on T2 and setting one of the bit lines BL, BL (for example, BL) to a high potential,
The n-transistor (T4) of the second transfer gate connected to the bit line (BL) on the low potential side becomes conductive, and information is written.

On the other hand, for memory cells in other columns connected to the same word line WL as the selected memory cell, the word line WL is at a high potential, but both bit lines BL and BL are at a low potential. Similarly, no operating current flows through the memory cell.

In this way, a memory cell is selected only when the potential of the word line WL is set to a high potential and the potential of at least one of the bit lines BL and BL is set to a high potential. The memory cell can be brought into a non-operating state by setting the potentials of both bit lines BL and BL to a low potential. That is, by using the bit lines BL and BL as memory cell selection control lines during a read operation or a write operation, the power consumption of the entire memory cell array can be suppressed.

[0022] Note that the n-transistors T1, T2, T3, and T4 constituting the transfer gate can also be constructed of p-transistors. In that case, the bit lines BL,
A memory cell is selected only when the potential of at least one of BL and the potential of word line WL are both low, and for other memory cells connected to the same word line WL, the corresponding bit lines are both high. By setting it to a potential, it can be brought into a non-operating state.

FIG. 2 is a diagram showing the relationship between the number of memory cells connected to one word line WL and the current consumption of the entire memory cell array. In the figure, it can be seen that in the conventional configuration, the current consumption increased in proportion to the increase in the number of memory cells, but the configuration of the present invention suppresses this increase.

FIG. 3 is a diagram showing the configuration of a first embodiment of the invention according to claim 3. In the figure, word lines WL,
bit lines BL, BL, p transistors Q1, Q3 and n transistor Q2, which constitute a flip-flop circuit;
Q4, n-transistor T forming the transfer gate
1 and T2 are similar to conventional memory circuits.

The feature of this embodiment is that the n-transistor T3, which is driven and controlled by the word line WL, is connected between the gate terminal of the n-transistor T1 and the bit line BL, and the n-transistor T3 is connected between the gate terminal of the n-transistor T2 and the bit line BL. line BL
It has a configuration in which an n-transistor T4 whose drive is controlled by the word line WL is connected between the word line WL and the word line WL. That is, n-transistors T1 and T2 forming the first transfer gate
is driven and controlled by the bit lines BL, BL via the n-transistors T3, T4 of the second transfer gate, which is driven and controlled by the word line WL, and the bit lines BL,
BL is shared as a control line for selecting memory cells.

First, the read operation of this memory cell will be explained. During standby, the word line WL is set to a low potential,
By setting both the bit lines BL and BL to a low potential, n
Transistors T1, T2, T3, and T4 are all rendered non-conductive, and no operating current flows through the memory cell. Also,
At the time of selection, the word line WL is set to a high potential, and the bit line BL is set to a high potential.
, BL are set to a high potential, all of the n-transistors T1, T2, T3, and T4 become conductive, and an operating current flows through the memory cell.

On the other hand, for memory cells in other columns connected to the same word line WL as the selected memory cell, n transistors T3 and T4 are connected because the word line WL is at a high potential.
However, by keeping both bit lines BL and BL at a low potential, n-transistors T1 and T2 become non-conductive and no operating current flows through the memory cell.

Next, the write operation of this memory cell will be explained. During standby, the word line WL is similarly set to a low potential, and the bit lines BL and BL are also set to a low potential, so that all n-transistors T1, T2, T3, and T4 are rendered non-conductive, and no operating current flows into the memory cell. does not flow. In addition, at the time of selection, by setting the word line WL to a high potential, the n-transistor T3 of the second transfer gate,
By turning on T4 and setting one of the bit lines BL, BL (for example, BL) to a high potential,
The n-transistor (T2) of the first transfer gate connected to the bit line (BL) on the low potential side becomes conductive, and information is written.

On the other hand, for memory cells in other columns connected to the same word line WL as the selected memory cell, the word line WL is at a high potential, but both bit lines BL and BL are at a low potential. Similarly, no operating current flows through the memory cell.

[0030] In this way, in this embodiment as well,
The potential of the word line WL is set to a high potential, and then the potential of the bit line BL is set to a high potential.
, BL is selected only when the potential of at least one of the bit lines BL and BL is set to a high potential, and for other memory cells connected to the word line WL, the potentials of both the bit lines BL and BL are set to a low potential. Can be inactive. That is, by using the bit lines BL and BL as memory cell selection control lines during a read operation or a write operation, the power consumption of the entire memory cell array can be suppressed.

Note that in this embodiment as well, the n-transistors T1, T2, T
3. T4 can also be configured with a p-transistor. In that case, a memory cell is selected only when the potential of at least one of the bit lines BL, BL and the potential of the word line WL are both low potentials, and the memory cell is selected with respect to other memory cells connected to the same word line WL. In this case, the corresponding bit lines can be brought into a non-operating state by setting both the corresponding bit lines to a high potential.

FIG. 4 is a diagram showing the configuration of a second embodiment of the invention according to claim 3. In the figure, in addition to the configuration of the first embodiment shown in FIG. Voltage source V
High resistors Z1 and Z2 are inserted and connected between ss. Therefore, the gate potentials of the n-transistors T1 and T2 during standby can be fixed at a low potential, and the stability of the operation of the present memory circuit can be improved.

Note that the high resistors Z1 and Z2 are not limited to ordinary resistors, but may also be, for example, reversely connected diodes, MOS transistors, or the like. The operation of this embodiment will be explained in exactly the same way as the first embodiment. Also,
Similarly, in this embodiment, the n-transistors T1, T2, T3, and T4 constituting the transfer gate can also be configured with p-transistors. In that case,
The power supply connected to the high resistors Z1 and Z2 is a high potential DC constant voltage source Vdd, and a memory cell is selected only when the potential of at least one of the bit lines BL and BL and the potential of the word line WL are both low potentials. , other memory cells connected to the same word line WL can be brought into a non-operating state by setting the corresponding bit line to a high potential.

Note that the present invention is applicable not only to one-port cells but also to
It can also be applied to 2-port cells and other multi-port cells.

[0035]

As explained above, the present invention uses transfer gates driven and controlled by word lines and transfer gates driven and controlled by bit lines. Cell selection can be made. therefore,
In the memory cell array, there is only one memory cell that consumes current.
It is possible to significantly reduce power consumption.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the invention according to claim 2.

FIG. 2 is a diagram showing the relationship between the number of memory cells connected to one word line WL and the current consumption of the entire memory cell array.

FIG. 3 is a diagram showing the configuration of a first embodiment of the invention according to claim 3.

FIG. 4 is a diagram showing the configuration of a second embodiment of the invention according to claim 3.

FIG. 5 is a diagram showing a configuration example of a conventional static memory cell using a CMOS flip-flop circuit.

FIG. 6 is a block diagram showing an example of the overall configuration of a memory cell array in which memory cells are arranged in rows and columns.

[Explanation of symbols]

Q1, Q3 p-channel MOS transistor (p transistor) Q2, Q4 n-channel MOS transistor (n transistor) T1, T2, T3, T4 n-channel MOS transistor (n transistor) Z1, Z2 High resistor WL Word line BL, BL Bit Line MS Memory cell 61 Word line drive circuit 62 Bit line control circuit

Claims (3)

[Claims] Claim 1: A transfer gate driven and controlled by a word line is connected to a transfer gate driven and controlled by a bit line, and the bit line is connected to a flip-flop circuit selected via both transfer gates. A memory circuit characterized by: 2. A memory circuit comprising a flip-flop circuit serving as a memory element and a first transfer gate controlling connection between the flip-flop circuit and a bit line by a word line, wherein the gate terminals are on opposite sides of each other. A memory circuit comprising second transfer gates each connected in series to the first transfer gate, each of which is driven and controlled by a bit line of the second transfer gate. 3. In a memory circuit comprising a flip-flop circuit serving as a memory element and a first transfer gate controlling connection between the flip-flop circuit and a bit line, a second transfer gate whose drive is controlled by a word line is provided. 1. A memory circuit comprising a transfer gate, wherein the first transfer gate is driven and controlled by mutually opposite bit lines via the second transfer gate.