JPH04367277A - Thin film transistor and manufacture thereof - Google Patents
Thin film transistor and manufacture thereofInfo
- Publication number
- JPH04367277A JPH04367277A JP16899891A JP16899891A JPH04367277A JP H04367277 A JPH04367277 A JP H04367277A JP 16899891 A JP16899891 A JP 16899891A JP 16899891 A JP16899891 A JP 16899891A JP H04367277 A JPH04367277 A JP H04367277A
- Authority
- JP
- Japan
- Prior art keywords
- film
- type
- amorphous silicon
- silicon nitride
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000010408 film Substances 0.000 claims abstract description 79
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000001681 protective effect Effects 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 23
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、薄膜トランジスタおよ
びその製造方法に関し、特にアモルファスシリコンを活
性層とする逆スタガ型の薄膜トランジスタとその製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly to an inverted staggered thin film transistor having an active layer of amorphous silicon and a method for manufacturing the same.
【０００２】0002
【従来の技術】従来のアモルファスシリコン薄膜トラン
ジスタの製造方法を図４を参照して説明する。ガラス基
板１上にクロムを膜厚１４０ｎｍに成膜し、パターニン
グすることによりゲート電極２を形成する。次に、ゲー
ト絶縁膜となる窒化シリコン膜３を膜厚４００ｎｍに、
動作層となるノンドープアモルファスシリコン膜（以下
、ａ−Ｓｉ膜と記す）４を膜厚３００ｎｍに、オーミッ
クコンタクトを得るためのリン（Ｐ）ドープアモルファ
スシリコン膜（以下、ｎ＋型ａ−Ｓｉ膜と記す）５を膜
厚５０ｎｍにそれぞれプラズマＣＶＤ法により成膜し、
素子部以外のアモルファスシリコンを除去する。2. Description of the Related Art A conventional method for manufacturing an amorphous silicon thin film transistor will be described with reference to FIG. A gate electrode 2 is formed by forming a chromium film to a thickness of 140 nm on a glass substrate 1 and patterning it. Next, a silicon nitride film 3 that will become a gate insulating film is formed to a thickness of 400 nm.
A non-doped amorphous silicon film (hereinafter referred to as an a-Si film) 4 serving as an active layer has a thickness of 300 nm, and a phosphorus (P) doped amorphous silicon film (hereinafter referred to as an n+ type a-Si film) for obtaining ohmic contact is used. ) 5 to a film thickness of 50 nm by plasma CVD method,
Amorphous silicon other than the element portion is removed.
【０００３】その後、膜厚２００ｎｍにクロム膜を成膜
し、これをパターニングすることにより、ドレイン電極
６、ソース電極７を形成する。次に、ドレイン電極６、
ソース電極７間のｎ＋ 型ａ−Ｓｉをエッチング除去す
ることにより、両電極の分離を行う。Thereafter, a chromium film is formed to a thickness of 200 nm and patterned to form a drain electrode 6 and a source electrode 7. Next, the drain electrode 6,
By etching away the n+ type a-Si between the source electrodes 7, the two electrodes are separated.
【０００４】次に、ドレイン電極６、ソース電極７間の
、エッチングにより露出したａ−Ｓｉ４の表面、即ち、
バックチャネル部を不動態化するために、プラズマＣＶ
Ｄ法により全面に窒化シリコン膜１１を形成する。Next, the surface of the a-Si4 exposed by etching between the drain electrode 6 and source electrode 7, ie,
Plasma CV to passivate the back channel part
A silicon nitride film 11 is formed on the entire surface by method D.
【０００５】この薄膜トランジスタでは、ドレイン電極
６とソース電極７に対するコンタクト領域としてｎ＋
型ａ−Ｓｉを用いているため、電流は電子の伝導による
ものであり、正孔はコンタクト部でブロックされ、チャ
ネル部には注入されない。[0005] In this thin film transistor, n +
Since type a-Si is used, current is caused by electron conduction, and holes are blocked at the contact portion and are not injected into the channel portion.
【０００６】[0006]
【発明が解決しようとする課題】この従来のアモルファ
スシリコン薄膜トランジスタでは、動作層のａ−Ｓｉが
弱いｎ型半導体であるため、保護膜となる窒化シリコン
中または保護膜上部に正の電荷が存在すると、バックチ
ャネル界面に電子が誘起され、ここがより電子濃度の高
いｎ型に変換される。このためトランジスタのオフ状態
においてもバックチャネル部に電流が流れ、リーク不良
となる。[Problems to be Solved by the Invention] In this conventional amorphous silicon thin film transistor, since the a-Si in the active layer is a weak n-type semiconductor, if positive charges exist in the silicon nitride that serves as the protective film or on the upper part of the protective film, , electrons are induced at the back channel interface, which is converted to n-type with higher electron concentration. Therefore, even when the transistor is in the off state, current flows through the back channel portion, resulting in a leakage defect.
【０００７】[0007]
【課題を解決するための手段】本発明の薄膜トランジス
タは、ゲート電極上にゲート絶縁膜を介してアモルファ
スシリコン層が形成され、該アモルファスシリコン層上
に絶縁性保護膜が形成されたものであって、前記絶縁性
保護膜にはＩＩＩ 族元素がドープされかつ該絶縁性保
護膜下のアモルファスシリコン層の表面がｐ型化されて
いることを特徴としている。[Means for Solving the Problems] A thin film transistor of the present invention includes an amorphous silicon layer formed on a gate electrode via a gate insulating film, and an insulating protective film formed on the amorphous silicon layer. , the insulating protective film is doped with a group III element, and the surface of the amorphous silicon layer under the insulating protective film is p-type.
【０００８】また、その製造方法は、絶縁性基板上にゲ
ート電極を形成する工程と、前記ゲート電極を覆うゲー
ト絶縁膜を形成する工程と、前記ゲート絶縁膜上に活性
層となるアモルファスシリコン層を形成する工程と、Ｉ
ＩＩ 族元素が含まれるプラズマガスにより前記アモル
ファスシリコン層上に絶縁膜を成膜する工程と、熱処理
を行って前記アモルファスシリコン層の表面をｐ型化す
る工程と、を含んでいる。The manufacturing method also includes a step of forming a gate electrode on an insulating substrate, a step of forming a gate insulating film covering the gate electrode, and a step of forming an amorphous silicon layer as an active layer on the gate insulating film. a step of forming I
The method includes a step of forming an insulating film on the amorphous silicon layer using a plasma gas containing a group II element, and a step of performing heat treatment to make the surface of the amorphous silicon layer p-type.
【０００９】[0009]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１は、本発明の第１の実施例を示す断面
図である。同図において、１はガラス基板、２はクロム
からなるゲート電極、３はゲート絶縁膜となる窒化シリ
コン膜、４はａ−Ｓｉ膜、５はｎ＋ 型ａ−Ｓｉ膜、６
、７はそれぞれドレイン電極とソース電極、８は保護膜
となるＢ（ボロン）ドープ窒化シリコン膜、９はａ−Ｓ
ｉ膜４の表面に形成されたｐ型変換層である。Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention. In the figure, 1 is a glass substrate, 2 is a gate electrode made of chromium, 3 is a silicon nitride film serving as a gate insulating film, 4 is an a-Si film, 5 is an n+ type a-Si film, 6
, 7 is a drain electrode and a source electrode, 8 is a B (boron) doped silicon nitride film serving as a protective film, and 9 is an a-S
This is a p-type conversion layer formed on the surface of the i-film 4.
【００１０】次に、本実施例の製造方法について説明す
る。ドレイン電極６、ソース電極７をマスクにｎ＋ 型
ａ−Ｓｉ膜５をエッチング除去してａ−Ｓｉ膜４の表面
を露出させる迄の工程は従来通りであるのでその説明は
省略する。Next, the manufacturing method of this embodiment will be explained. The steps up to etching and removing the n+ type a-Si film 5 using the drain electrode 6 and source electrode 7 as masks to expose the surface of the a-Si film 4 are the same as in the prior art, and therefore their explanation will be omitted.
【００１１】ドレイン電極６−ソース電極７間のａ−Ｓ
ｉ膜４の表面を露出させた後、バックチャネル保護膜と
してＢドープ窒化シリコン膜８を膜厚４０００Åにプラ
ズマＣＶＤ法により成長させる。A-S between drain electrode 6 and source electrode 7
After exposing the surface of the i-film 4, a B-doped silicon nitride film 8 is grown as a back channel protective film to a thickness of 4000 Å by plasma CVD.
【００１２】窒化シリコン膜の代表的な成長条件は、シ
ラン（ＳｉＨ４ ）：アンモニア（ＮＨ３ ）：窒素（
Ｎ２ ）＝１：２：２０の流量比、圧力＝１００Ｐａ、
温度＝２５０℃、パワー密度＝０．１Ｗ／ｃｍ２ であ
るが、本実施例では、これにジボラン（Ｂ２ Ｈ６ ）
を流量比で１０−３程度混合させてＢドープ窒化シリコ
ン膜を成膜した。Typical growth conditions for a silicon nitride film are silane (SiH4): ammonia (NH3): nitrogen (
N2) = 1:2:20 flow rate ratio, pressure = 100 Pa,
Temperature = 250°C, power density = 0.1 W/cm2, but in this example, diborane (B2 H6)
A B-doped silicon nitride film was formed by mixing them at a flow rate ratio of about 10-3.
【００１３】図２は、窒化シリコン膜のＢドーピング特
性を導電率で示したものである（Ｍｕｎｅｋａｔａ ｅ
ｔ．ａｌ，Ｐｒｏｃ． ３ｒｄ Ｐｈｏｔｏｖｏｌｔａ
ｉｃ Ｓｃｉｅｎｃｅ ａｎｄ Ｅｎｇｉｎｅｅｒｉｎ
ｇ Ｍａｙ，１９８２）。同図に示されるように、１０
−３程度Ｂ２ Ｈ６ を混合することにより、窒化シリ
コン膜の導電率は低下し、絶縁膜としての機能は強化さ
れる。FIG. 2 shows the B doping characteristics of the silicon nitride film in terms of conductivity (Munekata et al.
t. al, Proc. 3rd Photovolta
ic Science and Engineering
g May, 1982). As shown in the figure, 10
By mixing approximately -3 B2 H6, the electrical conductivity of the silicon nitride film is reduced and its function as an insulating film is strengthened.
【００１４】Ｂドープ窒化シリコン膜８を成膜した後、
２５０〜３００℃でアニール処理を行うとＢがａ−Ｓｉ
膜４中に拡散し、バックチャネル界面はｐ型に変換され
る。結晶Ｓｉでの不純物拡散は、〜１０００℃程度の高
温処理で達成されるが、アモルファスシリコンの場合は
膜の構造的な不均一性のため、比較的低温で元素の移動
がおこり、上述したアニール処理によってａ−Ｓｉのｐ
型変換が可能である。After forming the B-doped silicon nitride film 8,
When annealing is performed at 250 to 300°C, B changes to a-Si.
It diffuses into the membrane 4 and the back channel interface is converted to p-type. Impurity diffusion in crystalline Si is achieved by high-temperature treatment at ~1000°C, but in the case of amorphous silicon, element migration occurs at relatively low temperatures due to the structural non-uniformity of the film, and the above-mentioned annealing process p of a-Si by treatment
Type conversion is possible.
【００１５】図３は本発明の第２の実施例の断面図であ
る。この実施例を作成するには、ａ−Ｓｉ膜４を成膜し
た後にＢドープ窒化シリコン８を成膜し、バックチャネ
ル保護を行う。この後、バックチャネル部以外のＢドー
プ窒化シリコン８および素子部以外のａ−Ｓｉ膜４を除
去する。FIG. 3 is a cross-sectional view of a second embodiment of the invention. To create this embodiment, after forming the a-Si film 4, B-doped silicon nitride 8 is formed to protect the back channel. Thereafter, the B-doped silicon nitride 8 other than the back channel portion and the a-Si film 4 other than the element portion are removed.
【００１６】次に、ｎ＋ 型ａ−Ｓｉ膜５を成膜し、こ
れをパターニングした後、クロム膜の成膜とそのパター
ニングによってドレイン電極６、ソース電極７を形成し
、さらに保護膜としての窒化シリコン膜１０を形成する
。Next, after forming an n+ type a-Si film 5 and patterning it, a chromium film is formed and patterned to form a drain electrode 6 and a source electrode 7, and a nitride film is further formed as a protective film. A silicon film 10 is formed.
【００１７】この実施例においては、ａ−Ｓｉ膜４の形
成直後にバックチャネル保護膜となるＢドープ窒化シリ
コン膜８を形成するため、ａ−Ｓｉ膜４と窒化シリコン
膜８の界面は、エッチング等のダメージ汚染を受ける履
歴を経ない。そのため、この実施例ではバックチャネル
のｐ型変換の効果が安定して得られる。In this embodiment, since the B-doped silicon nitride film 8 serving as a back channel protective film is formed immediately after the formation of the a-Si film 4, the interface between the a-Si film 4 and the silicon nitride film 8 is etched. No history of damage or contamination. Therefore, in this embodiment, the effect of back channel p-type conversion can be stably obtained.
【００１８】なお、窒化シリコン膜８の成膜工程におい
て、ガスにＢ２ Ｈ６ を混合するのは必ずしも全成膜
工程に渡る必要はなく、成膜工程の初期の段階だけであ
ってもよい。In the process of forming the silicon nitride film 8, it is not necessary to mix B2 H6 into the gas during the entire film forming process, but may be done only at the initial stage of the film forming process.
【００１９】[0019]
【発明の効果】以上説明したように、本発明は、１００
０ｐｐｍ程度にＢを含んだ窒化シリコン膜を薄膜トラン
ジスタのバックチャネル部の保護膜として用い、バック
チャネル界面を弱いｐ型としたものであるので、本発明
によれば、バックチャネルのｎ型変換のしきい値を増加
させ、オフ時のリーク電流を低減させることができる。Effects of the Invention As explained above, the present invention provides 100
According to the present invention, a silicon nitride film containing approximately 0 ppm of B is used as a protective film for the back channel portion of a thin film transistor, and the back channel interface is made into a weak p-type. It is possible to increase the threshold value and reduce leakage current during off-time.
【００２０】また、バックチャネル界面のｐ型化は、プ
ラズマＣＶＤ法による成膜とアニール処理によって達成
するものであるので、特別な工程の追加を伴うことなく
ｐ型化を実現できる。またＢのドーピングがプラズマＣ
ＶＤ装置を用いて行われるものであるため、広い面積に
渡って均等なドーピングを行うことができる。Furthermore, since the back channel interface is made to be p-type by forming a film by plasma CVD and annealing, it is possible to make the back-channel interface p-type without adding any special process. Also, B doping is plasma C
Since it is performed using a VD device, uniform doping can be performed over a wide area.
【図１】 本発明の第１の実施例を示す断面図。FIG. 1 is a sectional view showing a first embodiment of the present invention.
【図２】 窒化シリコン成膜時のガス混合比と導電率
の関係を示すグラフ。FIG. 2 is a graph showing the relationship between gas mixture ratio and conductivity during silicon nitride film formation.
【図３】 本発明の第２の実施例を示す断面図。FIG. 3 is a sectional view showing a second embodiment of the present invention.
【図４】 従来例の断面図。FIG. 4 is a sectional view of a conventional example.
１…ガラス基板、 ２…ゲート電極、 ３
…窒化シリコン膜、 ４…ノンドープアモルファ
スシリコン膜（ａ−Ｓｉ膜）、 ５…Ｐドープア
モルファスシリコン膜（ｎ＋ 型ａ−Ｓｉ膜）、
６…ドレイン電極、 ７…ソース電極、
８…Ｂドープ窒化シリコン膜、 ９…ｐ型変換
層、 １０、１１…窒化シリコン膜。1... Glass substrate, 2... Gate electrode, 3
...silicon nitride film, 4...non-doped amorphous silicon film (a-Si film), 5...P-doped amorphous silicon film (n+ type a-Si film),
6...Drain electrode, 7...Source electrode,
8... B-doped silicon nitride film, 9... p-type conversion layer, 10, 11... silicon nitride film.
Claims (2)
アモルファスシリコン層が形成され、該アモルファスシ
リコン層上に絶縁性保護膜が形成されている薄膜トラン
ジスタにおいて、前記絶縁性保護膜にはＩＩＩ 族元素
がドープされかつ該絶縁性保護膜下の前記アモルファス
シリコン層の表面はｐ型化されていることを特徴とする
薄膜トランジスタ。1. A thin film transistor in which an amorphous silicon layer is formed on a gate electrode via a gate insulating film, and an insulating protective film is formed on the amorphous silicon layer, the insulating protective film containing a group III element. A thin film transistor characterized in that the surface of the amorphous silicon layer under the insulating protective film is doped with p-type.
工程と、前記ゲート電極を覆うゲート絶縁膜を形成する
工程と、前記ゲート絶縁膜上に活性層となるアモルファ
スシリコン層を形成する工程と、ＩＩＩ 族元素が含ま
れるプラズマガスにより前記アモルファスシリコン層上
に絶縁膜を成膜する工程と、熱処理を行って前記アモル
ファスシリコン層の表面をｐ型化する工程と、を含む薄
膜トランジスタの製造方法。2. A step of forming a gate electrode on an insulating substrate, a step of forming a gate insulating film covering the gate electrode, and a step of forming an amorphous silicon layer serving as an active layer on the gate insulating film. , a method for manufacturing a thin film transistor, comprising the steps of: forming an insulating film on the amorphous silicon layer using a plasma gas containing a Group III element; and performing heat treatment to make the surface of the amorphous silicon layer p-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16899891A JPH04367277A (en) | 1991-06-14 | 1991-06-14 | Thin film transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16899891A JPH04367277A (en) | 1991-06-14 | 1991-06-14 | Thin film transistor and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04367277A true JPH04367277A (en) | 1992-12-18 |
Family
ID=15878461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16899891A Pending JPH04367277A (en) | 1991-06-14 | 1991-06-14 | Thin film transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04367277A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5561074A (en) * | 1994-04-22 | 1996-10-01 | Nec Corporation | Method for fabricating reverse-staggered thin-film transistor |
| US5739886A (en) * | 1993-12-20 | 1998-04-14 | Nec Corporation | Liquid crystal display with reverse staggered thin film transistors and opposite electrode, and fabrication method thereof |
| EP1017108A2 (en) * | 1998-12-25 | 2000-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
| US6891236B1 (en) | 1999-01-14 | 2005-05-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| JP2009260044A (en) * | 2008-04-17 | 2009-11-05 | Hitachi Displays Ltd | Display device |
| GB2471128A (en) * | 2009-06-18 | 2010-12-22 | Rec Solar As | Surface passivation of silicon wafers |
| JP2014131052A (en) * | 2008-11-07 | 2014-07-10 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| JP2017168854A (en) * | 2012-06-29 | 2017-09-21 | 株式会社半導体エネルギー研究所 | Manufacturing method for semiconductor device |
-
1991
- 1991-06-14 JP JP16899891A patent/JPH04367277A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5739886A (en) * | 1993-12-20 | 1998-04-14 | Nec Corporation | Liquid crystal display with reverse staggered thin film transistors and opposite electrode, and fabrication method thereof |
| US5561074A (en) * | 1994-04-22 | 1996-10-01 | Nec Corporation | Method for fabricating reverse-staggered thin-film transistor |
| EP1017108A2 (en) * | 1998-12-25 | 2000-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
| EP1017108A3 (en) * | 1998-12-25 | 2001-01-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
| US6891236B1 (en) | 1999-01-14 | 2005-05-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| US7491655B2 (en) | 1999-01-14 | 2009-02-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| JP2009260044A (en) * | 2008-04-17 | 2009-11-05 | Hitachi Displays Ltd | Display device |
| JP2014131052A (en) * | 2008-11-07 | 2014-07-10 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US8980665B2 (en) | 2008-11-07 | 2015-03-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US9231110B2 (en) | 2008-11-07 | 2016-01-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| GB2471128A (en) * | 2009-06-18 | 2010-12-22 | Rec Solar As | Surface passivation of silicon wafers |
| JP2017168854A (en) * | 2012-06-29 | 2017-09-21 | 株式会社半導体エネルギー研究所 | Manufacturing method for semiconductor device |
| US10811521B2 (en) | 2012-06-29 | 2020-10-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US11393918B2 (en) | 2012-06-29 | 2022-07-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
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