JPH0435047A - Forming method for multilayer wiring of semiconductor device - Google Patents

Abstract

PURPOSE:To form a side wall without increasing film-forming process for excluding generation of defective hole opening by a method wherein an open hole reaching a first metal wiring is formed, a second oxide film is formed inside the open hole and on an SOG film, and anisotropic etching is performed for the second oxide film using a mask having an equal open hole diameter to that of a mask used at the time of open hole formation. CONSTITUTION:An open hole 8a is formed while exposing part of a first Al wiring 2. Next, a second oxide film 5 consisting of plasma SiO is formed on the formed open hole 8a and on an SOG film 4 by a plasma CVD method. Next, a positive type resist 11 is stuck, thereon light is selectively irradiated to form a mask having an equal open hole diameter to that of a mask of an open hole forming process. Anisotropic etching is performed by reactive ion etching to form a contact hole 8 provided with a side wall 9 covering the SOG film 4 on the side wall of the open hole 8a.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for forming multilayer interconnections for semiconductor devices, in which contact holes are formed to connect upper and lower interconnects. The present invention relates to a method for forming a multilayer wiring of a semiconductor device, in which the metal wiring is protected from the adverse effects of outgassing from the SOG film by covering the SOG film.

[Conventional technology]

Conventional semiconductor devices, such as bipolar integrated circuits and MO3
In integrated circuits, multilayer wiring is used to achieve high integration density. The formation of multi-layer wiring for such a semiconductor device involves first depositing aluminum on the surface of a semiconductor substrate 1, and then etching it into a predetermined wiring pattern to form a first AN wiring 2, as shown in FIG. do. Next, a first oxide film 3 made of plasma SiO is formed on the semiconductor substrate 1 and the wiring 2 by plasma CVD.

Furthermore, in order to fill in the steps on the first oxide film 3 and planarize the semiconductor substrate, a solution containing a Si compound as a main component is applied onto the first oxide film 3, and then hardened by heat treatment. In this way, an SOG film 4 is formed. Next, a second oxide film 5 made of plasma SiO is formed on this planarized SOG film 4 by plasma CVD.

After the above steps are completed, the first AI! Etching the first and second oxide films 3.5 and SOG film 4 on the wiring 2,
A contact hole 8 is formed by exposing the first Al wiring 2.

Next, aluminum is vapor-deposited in the contact hole 8 formed above to form a second Affi wiring 7, and the first /
1 wiring 2 to form the desired multilayer wiring.

However, in the above-mentioned multilayer wiring formation method, the first A/2 wiring 2 and the second A2 wiring are
AI in contact hole 8 connecting wiring 7! Corrosion of the wiring creates voids and increases contact resistance, causing poor conductivity and deteriorating the yield of semiconductor devices.

Therefore, conventionally, as shown in FIG. 3(b), a sidewall 9 was formed to cover the SOG film exposed on the sidewall of the contact hole 8 to solve the above problem.

Conventionally, the formation of the sidewall is performed using the second AI!, as shown in FIG. 3(a). , After depositing the third oxide film 12 in the contact hole 8 before forming the wiring 7, a mask (not shown) having an opening diameter smaller than that of the mask used to open the contact hole 8 is used. Etching back was performed using a etchant, leaving only the third oxide film 12 on the side wall of the contact hole 8, and forming a sidewall 9 covering the exposed portion of the SOG film 4.

[Problem to be solved by the invention]

However, in the conventional method for forming multilayer wiring for a semiconductor device, there is a problem that the third oxide film 12 needs to be formed, which increases the number of film forming steps and complicates the formation of multilayer wiring.

In addition, using a mask having a smaller aperture diameter than the mask used when forming the contact hole 8, the contact hole 8 is
Since the sidewall 9 is formed on the sidewall of the contact hole 8, the thickness of the sidewall 9 becomes thicker, and the diameter of the contact hole 8 becomes smaller by the thickness of the sidewall 9. For this reason, the cross-sectional area of the contact portion connecting the first An wiring 2 and the second Al wiring 7 becomes small, and the first Al wiring 2
There is also the problem that when the semiconductor device is miniaturized, poor opening of the contact hole 8 occurs, causing conductivity defects in the semiconductor device.

An object of the present invention is to provide a method for forming a multilayer interconnection of a semiconductor device, in which a sidewall is formed without increasing the number of film forming steps, and a hole defect does not occur.

[Means to solve the problem]

In order to achieve the above object, the method for forming multilayer wiring for a semiconductor device of the present invention includes forming a first oxide film so as to cover a first metal wiring formed on a semiconductor substrate; After forming an SOG film by coating and baking a solution containing an St compound as a main component on the film, a contact hole reaching the first metal wiring is formed, and a second metal wiring is formed in the contact hole.
In the method for forming a multilayer interconnection of a semiconductor device, in which the contact hole is formed, an opening reaching the first metal interconnection is formed, and the inside of the opening and the SO
After forming a second oxide film on the G film, anisotropic etching is performed on the second oxide film using a mask having an opening diameter equal to that of the mask used when forming the opening,
The present invention is characterized in that the second oxide film is left only on the sidewall of the opening to form a sidewall that covers the SOG film exposed on the sidewall.

[Effect]

In the method for forming multilayer wiring for a semiconductor device of the present invention, an opening is formed before forming the second oxide film covering the SOG film, and a part of the second oxide film to be formed next is used as a sidewall. In this way, a sidewall is formed without increasing the number of oxide film forming steps. Furthermore, in the formation of the sidewall, SO
In order to cover the G film, the contour I portion of the metal wiring is protected from degassing by the SOG film.

In addition, in order to form the sidewall by etching back the second oxide film using a mask with the same opening diameter as the mask used in the opening formation process, the thickness of the sidewall was made thinner than before. The cross-sectional area of the contact portion of the metal wiring becomes close to the cross-sectional area of the contact portion when no sidewall is formed.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. FIGS. 1(a) to 1(f) are cross-sectional views showing one embodiment of the present invention, showing a part of the manufacturing process of a semiconductor device.

First, to explain the manufacturing process, aluminum is deposited on the semiconductor substrate 1 using a sputtering device, and then the deposited aluminum film is etched into a predetermined wiring pattern by photo-etching to form the first Aff wiring. 2
form.

Next, the substrate 1 and the first
A first oxide film 3 made of plasma SiO is formed on the A2 wiring 2 (see FIG. 1(a)).

Next, Si is deposited on the first oxide film 3 by the SOG method.
After applying an ethanol organic solvent containing a compound as a main component, it is baked at 400°C to form an SOG film 4 made of Sin, thereby filling the steps formed on the surface of the first oxide film 3. , planarize the substrate (see FIG. 1(b)).

Next, the first A! In order to expose a part of the wiring 2 and form the opening 8a, a positive resist 10 is deposited, a mask is formed by selectively irradiating this with light, and the first resist is etched by reactive ion etching. The first oxide film 3 on the AP wiring 2 of
Then, the SOG film 4 is removed to form an opening 8a, and the deposited resist 10 is further removed (see FIG. 1C).

Next, a second oxide film 5 made of plasma SiO is formed on the above-formed openings 8a and the SOG film 4 by plasma CVD (see FIG. 1(d)).

Next, as shown in FIG. 1(d), the first
A contact hole 8 is formed by exposing the surface of the Aj2 wiring 2.
In order to form a positive resist 11, a positive resist 11 is deposited and selectively irradiated with light to form a mask having an aperture diameter equal to that of the mask used in the aperture forming step. By performing directional etching and removing the second oxide film 5 on the first Affi wiring 2 leaving only the second oxide film 5 on the side wall, SOG is formed on the side wall of the opening 8a.
A contact I hole 8 with a sidewall 9 covering the membrane 4 is formed (see FIG. 1(e)).

Next, aluminum is vapor-deposited into the contact hole 8 formed above and etched into a predetermined wiring pattern to form a second A2 wiring 7 (see FIG. 1(f)), and then to the first N wiring. 2 and the second AI wiring 7 are connected to form a multilayer wiring of the target semiconductor device.

By forming a multilayer wiring of a semiconductor device through the above steps, sidewalls can be formed without adding a new oxide film formation step, and the SOG film 4 is exposed on the sidewall of the contact hole 8. A! from degassing from the S○G film 4 because it is covered with the sidewall 9! Protects the contact portion of wiring to prevent conduction defects.

In addition, in the conventional formation of the sidewall 9, the diameter of the contact hole 8 is reduced and the cross-sectional area of the contact portion of the Affi wiring is reduced, which increases the conductive resistance. The second oxide film 5 is etched and hacked using the mask to form the sidewall 9.
By forming the contact hole, the thickness of the sidewall 9 can be reduced, and the diameter of the contact hole does not become so small and the conductive resistance does not change.

In this example, aluminum was used as the metal wiring, but conductive metals such as W, Ti, Mo, or their compounds can also be used.In short, any conductive material that can be deposited on a semiconductor substrate can be used. It's good to have.

Further, in this embodiment, the oxide film 3.5 is formed by plasma CVD, but it may be formed by other known means such as low pressure CVD instead.

Furthermore, in this example, S
Although the SOG film was formed by the OG method, the SOG film may be formed by the SOG method using an inorganic St compound instead.

〔Effect of the invention〕

As explained above, in the method for forming multilayer wiring for a semiconductor device according to the present invention, sidewalls can be formed while reducing the number of oxide film forming steps by one compared to the conventional example, and the sidewalls can form an SOG layer. The coverage of the metal wiring is improved because the metal wiring is protected from
Further, there is an effect that poor conductivity due to degassing from the SOG film is prevented, and wiring with a good yield can be realized.

Further, the sidewall is formed by etching back the second oxide film using a mask having the same opening diameter as the mask used in the opening formation step formed in the previous step. Since the thickness of the contact portion of the first and second metal wirings can be made thinner, the cross-sectional area of the contact portion of the first and second metal wirings can be made to have a diameter close to that in the case where no sidewall is formed, and the conductivity of the contact portion due to the formation of the sidewall can be reduced. It also has the effect of suppressing the increase in resistance.

[Brief explanation of drawings]

FIGS. 1(a) to (f) are cross-sectional views showing the steps of a semiconductor device, FIG. 2 is a cross-sectional view showing a conventional semiconductor device, and FIG.
) is a cross-sectional view showing a contact hole covered with a third oxide film, and FIG. 3(b) is a cross-sectional view showing a conventional semiconductor device equipped with a sidewall. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... First /l wiring, 3...
・First oxide film, 4... SOG film, 5... Second oxide film, 7... Second Affi wiring, 8... Contact hole, 9... Side wall

Claims (1)

[Claims] (1) A first oxide film is formed to cover a first metal wiring formed on a semiconductor substrate, and a solution containing a Si compound as a main component is applied and baked on the first oxide film to form an SOG film. In a method for forming a multilayer wiring for a semiconductor device, in which a contact hole reaching the first metal wiring is formed after forming a contact hole, and a second metal wiring is formed in the contact hole, when forming the contact hole, After forming an opening reaching the first metal wiring and forming a second oxide film within the opening and on the SOG film, apply a mask to the second oxide film that was used when forming the opening. Anisotropic etching is performed using a mask having an opening diameter equal to , and a second oxide film is left only on the sidewall of the opening to form a sidewall that covers the SOG film exposed on the sidewall. A method for forming multilayer wiring in a semiconductor device.