JPH04273442A - Wiring formation - Google Patents

Abstract

PURPOSE:To prevent the oxidation of a formed pattern after dry etching a Cu material layer and improve the reliability on Cu wiring. CONSTITUTION:A Cu layer 2 is dry etched by using NO2 gas, for example, to form a Cu electrode pattern 2a, and oxygen containing layers 2b formed on the side walls of the Cu electrode pattern 2a are reduction removed by plasma process using NH3 gas, etc. An organic polymer layer 4 is formed on the whole plane of a wafer 19 by plasma process using accumulatable gas such as CHF3. Such residual oxygen removal and the polymer passivation prevent the oxidation of the Cu electrode pattern 2a. Such series of processes are continually performed in high vacuum by a device which connects a parallel flat type RIE device with two down flow type plasma processing devices by valves.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a wiring forming method for forming metal wiring made of a copper (Cu)-based material in the field of manufacturing semiconductor devices, etc., and in particular to a method for preventing deterioration in reliability of metal wiring due to oxidation. Regarding.

0002

[Background Art] As semiconductor devices become more highly integrated and performant as seen in VLSI, ULSI, etc. in recent years, the design rules for metal interconnections are becoming smaller to submicron or even quarter micron. There is. Conventionally, metal wiring in semiconductor devices has been made of aluminum (Al
) type materials are the mainstream. However, with Al-based metal wiring, when the design rule becomes finer than 0.5 μm, the reliability of the wiring deteriorates due to electromigration, etc., and the aspect ratio is as large as 1 to 2 due to the need to maintain a low resistance value. Therefore, a series of subsequent processes such as insulating film formation and planarization become difficult to implement. Against this background, wiring formation using Cu-based metal materials is attracting attention. Cu has high electromigration resistance and has a low electrical resistivity of about 1.4 μΩcm, which is only about half that of Al. Therefore, the metal wiring layer can be made thinner without impairing reliability, and the aspect ratio can also be reduced.

[0003] However, the possibility of etching Cu-based materials is still being explored at the research level, and there are many technical problems to be solved before it can be put to practical use. Improving oxidation resistance is one of the above issues. Cu
CuClx is a metal that is extremely easily oxidized, and in order to volatilize and remove CuClx, which has a low vapor pressure and is a reaction product when etching with chlorine-based gas,
The wafer needs to be heated to about 00 to 400°C. Therefore, the surface of the Cu layer is always in a state where a copper oxide film is easily formed even in the presence of a trace amount of oxygen. However, if a copper oxide film is formed on the ion incidence surface during etching, it will cause a decrease in the etching rate. Therefore, for example, Japanese Patent Application Laid-Open No. 1-234578 discloses a technique in which several percent of hydrogen is added to the etching gas to reduce the copper oxide film to pure Cu while etching is performed.

Furthermore, when a copper oxide film is formed on the surface of a pattern made of a Cu-based material, the resistance increases significantly and the reliability of the pattern as a wiring layer is impaired. For example, as stated in Monthly Semiconductor World June 1988 issue, pages 89-93, C.
Oxygen present on the surface of the u pattern diffuses into the inside of the pattern. In other words, in contrast to the aluminum oxide (Al2O3) formed on the surface of the Al-based material layer, which forms a stable passive film with a dense structure, copper oxide does not play the role of a passive film. It is. Therefore, in Japanese Patent Application Laid-open No. 64-71151, after patterning the Cu film and the barrier metal underneath in an etching chamber, the wafer is vacuum transferred from the etching chamber to a sputtering chamber, and the entire surface of the substrate is covered with PSG (phosphorus). A technique of coating with a silicate glass film has been disclosed.

[0005]

However, the technique disclosed in Japanese Unexamined Patent Publication No. 64-71151 has the following problems. As mentioned above, etching the Cu-based material layer requires heating the wafer to a high temperature, so a resist mask cannot be used as an etching mask, and a heat-resistant inorganic mask is used. Even in the above prior art, P
The SG film is used as an etch mask. However, as mentioned in the above publication, this etching mask recedes due to sputtering during etching, and as a result, oxygen is naturally released into the etching system. The released oxygen should easily bond to the surface of the activated Cu film and form an oxide film on the side walls of the wiring pattern. If the entire surface of the base is covered with another PSG film in this state, the oxide film can no longer be removed, causing deterioration of the reliability of the wiring over time. Therefore, an object of the present invention is to provide a method for forming Cu wiring that does not deteriorate over time even after etching.

[0006]

[Means for Solving the Problems] The wiring forming method of the present invention is proposed to achieve the above-mentioned objects.
The method includes a step of etching a Cu-based material layer formed on a substrate to form a predetermined pattern, a step of reducing the side wall surface of the pattern, and a step of coating the entire surface of the substrate with an organic polymer. It is characterized by:

[0007]

[Operation] In the present invention, after etching the Cu-based material layer, the sidewall portions of the formed pattern are reduced. Through this operation, the copper oxide film or reaction products containing oxygen formed on the side wall exposed in the etching process are reduced, and residual oxygen is removed. After that, the entire surface of the substrate is covered with an organic polymer, so even if the processed wafer is taken out into the atmosphere to be transferred to the next process, the pattern made of the Cu-based material layer will be directly exposed to oxygen and moisture in the atmosphere. There is no contact. As described above, according to the present invention, oxidation of the pattern can be effectively prevented by taking a two-step measure of removing residual oxygen on the sidewalls of the pattern and also cutting off contact with oxygen in the atmosphere. Therefore, the reliability of Cu wiring can be improved.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. First, before entering into a description of the etching process, an example of the configuration of an apparatus used in the present invention will be described with reference to FIG.

This apparatus includes a parallel plate type RIE (reactive ion etching) apparatus 10 that performs dry etching of a Cu-based material layer, and a pattern (hereinafter referred to as
This is called a Cu wiring pattern. ) are connected in series through a gate valve, and a first downflow type plasma processing apparatus 20 that performs reduction of the sidewall portion of the A substrate to be processed (wafer) 19 is vacuum-transferred between the two apparatuses.

The parallel plate type RIE apparatus 10 applies an RF electric field between an upper electrode 12 and a wafer mounting electrode 13 which are disposed opposite to each other in an etching chamber 11, and uses plasma generated by discharge. This is designed to etch the Cu-based material layer on the wafer 19. A gas supply pipe 15 is opened in the ceiling of the etching chamber 11 for supplying gas necessary for processing from the direction of arrow B1 in the figure. Furthermore, an exhaust port 16 is opened at the bottom of the etching chamber 11 to exhaust gas in the system in the direction of arrow A1 in the figure in order to remove reaction products and particles generated during processing. ing. The wafer mounting electrode 13 has a built-in heater 14 that can heat the wafer 19 mounted thereon. Further, a blocking capacitor 17 is provided on the wafer mounting electrode 13 to block the DC component.
An RF power source 18 is connected through the RF power source 18, and the configuration is of a cathode coupling type.

The first downflow type plasma processing apparatus 20 guides microwaves generated from a microwave oscillator (not shown) using a rectangular waveguide 21 and a circular waveguide 22, and a microwave introduction window made of quartz. 23 to the plasma generation chamber 24, and is supplied to the plasma generation chamber 24 from the direction of arrow B2 through the gas supply pipe 30. Using plasma generated by decomposing a reducing gas by microwave discharge, the Cu electrode pattern is This is for reducing the side wall portion. A first processing chamber 26 for performing predetermined processing on the wafer 19 is connected to the plasma generation chamber 24 via a mesh electrode 25. This mesh electrode 25 is provided to trap charged particles in plasma. Therefore, the first processing chamber 2
Only neutral active species such as radicals are drawn out as a downward flow (downflow) to the 6 side, allowing processing to be performed with less damage. The processing chamber 26 has an exhaust port 29
is evacuated to a high vacuum by a vacuum system (not shown),
The wafer stage 2 has a built-in heater 28 inside it.
It accommodates 7. The wafer 19 is placed on this wafer stage 27 so as to face the mesh electrode 25 . The first processing chamber 26 is connected to the etching chamber 11 of the parallel plate type RIE apparatus 10 via a second gate valve 53, and both chambers 1
The wafer 19 is vacuum-transferred between the wafers 1 and 26.

The second downflow type plasma processing apparatus 40 has almost the same configuration as the first downflow type plasma processing apparatus 20 described above, and includes a rectangular waveguide 41, a circular waveguide 42, and a micro waveguide. Wave introduction window 43, plasma generation chamber 4
4, a mesh electrode 45, a second processing chamber 46, a wafer stage 47, an exhaust port 48, a gas supply pipe 49, and the like. In this device, an organic polymer deposition gas supplied through a gas supply pipe 49 from the direction of arrow B3 is decomposed in a plasma generation chamber 44 by microwave discharge.
Radicals are drawn into the second processing chamber 46 through the mesh electrode 45, and a radical polymerization reaction is performed on the surface of the wafer 19 placed on the wafer stage 47, thereby forming an organic polymer. At this time, since a low temperature is advantageous for organic polymer deposition, unlike the first downflow type plasma processing apparatus 20, the wafer stage 47 of this apparatus does not have a built-in heater. The second processing chamber 46 is connected to the first processing chamber 26 of the first down-flow plasma processing apparatus 20 via a third gate valve 54, and there is a gap between the two chambers 26, 46. The wafer 19 is transferred under vacuum.

Furthermore, in the front stage of the parallel plate type RIE apparatus 10, a load chamber 50 equipped with a loading cassette 51 for storing a plurality of wafers 19 at once and a wafer transport mechanism (not shown) is connected to a first gate. They are connected via a valve 52. Further, at the rear stage of the second downflow type plasma processing apparatus 40, there is a fourth unloading chamber 56 equipped with an unloading cassette 57 for storing a plurality of wafers 19 at once and a wafer transport mechanism (not shown). are connected via a gate valve 55. According to this apparatus configuration, the wafer 19 is transferred from the load chamber 50 to the parallel plate type RIE apparatus 10 to perform dry etching of the Cu-based material layer, and then transferred to the first downflow type plasma processing apparatus 20. The wafer is subjected to a series of operations in which the sidewalls of the pattern are reduced, then transported to the second downflow plasma processing apparatus 40 to deposit an organic polymer, and finally transported to the unloading chamber 56. 1
9 can be carried out continuously without exposing to the atmosphere. In the following example, an actual process example using the above etching apparatus will be explained with reference to FIGS. 1(a) to 1(d).

First, as shown in FIG. 1(a), a Cu layer 2 is deposited on the entire surface of an interlayer insulating film 1 made of silicon oxide by a method such as sputtering, and then a heat-resistant etching mask 3 is formed. were selectively formed. here,
As the etching mask 3 above, we used a SiN film that can be formed at a relatively low temperature by plasma CVD and patterned using a resist mask and a CF4/O2 mixed gas. A silicone mask may also be used.

Next, the above-mentioned wafer 19 is subjected to parallel plate type RI.
The wafer 19 was set on the wafer mounting electrode 13 of the E apparatus 10 and heated to about 150° C. using the heater 14. In this state, as an example, NO2 flow rate is 50SCCM, gas pressure is 6.7 Pa (50 mTorr), and RF power density is 0.4.
Cu layer 2 under the condition of 5W/cm2 (13.56MHz)
etched. This etching of a Cu-based material layer using NO2 was previously proposed by the present inventor in Japanese Patent Application No. 2-9729.
This was proposed in the specification of No. 5, and even if the heating temperature of the wafer is 200°C or less, Cu is converted into copper nitrate Cu (NO
x )y (mainly x=3, y=2) can be efficiently sublimated and removed. This method has a high selectivity to the mask pattern and the underlying interlayer insulating film because there are no halogen-based active species, and also prevents the formation of copper oxide because the wafer is heated at a relatively low temperature. It has the advantage of being less. As a result of this etching, as shown in FIG. 1(b), C
A u-electrode pattern 2a was formed. However, at this time C
An oxygen-containing layer 2b was formed on the side wall surface of the u-electrode pattern 2a. This oxygen-containing layer 2a is mainly made of copper oxide, which is formed by the direct reaction between oxygen-based active species generated in the etching reaction system by discharge decomposition of NO2 and the side wall portion of the Cu electrode pattern 2a. However, it also includes copper nitrate and the like adsorbed on the sidewalls of the pattern.

Next, the wafer 19 is transferred to the first downflow type plasma processing apparatus 20 via the second gate valve 53 and set on the wafer stage 27.
It was heated to 300°C using a heater 28. In this state, as an example, NH3 flow rate is 100SCCM, gas pressure is 100P.
The oxygen-containing layer 2b was reduced under the conditions of a (700 mTorr) and a microwave current of 400 mA. In this process, hydrogen-based active species generated by discharge decomposition of NH3 were drawn into the first processing chamber 26, and the copper oxide formed on the side wall of the Cu electrode pattern 2a was reduced to pure Cu. At the same time, H and N produced by the discharge decomposition of NH3 combine with some of the dangling bonds produced during the reaction, producing hydrides and nitrides (both not shown). did. In any case, as shown in FIG. 1(c), the Cu electrode pattern 2
Residual oxygen on the surface of the side wall portion a was almost completely removed.

Next, the wafer 19 was transferred to the second downflow type plasma processing apparatus 40 via the third gate valve 54 and set on a wafer stage 47. In this state, as an example, CHF3 flow rate is 90SCCM.
, a gas pressure of 106 Pa (0.8 Torr), and a microwave current of 400 mA. In this process, C
CHFx*,C generated by discharge decomposition of HF3
Radicals such as Fx* were drawn into the second processing chamber 46 and radical polymerization occurred on the surface of the wafer 19. As a result, as shown in FIG. 1(d), the wafer 1
The entire surface of 9 was covered with an organic polymer layer 4.

In the wafer 19 that has gone through each of the above processes, residual oxygen has been removed and the surface is covered with the organic polymer layer 4, so even if it is taken out into the atmosphere, no carbon
No deterioration of the u wiring pattern 2a occurred. The organic polymer layer 4 is left on the wafer 19 until immediately before the next step in order to cut off contact with oxygen and moisture in the atmosphere. The organic polymer layer 4 can be easily dissolved and removed, for example, by immersing the wafer 19 in an organic solvent such as acetone immediately before forming an interlayer insulating film over the entire surface of the wafer 19.

It should be noted that the present invention is not limited to the above-mentioned embodiments. For example, as an etching gas for etching the Cu layer 2, in addition to the above-mentioned NO2, NO, NO2, N2O, etc. can be used. Nitrogen oxide or N2/O
2 Mixed gas etc. may be used. Alternatively, conventionally known chlorine gases may be used, such as BCl3 /Cl2 system, Cl2 /HCl system, Cl2 /HCl/BCl3
Examples include chlorine-based mixed gases such as chlorine-based gases. These chlorine-based mixed gases have dilution effects, sputtering effects,
A rare gas such as He or Ar may be added as appropriate to provide a cooling effect or the like. In addition to the above-mentioned NH3, H2 is used as the gas for reducing the side wall portion of the Cu electrode pattern 2a.
, CH4, etc. can be used. As the deposition gas for forming the organic polymer, the above-mentioned C
In addition to HF3, saturated fluorocarbon gases such as CH2 F2 and CH3 F, C2 F4, C2 H2 F
Unsaturated fluorocarbon gases such as 2, C3 F6, C3 H2 F4, etc. can be used. When using these fluorocarbon gases, in order to prevent the occurrence of undercuts etc. due to excessive F*,
It is desirable to select a compound with a /C ratio of 2 or less. Especially when using unsaturated fluorocarbon gas,
Efficient organic polymer formation can be expected by promoting radical polymerization reactions. Or CH4, C2 H6,
A saturated or unsaturated hydrocarbon gas such as C2H4 may also be used. Furthermore, the structure of the wiring part to which the present invention can be applied is not limited to the case where the Cu-based material layer is formed alone as in the above-mentioned embodiment, but for example, the structure of the wiring part is not limited to the case where the Cu-based material layer is formed alone.
It may be formed using a barrier metal such as a base metal. However, in this case, the Ti-based barrier metal cannot be etched with the nitrogen oxide-based gas mentioned above, so it is necessary to switch the etching gas to a chlorine-based gas or the like during the process.

[0020]

As is clear from the above description, according to the present invention, it is possible to prevent a pattern made of a Cu-based material layer from being oxidized after etching, making it possible to form highly reliable wiring. Therefore, the present invention is extremely effective in improving the reliability of wiring in a semiconductor device having high performance and high degree of integration.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing an embodiment of the wiring forming method of the present invention according to the process order, in which (a) shows the state of the wafer before etching, and (b) shows the state of the wafer containing oxygen in the side wall of the Cu electrode pattern. (c) shows the state in which the layer has been formed, (c) shows the state in which the side wall portion of the Cu electrode pattern has been reduced, and (d) shows the state in which the entire surface of the wafer is covered with the organic polymer layer.

FIG. 2 is a schematic cross-sectional view showing an example of the configuration of an apparatus used to carry out the wiring forming method of the present invention.

[Explanation of symbols]

1...Interlayer insulating film 2...Cu layer 2a...Cu electrode pattern 2b
...Oxygen-containing layer 3 ...Etching mask 4
...Organic polymer layer 10...
-Parallel plate type RIE apparatus 11...Etching chamber 13...Wafer mounting electrodes 14, 28...Heater 19...Wafer 20...First downflow type plasma processing apparatus 26... First processing chamber 27, 47
...Wafer stage 40 ...Second downflow type plasma processing apparatus

Claims (1)

[Claims] 1. A step of etching a copper-based material layer formed on a substrate to form a predetermined pattern, a step of reducing the side wall surface of the pattern, and a step of coating the entire surface of the substrate with an organic polymer. A wiring forming method characterized by comprising the steps of: