JPH04245346A - Microcomputer system - Google Patents

Abstract

PURPOSE:To access an odd and an even address at the same timing and to eliminate the need to consider the allocation address of data at the time of software generation. CONSTITUTION:This system consists of a microprocessor 11 which has 16-bit data bus width and a 1st memory 12 and a 2nd memory 13 which have 8-bit data bus width; and the 1st memory is stored with data corresponding to odd addresses and the 2nd memory is stored with data corresponding to even addresses. The microprocessor outputs an access signal to the 1st and 2nd memories at the same time when attaining 16-bit access to the odd addresses, and the 2nd memory uses the value, obtained by adding one to an address outputted by the microprocessor by an address incrementer 20, as an address. A 16-bit bus cycle is completed in a single bus cycle, so word access to the odd addresses can be performed by single-time memory access.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer system comprising a microprocessor having a bus width of 16 bits and a memory.

0002

2. Description of the Related Art Generally, when a memory is connected to a microprocessor having a bus width of 16 bits, the bus width is usually 8 bits so that the microprocessor can perform both 8-bit and 16-bit accesses to the memory. A configuration is used in which two memories with different widths are connected to the microprocessor so that the two memories store data corresponding to even addresses of data corresponding to odd addresses, respectively. When this microprocessor performs 8-bit access to memory, it accesses only one memory, and when it performs 16-bit access, it accesses both memories at the same time. It realizes two types of memory access: 16-bit access and 16-bit access.

FIG. 6 shows the configuration of a conventional microcomputer system consisting of a microprocessor and memory having a bus width of 16 bits. This microcomputer system includes a microprocessor 11 and an upper memory 12.
and a lower memory 13.

From this microprocessor 11 to the upper memory 12 and lower memory 13, there is an address bus 14 that specifies the address when the microprocessor 11 performs memory access, and a memory access bus 14 that specifies the address when the microprocessor 11 performs memory access. A read/write signal (hereinafter referred to as
It is written as R/W signal. )17 is output.

The microprocessor 11, upper memory 12, and lower memory 13 are connected to an upper data bus 15 and a lower data bus 1, which are 8-bit wide buses that transfer data between the microprocessor and the memory during memory access.
6 are connected to each other.

Furthermore, from the microprocessor 11 to the upper memory 12 and the lower memory 13, the microprocessor 11 outputs data to the data bus at the timing of reading data on the data bus when reading the memory or when writing the data to the memory. Upper data strobe signal (hereinafter referred to as UDS), which is a strobe signal that specifies the timing to
signal) 18, lower data strobe signal (hereinafter referred to as L
DS signal) 19 is output, and when the microprocessor 11 accesses the upper memory 12, the UD signal is output.
When the S signal 18 accesses the lower memory 12, it becomes L.
The DS signal 19 becomes an active low level.

The upper memory 12 and lower memory 13 are shown in FIG.
As shown in the figure, addresses are assigned in 8-bit units, with odd addresses being assigned to the upper memory 12 side, even addresses being assigned to the lower memory 13 side, and so on. Inside the memory, the lowest bit of the address output by the microprocessor 11 is removed, and the value halved is used as the internal address.

In this microcomputer system, for example, when the microprocessor 11 performs an 8-bit access (hereinafter referred to as byte access) to the even address 2000, the microprocessor 11 inputs the address 2000 to the address bus 14. is output, and the LDS signal 19 is activated. Since the LDS signal 19 is active in the lower memory 13, an access is made to internal address 1000, which is halved from address 2000, and as a result, address 2000 is accessed.
Byte access to the address is realized.

Similarly, when the microprocessor 11 performs a byte access to address 2001, which is an odd address, the microprocessor 11 outputs the address 2001 to the address bus 14 and outputs the UDS signal 1.
Activate 8. Since the UDS signal 18 is active in the upper memory 12, access is made to internal address 1000, and byte access to address 2001 is realized.

Further, when the microprocessor 11 performs a 16-bit access (hereinafter referred to as word access) to address 2000, which is an even address, the microprocessor 11 sends the address 2000 to the address bus 14.
It outputs address 0 and makes the UDS signal 18 and LDS signal 19 active at the same time. Since the UDS signal 18 and LDS signal 19 are active in the upper memory 12 and lower memory 13, respectively, the internal address 1000, which is 1/2 of the address 2000, is accessed.
As a result, word access to address 2000 is realized.

However, when performing a word access to the odd address 2001, the microprocessor 11 outputs the address 2001 to the address bus 14 in the same way as when word access is performed to an even address, and the UDS signal 18 and LDS If signal 19 is activated at the same time, there will be no problem since internal address 1000 will be accessed on the upper memory 12 side, but internal address 1 will be accessed on the lower memory 13 side.
Address 000, that is, address 2000, is accessed, and address 2002, which should originally be accessed, is not accessed.

In order to avoid this, as shown in the timing chart of FIG. 8, in the conventional microprocessor 11, when performing a word access to an odd address, the memory access is divided into two byte accesses. 1
In the second memory access, the address 2001 is output on the address bus 14, and the UDS signal 18 is activated, and in the second access, the address 2002, which is the address added by "1" to the original address, is output on the address bus 14. and makes the LDS signal 19 active. In the first memory access of the upper memory 12, since the address is 2001 and the UDS signal 18 is active, the internal address 1000 is accessed. In the lower memory 13, in the second memory access, the address is 2002 and the LDS signal 19 is active, so the internal address 1001 is accessed, resulting in a word access.

[0013]

[Problems to be Solved by the Invention] In the above-mentioned conventional microprocessor having a bus width of 16 bits, when performing a word access to an odd address, the word access is performed in two byte accesses. It takes twice as long as normal memory access. As a result, when word accesses to odd addresses are frequently used, the performance of the microcomputer system is degraded.

[0014] The purpose of the present invention is to eliminate such drawbacks,
The object of the present invention is to provide a microcomputer system that reduces memory access time and improves performance.

[0015]

Means for Solving the Problems The present invention has a configuration including a microprocessor having a data bus width of 16 bits, a first memory device connected to the microprocessor, and a first memory device each having a data bus width of 8 bits. 2 memory devices, the first memory device stores data corresponding to odd addresses, and the second memory device stores data corresponding to even addresses, the microprocessor comprising: , outputs an access signal to each of the first and second memory devices at the same time when executing a 16-bit access to the odd address, and the second memory device has an address incremented by the address incremented by the microprocessor. It is characterized in that a 16-bit bus cycle to an odd address is performed in one bus cycle by using the value added by 1 as an address.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a first embodiment of the present invention. In contrast to the conventional example, this microcomputer system simultaneously activates the UDS signal 18 and LDS signal 19 when the microprocessor 11 refers to a word to an odd address, thereby converting the word reference to an odd address into one memory access. address bus 1 as the input address to the lower memory 13.
An address incrementer 20 is added that inputs a value obtained by adding "1" to the address above.

The operation of this microcomputer system during memory access will be explained using the timing charts of FIGS. 2 and 3. Figure 2(a) shows an even number address 200.
12 is a timing chart when a byte access is made to address 0. FIG.

The microprocessor 11 outputs the address 2000 to the address bus 14, and also outputs the LDS
The signal 19 is set to active low level. At this time, the address incrementer 20 adds "1" to the address and outputs address 2001 as an input address to the lower memory 13. In the lower memory 13, the LDS signal 19
is active, access is made to internal address 1000 for input address 2001. As a result, access to address 2000 is performed.

FIG. 2(b) is a timing chart when a byte access is made to the odd address 2001. The microprocessor 11 outputs the address 2001 to the address bus 14, and also outputs the UDS signal 1.
Set 8 to low level, which is access. Upper memory 12
Here, since the UDS signal 18 is active, access is made to the internal address 1000 for the input address 2001. As a result, address 200
Access to address 1 is made.

FIG. 3(a) is a timing chart when a word access is made to an even number address 2000. The microprocessor 11 outputs the address 2000 to the address bus 14 and also outputs the UDS signal 1.
8. Both LDS signals 19 are set to active low level. In the upper memory 12, since the UDS signal 18 is active, access is made to the internal address 1000 for the input address 2000. In addition, since the LDS signal 19 is active in the lower memory 13, the internal address 1 for the address 2001 incremented by the address incrementer 20
Access to address 000 is made. As a result,
The memories corresponding to addresses 2000 and 2001 are accessed to realize word access.

FIG. 3(b) is a timing chart when a word access is made to the odd address 2001. The microprocessor 11 outputs the address 2001 to the address bus 14, and also outputs the UDS signal 1.
8. Both LDS signals 19 are set to active low level. In the upper memory 12, since the UDS signal 18 is active, access is made to the internal address 1000 for the input address 2001. Further, the address 2002, which has been incremented by "1" by the address incrementer 20, is input to the lower memory 13. Since the LDS signal 19 is active in the lower memory 13, the internal address 1001 is accessed from the input address 2002. As a result, the memories corresponding to addresses 2001 and 2002 are accessed to realize word access.

By adding the address incrementer 20 to the input to the lower memory in this way, a word reference to an odd address can be made in one memory access.

FIG. 4 is a block diagram of a second embodiment of the invention. In the first embodiment, the address incrementer 20 that adds "1" to the address input to the lower memory performs the addition of "1" to all bits of the address, whereas in the present embodiment, the address incrementer 20a In this case, it is only necessary to add "1" to a predetermined number of lower bits of the address. Here, the description will be made assuming that the number of bits for performing the address incrementer is 3 bits.

This microcomputer system has the microprocessor 11 shown in FIG. 1 check the value of the lower three bits of the address, and if all the bits are "1" and "1" is added to the address, the lower three bits are A carry detection circuit 21 is added which detects a condition in which a carry occurs from a bit to an upper bit, and outputs "1" when a carry occurs, and outputs "0" in other cases.

When the microprocessor 11a accesses a word at an odd address, the output of the carry detection circuit 21 becomes "
1", 2" as in the conventional microprocessor.
Execute memory access divided into 1 times memory access,
When the output of the carry generation circuit 21 is “0”, the first
Similar to the microprocessor shown in the embodiment, the modification is made so that a word access to an odd address is performed in one memory access, and addition of "1" to an address by the address incrementer 20a is performed only for a predetermined number of lower bits. I am changing it to do this.

[0026] In this microcomputer system,
When byte access or word access is made to an even address, the address is an even number, so the operation is the same as in the first embodiment. In addition, since the LDS signal does not become active during byte access to an odd address, the input address to the lower memory 13 is not related to the operation, so it is not affected by this change, and the operation is the same as the first embodiment. Become.

The operation of this microcomputer system when accessing a word to an odd address is shown in FIGS. 5(a) and 5(a).
This will be explained using the timing chart in (b).

FIG. 5(a) is a timing chart when a word reference is made to address 1. bottom 3
Since the bit is "001", the carry detection circuit 21 outputs "0". Since the output of the carry generation circuit 21 is "0", the microprocessor outputs the address 1 on the address bus 14 and outputs the UDS as in the case of FIG. 3(b) of the first embodiment. Both signal 8 and LDS signal 19 are set to active low level.

In the upper memory 12, since the UDS signal 18 is active, access is made to internal address 0 for input address 1. Further, the lower memory 13 has an address incrementer 20a.
Address No. 2 with the bit added by "1" is input. Since the LDS signal 19 is active in the lower memory 13, access is made to the internal address 1 for the input address 2. As a result, the memories corresponding to addresses 1 and 2 are accessed to realize word access.

FIG. 5(b) is a timing chart when a word reference is made to address number 7. bottom 3
Since the bit is "111", the carry detection circuit 21 outputs "1". Since the output of the carry generation circuit 21 is "1", the microprocessor 11a divides the memory access into two byte accesses and executes it, similar to the word access to an odd address in a conventional microprocessor. In the first memory access, the address 7 is output on the address bus 14 and the UDS signal 18 is activated, and in the second access, the address 8 is added to the original address 7 and "1" is added. is output onto the address bus 14 and the LDS signal 19 is activated.

In the upper memory 12, since the UDS signal 18 is active at address 7 in the first memory access, the corresponding internal address 3 is accessed. At this time, address 0, which is the value obtained by adding "1" to address 7 using only the lower three bits, is input to the lower memory 13, but since the LDS signal 19 is inactive, no access to address 0 occurs. . In the second memory access in the lower memory 13, the address incrementer 20a inputs address 9, which is obtained by adding "1" to the lower three bits of address 8 on the address bus 14. Since the LDS signal 19 is active, access to internal address 4 corresponding to address 9 is performed. As a result, addresses 7 and 8 are accessed, and word access is realized.

In this way, when the method described in this embodiment is adopted, the lower three bits of the address are "001" and "01".
1" and "101", a word access to an odd address is performed in one access, and the lower three addresses of the address are
When the bit is "111", word access to an odd address is performed in two accesses. As a result, on average, 3/4 of memory accesses to odd addresses are
This can be done with one memory access. Further, since the bit width for addition in the address incrementer 21 can be limited to the lower several bits, the address incrementer can be easily created.

In this embodiment, the bit width for adding "1" to an address is set to 3 bits, but this bit width can be set to any value.

[0034]

Effects of the Invention As explained above, the present invention enables word access to an odd numbered address to be performed in one time, whereas conventional microcomputer systems required two memory accesses.
Since this can be done with one memory access, the performance of the microcomputer system can be improved.

Furthermore, since odd and even addresses can be accessed at the same timing, there is no need to worry about data allocation addresses when creating software, reducing the burden on software developers and improving software productivity. Can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcomputer system according to a first embodiment of the present invention.

[Fig. 2] Timing chart of the operation of the microcomputer system of the embodiment shown in Fig. 1.

[Figure 3] Timing chart of the operation of the microcomputer system similar to Figure 2

FIG. 4 is a block diagram of a microcomputer system according to a second embodiment of the present invention.

[Fig. 5] Timing chart of the operation of the microcomputer system of the embodiment shown in Fig. 4.

[Figure 6] Block diagram of an example of a conventional microcomputer system

[Figure 7] Diagram showing address allocation to upper memory and lower memory in Figure 6

[Figure 8] Timing chart of the operation of the microcomputer system in Figure 6

[Explanation of symbols]

11, 11a Microprocessor 12
Upper memory 13 Lower memory 14 Address bus 15 Upper data bus 16 Lower data bus 17 R/W signal 18 UDS signal 19 LDS signal 20, 20a Address incrementer 21
Carry detection circuit

Claims (1)

[Claims] 1. A microprocessor comprising a microprocessor having a data bus width of 16 bits, and a first memory device and a second memory device respectively connected to the microprocessor and each having a data bus width of 8 bits; In a computer system in which a first memory device stores data corresponding to an odd numbered address and a second memory device stores data corresponding to an even numbered address, the microprocessor stores data corresponding to the odd numbered address.
When executing a 6-bit access, an access signal is simultaneously output to each of the first and second memory devices;
The memory device adds 1 to the address output by the microprocessor using an address incrementer, thereby adding 1 to the address output by the microprocessor.
A microcomputer system characterized by performing a 6-bit bus cycle in one bus cycle.