JPH04239767A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory which has high performance and prevents deterioration of memory characteristic due to a soft error, etc. CONSTITUTION:A single memory cell is formed of a switching transistor having an n<+> type impurity diffused layer 4 to become a drain to be formed on the sidewall of an island region 3, a gate insulating film 5, a gate electrode 6 to become a word line and an n<+> type impurity diffused layer 7 to become a source to be formed on the region 3, and a capacity having storage electrodes 8, 10 formed on the region 3, a capacitor insulating film 11 and a plate electrode 12, and each cell is electrically insulated.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention is particularly applicable to dynamic
The present invention relates to a semiconductor memory device having a novel device structure that increases the density of a memory cell array of a random access memory.

0002

2. Description of the Related Art Conventionally, a "one transistor/one capacitor" type memory cell consisting of one transistor and one capacitor has a small number of element components and the cell area can be easily reduced. It is widely used as a memory cell for high-density DRAM (dynamic random access memory).

In particular, in order to meet the demand for further miniaturization of devices, it has been proposed to make the structures of capacitors and switching transistors three-dimensional (
References: K. Sunouchi et al.
Surrounding Gate Transit
tor Cell for 64/256 Mbit
DRAMs”IEDM Technical Dige
st. 1989. pp23-26. ). FIG. 5 is a cross-sectional view showing the configuration of a conventional semiconductor memory device.

In FIG. 5, 101 is a p-type semiconductor substrate, 101a is a groove formed in the semiconductor substrate 101, and 101 is a groove formed in the semiconductor substrate 101.
b is an island region, 102 is an n+ type impurity diffusion layer which becomes the drain of the switching transistor formed on the surface of the island region 101b, and 103 is an n- type impurity diffusion layer which becomes the source of the switching transistor formed on the side wall of the groove 101a. An impurity diffusion layer, 104 is a gate insulating film formed on the side wall of the trench 101a, 105 is a word line forming a gate electrode formed on the gate insulating film 104 at the top of the trench 101a, and 106 is an n+ drain. 107 is a capacitor insulating film formed on the side wall of the trench 101a, and 108 is the trench 10.
This is a plate electrode formed inside 1a. Also, 1
09 is a p+ type impurity diffusion layer for preventing leakage current between memory cells, and 110 and 111 are interlayer insulating films.

As shown in FIG. 5, the conventional semiconductor memory device has an n+ type impurity diffusion layer 102 which serves as a drain formed on the surface of an island region 101b of a semiconductor substrate 101, and an n+ type impurity diffusion layer 102 formed on the side wall of the island region 101b. The n-
A switching transistor consisting of a type impurity diffusion layer 103, a gate insulating film 107, and a gate electrode 105 serving as a word line, and an n-type transistor formed on the side wall of the island region 101b.
+ type impurity diffusion layer 102, capacitor insulating film 107
and a capacitor section consisting of a plate electrode 108.

As described above, in the conventional semiconductor memory device, the capacitor and the switching transistor are connected to the trench 101.
It is three-dimensionally formed inside a.

[0007]

However, in the conventional semiconductor memory device, the capacitor section consisting of the plate electrode 108, the capacitor insulating film 107, and the n- type impurity diffusion layer 103 formed opposite to the plate electrode 108 is , exists inside the groove 101a formed in the semiconductor substrate 1. As a result, the capacitor section that constitutes a conventional semiconductor memory device is
The n-type impurity diffusion layer 103 is affected by leakage current generated in the semiconductor substrate 1 due to crystal defects, or α particles obtained in the semiconductor substrate 1 generate electrons and holes, and the noise charges are generated in the n- type impurity diffusion layer 103. There is a problem in that memory characteristics deteriorate due to soft errors that occur due to the depletion layer that has spread in the vicinity and enters the capacitor insulating film 107.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a high-performance semiconductor memory device that prevents deterioration of memory characteristics due to soft errors and the like.

[0009]

Means for Solving the Problems A semiconductor memory device according to claim 1 includes: a groove formed in a semiconductor substrate of a first conductivity type; an island region formed of a part of the semiconductor substrate surrounded by the groove; a first semiconductor layer of a second conductivity type forming a source formed on the top of the island region; a storage electrode formed on the first semiconductor layer; a capacitor insulating film formed on the surface of the storage electrode; A plate electrode formed on the capacitor insulating film, a second semiconductor layer of a second conductivity type forming a drain formed under the side wall of the island region, and a gate insulating layer formed on the side wall of the island region. The semiconductor device includes a film, a gate electrode formed on the gate insulating film and serving as a word line, and a bit line electrically connected to the second semiconductor layer.

A semiconductor memory device according to a second aspect of the present invention is the semiconductor memory device according to the first aspect, wherein the bit line is made of a conductive film formed at the bottom of the trench. A semiconductor memory device according to a third aspect of the invention is the semiconductor memory device according to the first or second aspect, characterized in that the storage electrode is made of conductor layers that are stacked with parts electrically connected to each other.

[0011]

[Function] According to the structure of the present invention, a capacitor portion consisting of a storage electrode, a capacitor insulating film, and a plate electrode is provided on the island region, and the first semiconductor layer of the second conductivity type is provided as a source. , a switching transistor comprising a second semiconductor layer of a second conductivity type serving as a drain, a gate insulating film, and a gate electrode serving as a word line is provided on the side wall portion of the island region, that is, inside the trench. Therefore, the capacitor insulating film constituting the capacitor section is located at a position apart from the semiconductor substrate, and thus signal charges can be stored in the capacitor insulating film apart from the semiconductor substrate.

Furthermore, according to the second aspect of the present invention, by using the conductive film formed at the bottom of the groove as the bit line electrically connected to the second semiconductor layer of the second conductivity type which becomes the drain. , a bit line with reduced wiring resistance can be obtained. Furthermore, according to the third aspect of the present invention, the storage electrode is made of conductive layers that are partially electrically connected and laminated. Therefore, the surface area of the storage electrode can be expanded, thereby increasing the storage capacity.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing the structure of a semiconductor memory device according to a first embodiment of the present invention, and FIG. 2 is a plan view showing the structure of the same semiconductor memory device. Note that FIG. 1 is I-I' in FIG.
FIG. In Figures 1 and 2, 1
is a p-type semiconductor substrate, 2 is a groove formed in the semiconductor substrate 1,
3 is an island region consisting of a part of the semiconductor substrate 1 surrounded by the groove 2; 4 is an n+ type impurity diffusion layer forming a drain formed at the lower part of the side wall of the island region 3; 5 is a side wall of the island region 3. 6 is a gate electrode formed on the gate oxide film 5 and serves as a word line; 7 is an n+ type impurity diffusion layer that serves as a source and is formed on the island region 3 of the semiconductor substrate 1. . In this way, the switching transistor is composed of the n+ type impurity diffusion layer 4 as the drain, the gate insulating film 5, the gate electrode 6 as the word line, and the impurity diffusion layer 7 as the source formed on the upper part of the island region.
It exists in the groove 2 formed in the semiconductor substrate 1, that is, on the side wall of the island region 3, and has a vertical structure.

Reference numerals 8 and 10 are storage electrodes formed on the n+ type impurity diffusion layer 7 which serves as a source, and these storage electrodes 8 and 10 are formed by laminating conductor layers (parts of which are electrically connected). For example, a polysilicon film, etc.). In addition, the storage electrodes 8 and 10 are n+ type impurity diffusion layers 7 that serve as sources.
is electrically connected to. 9, 11 are storage electrodes 8, 10
This is a capacitor insulating film formed on the surface of the capacitor, and is made of an ONO film or the like. 12 is a plate electrode formed on the capacitor insulating films 9 and 11, and is made of a polysilicon film or the like.

As described above, the capacitive portion consisting of the storage electrodes 8 and 10, the capacitor insulating film 11 and the plate electrode 12 exists on the island region 3 which is a part of the semiconductor substrate 1, and the capacitor insulating film 11 is located on the island region 3 which is a part of the semiconductor substrate 1. It exists at a position far from 1. A single memory cell consists of an n+ type impurity diffusion layer 4 formed on the side wall of the island region 3 as a drain, a gate insulating film 5, a gate electrode 6 as a word line, and a source formed on the top of the island region 3. A switching transistor consisting of an n+ type impurity diffusion layer 7, storage electrodes 8, 10 formed on the island region 3, and a capacitor insulating film 1.
1 and a capacitive part consisting of a plate electrode 12,
Each memory cell is electrically insulated by groove 2.

Note that 13 is an insulating film formed at the bottom of the trench 2, and 14 is an impurity diffusion layer of the same conductivity type (p type) as the semiconductor substrate 1 formed at the bottom of the trench 2, to prevent leakage current. . 15 is an insulating film filled in the groove 2, and 16 is an interlayer insulating film formed on the plate electrode 12. Further, bit lines 17 electrically connect the n+ type impurity diffusion layers forming the drains of each memory cell.

A method of manufacturing the semiconductor memory device of the first embodiment will now be briefly described. A groove 2 is formed in a semiconductor substrate 1 by anisotropic etching. At this time, a part of the semiconductor substrate 1 surrounded by the groove 2 becomes an island region 3. next,
After forming an insulating film (not shown) inside the trench 2 by CVD or the like, the insulating film at the bottom of the trench 2 is removed. Next, an n+ type impurity diffusion layer 4 serving as a drain and a bit line 17 are formed by ion implantation or solid phase diffusion such as SOG. Next, after removing the insulating film formed on the sidewalls of the island region 3, that is, the sidewalls of the trench 2, thermal oxidation is applied to the trench 2.
A gate insulating film 5 and an insulating film 13 are formed on the side walls and bottom of the
Further, LP-CV is formed on this gate insulating film 5.
By depositing a polysilicon film using the D method etc.
A gate electrode 6 that will become a word line is formed. Next, an n+ type impurity diffusion layer 7, which will serve as a source, is formed on the surface of the island region 3 by ion implantation. After filling the inside of the trench 2 with an insulating film 15 by depositing an insulating film on the surface,
The surface is flattened by an etch-back method or the like.

Next, an opening window is formed in the insulating film 15 on the island region 3, a polysilicon film is deposited on this opening window by LP-CVD method, etc. The storage electrode 8 is formed by diffusing an impurity of the same conductivity type (n type) as the impurity diffusion layer. This storage electrode 8 is electrically connected to an n+ type impurity diffusion layer 7 which serves as a source. Next, an insulating film (not shown) is deposited on the storage electrode 8 by CVD or the like. After forming a contact hole in the insulating film by etching this insulating film using a resist pattern, a polysilicon film is deposited on the contact hole by LP-CVD method, etc. The storage electrode 10 is formed by diffusing an impurity of the same conductivity type (n type) as that of the n- type impurity diffusion layer. As a result, the storage electrodes 8 and 10 have a multilayer structure, increasing their surface area. Next, after removing the insulating film remaining on the surface, a capacitor insulating film 11 is formed on the surfaces of the storage electrodes 8 and 10 by thermal oxidation or CVD. Thereafter, a polysilicon film is deposited on this capacitor insulating film 11 by LP-CVD or the like to form a plate electrode 12, thereby completing the formation of the memory cell.

FIG. 3 is a sectional view showing the structure of a semiconductor memory device according to a second embodiment of the invention, and FIG. 4 is a plan view showing the structure of the semiconductor memory device. Note that FIG. 3 shows II-I in FIG.
It is a sectional view taken along I' line. Further, the same reference numerals as in the first embodiment are given the same reference numerals, and the explanation thereof will be omitted. In FIG. 3, 22 is an insulating film formed at the bottom of the groove 2 and the lower part of the side wall of the island region 3, and 23 is an insulating film formed on the insulating film 22 and electrically connected to the n+ type impurity diffusion layer 4 which becomes the drain. This is a bit line and is made of a conductive film such as a polysilicon film, polycide, and metal. A bit line made of this conductive film has a lower resistance than a bit line made of an impurity diffusion layer. Further, 24 is an insulating film formed on the bit line 23 to electrically insulate the gate electrode 6 and the bit line 23.

Similar to the first embodiment, n becomes the drain.
A switching transistor consisting of a + type impurity diffusion layer 4, a gate insulating film 5, a gate electrode 6 serving as a word line, and an impurity diffusion layer 7 forming a source formed on the top of an island region is placed in a groove 2 formed in a semiconductor substrate 1. That is, it exists on the side wall portion of the island region 3 and has a vertical structure. In addition, the capacitive part consisting of the storage electrodes 8 and 10, the capacitor insulating film 11, and the plate electrode 12 exists on the island region 3 consisting of a part of the semiconductor substrate 1, and in particular, the capacitor insulating film 11 is located away from the semiconductor substrate 1. exist in position.

A method of manufacturing the semiconductor memory device of the second embodiment will now be briefly described. In the same manner as in the first embodiment, a groove 2 and an island region 3 are formed in a semiconductor substrate 1, and an n+ type impurity that will become a drain is diffused into the side wall of the island region 3 by ion implantation or solid phase diffusion of SOG or the like. Form layer 4. After forming an insulating film 22 on the bottom of the groove 4 and the lower part of the side wall of the island region 3, a bit line 23 electrically connected to the n+ type impurity diffusion layer 4, which will become the drain, is formed on the insulating film 22. Form. This bit line 23 is made of a conductive film such as a polysilicon film in which impurities are diffused, polycide, and metal. Next, after forming an insulating film 24 on the bit line 23 by CVD or the like, a gate insulating film 5 is formed on the side wall of the trench 2, that is, on the side wall of the island region 3, by thermal oxidation. Then, a gate electrode 6 that will become a word line is formed on this gate insulating film 5. Thereafter, in the same manner as in the first embodiment, an n+ type impurity diffusion layer 7 serving as a source, an insulating film 15, storage electrodes 8, 10, a capacitor insulating film 11, and a plate electrode 12 are formed, and a memory cell is formed. finish.

According to the first and second embodiments described above,
A switching transistor consisting of an n+ type impurity diffusion layer 4 serving as a drain, a gate insulating film 5, a gate electrode 6 serving as a word line, and an impurity diffusion layer 7 forming a source formed on the top of an island region is formed on a semiconductor substrate 1. A capacitive part that exists within the groove 2, that is, on the side wall of the island region 3, and is made up of the storage electrodes 8, 10, the capacitor insulating film 11, and the plate electrode 12, is located on the island region 3 that is a part of the semiconductor substrate 1. exist. Therefore, the capacitor insulating film 11 constituting the capacitive part is located at a distance from the semiconductor substrate 1. Thereby, it is possible to obtain a semiconductor memory device having a capacitor portion that is less susceptible to leakage current generated in the semiconductor substrate 1 and has high soft error resistance.

[0023]

According to the semiconductor memory device of the present invention, a capacitor portion consisting of a storage electrode, a capacitor insulating film, and a plate electrode is provided on an island region, and a capacitor portion of a second conductivity type serving as a source is provided. 1 semiconductor layer, the second layer becomes the drain
A switching transistor including a second conductive semiconductor layer, a gate insulating film, and a gate electrode serving as a word line is provided on the side wall of the island region, that is, inside the trench. Therefore, it is possible to significantly increase the density of cells two-dimensionally, and signal charges can be stored in a capacitor section that is remote from the semiconductor substrate. As a result, it is possible to obtain a high-performance semiconductor memory device that prevents deterioration of memory characteristics due to soft errors and the like.

Further, according to the semiconductor memory device according to the second aspect, the conductive film formed at the bottom of the trench is used as the bit line electrically connected to the second semiconductor layer of the second conductivity type which becomes the drain. As a result, a bit line with reduced wiring resistance can be obtained. Furthermore, according to the semiconductor memory device according to the third aspect of the present invention, the storage electrode is made of conductor layers that are stacked and partially electrically connected. Therefore, the surface area of the storage electrode can be expanded, thereby increasing the storage capacity.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the configuration of a semiconductor memory device according to a first embodiment of the invention.

FIG. 2 is a plan view showing the configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 3 is a sectional view showing the structure of a semiconductor memory device according to a second embodiment of the invention.

FIG. 4 is a plan view showing the configuration of a semiconductor memory device according to a second embodiment of the invention.

FIG. 5 is a cross-sectional view showing the configuration of a conventional semiconductor memory device.

[Explanation of symbols]

1 Semiconductor substrate 2 Groove 3 Island region 4 n+ type impurity diffusion layer (second conductivity type second
) 5 Gate insulating film 6 Gate electrode 7 N+ type impurity diffusion layer (second conductivity type first semiconductor layer) 5 Gate insulating film 6 Gate electrode 7
) 8, 10 Storage electrode 9 Capacitor insulating film 17, 24 Bit line

Claims (3)

[Claims] 1. A groove formed in a semiconductor substrate of a first conductivity type, an island region consisting of a part of the semiconductor substrate surrounded by the groove, and a second island region forming a source formed on the island region.
a first conductive semiconductor layer, a storage electrode formed on the first semiconductor layer, a capacitor insulating film formed on the surface of the storage electrode, a plate electrode formed on the capacitor insulating film, a second semiconductor layer of a second conductivity type forming a drain formed under the side wall of the island region; a gate insulating film formed on the side wall of the island region; and a word line formed on the gate insulating film. A semiconductor memory device comprising a gate electrode and a bit line electrically connected to the second semiconductor layer. 2. The semiconductor memory device according to claim 1, wherein the bit line is made of a conductive film formed at the bottom of the trench. 3. The semiconductor memory device according to claim 1, wherein the storage electrode is formed of conductor layers stacked with parts electrically connected to each other.