JPH04196434A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04196434A JPH04196434A JP32804790A JP32804790A JPH04196434A JP H04196434 A JPH04196434 A JP H04196434A JP 32804790 A JP32804790 A JP 32804790A JP 32804790 A JP32804790 A JP 32804790A JP H04196434 A JPH04196434 A JP H04196434A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- plating
- bump
- film layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052802 copper Inorganic materials 0.000 abstract description 9
- 239000010949 copper Substances 0.000 abstract description 9
- 229910052804 chromium Inorganic materials 0.000 abstract description 8
- 239000011651 chromium Substances 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 238000002161 passivation Methods 0.000 abstract description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 6
- 239000010931 gold Substances 0.000 abstract description 6
- 229910052737 gold Inorganic materials 0.000 abstract description 6
- 238000007747 plating Methods 0.000 abstract description 6
- 238000010884 ion-beam technique Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/1354—Coating
- H01L2224/1356—Disposition
- H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
- H01L2224/13565—Only outside the bonding interface of the bump connector
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置の製造方法に関するものであり、特
に外部接続端子であるバンプ型電極を有する半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a semiconductor device having bump-type electrodes that are external connection terminals.
［従来の技術］
従来、半導体装置のバンプ型電極に関しては、数多くの
提案がなされ改良が加えられている。[Prior Art] Conventionally, many proposals have been made and improvements have been made regarding bump-type electrodes for semiconductor devices.
第２図は、従来のバンプ電極の断面図である。FIG. 2 is a cross-sectional view of a conventional bump electrode.
従来はアルミ電極バッド２１及びパッシベーション膜２
２の上に、密着金属膜層であるクロム膜２３、拡散バリ
ア層であるｆｆ４ｇ２４、そしてその上に金メツキ部２
５という構造をとっていた。この様な構造にて形成され
たバンプ型電極は、クロム膜２３や、銅膜２４が大気に
晒されているために、高湿度の雰囲気で使用した場合、
クロム膜２３や銅膜２４が腐食するといった問題があっ
た。Conventionally, aluminum electrode pad 21 and passivation film 2
2, a chromium film 23 which is an adhesion metal film layer, ff4g 24 which is a diffusion barrier layer, and on top of that a gold plating part 2.
It had a structure of 5. Since the bump-type electrode formed with such a structure has the chromium film 23 and the copper film 24 exposed to the atmosphere, when used in a high humidity atmosphere,
There was a problem that the chromium film 23 and the copper film 24 were corroded.
［発明が解決しようとする課題］
本発明は、クロム膜や銅膜が腐食するという課題を解決
しようとするもので、高湿度雰囲気で使用しても腐食し
ないように、密着金属膜層、拡散バリア膜層及びバンプ
部側面を絶縁膜て被覆することにより、高信頼性半導体
装置を提供することにある。[Problems to be Solved by the Invention] The present invention attempts to solve the problem that chromium films and copper films corrode. An object of the present invention is to provide a highly reliable semiconductor device by covering a barrier film layer and a side surface of a bump portion with an insulating film.
［課題を解決するための手段］
集積回路の電極パッド上及び絶縁膜上に形成されるバン
プ型電極において
１）密着金属膜層、拡散バソア襄層及びバング部を絶縁
族で覆う工程
２）異方性エツチングにより、密着金属膜層、拡散バリ
ア膜層及びバンプ部側面に絶縁膜を残し、バンプ部上面
を露出させる工程。[Means for Solving the Problems] In bump type electrodes formed on electrode pads and insulating films of integrated circuits, 1) step of covering the adhesion metal film layer, diffused bathoa layer and bang portion with an insulating group 2) different A step in which the top surface of the bump is exposed by directional etching, leaving an insulating film on the adhesion metal film layer, diffusion barrier film layer, and side surfaces of the bump.
から成ることを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, comprising:
［実施例］
以下に、本発明について製造方法の実施例に基ずき詳細
に説明をする。[Example] The present invention will be described in detail below based on an example of a manufacturing method.
第１図にある様に、本発明の電極様台バンプは、アルミ
電極パッド１１及びパッシベーション膜１４から成る集
積回路上に形成する。As shown in FIG. 1, the electrode-like platform bump of the present invention is formed on an integrated circuit consisting of an aluminum electrode pad 11 and a passivation film 14.
アルミ電極パッド１１及びパッシベーション躾１２との
密着性を得るためのクロムｌ！１３及び銅膜１４をスパ
ッタリング法を用いてそれぞれ０．１μｍ、０．５μｍ
厚で形成する。次に、２０μｍ以上の膜厚のフォトレジ
ストパターンを用いて、メツキ部１５を電解メツキ法に
より２０μｍ厚になるように形成する。次にメツキ部１
５をマスクとして、銅膜１４、クロム膜１３をイオンビ
ームエツチング法を用いてエッチ除去すると、第１図（
ａ）の構造となる。次に、プラズマＴＥｏＳ法を用いて
絶縁膜層１６（シリコン酸化膜）を２μｍ厚となる様、
全面に形成する。次にＣＨＦ３ガスを用いたドライエツ
チング法または、Ａｒガスを用いたイオンビームエツチ
ングにより、前記絶縁膜層１６を除去し、メツキ部１５
の上面が露出したところで、エツチング操作を中止する
と第１図（ｃ）の構造となり、本発明の半導体装置の製
造は終了する。Chromium for adhesion to the aluminum electrode pad 11 and passivation pad 12! 13 and copper film 14 to 0.1 μm and 0.5 μm, respectively, using a sputtering method.
Form thick. Next, using a photoresist pattern having a thickness of 20 μm or more, the plating portion 15 is formed to have a thickness of 20 μm by electrolytic plating. Next, the plating part 1
5 as a mask, the copper film 14 and chromium film 13 are etched away using the ion beam etching method, as shown in FIG.
The structure is a). Next, using the plasma TEoS method, the insulating film layer 16 (silicon oxide film) was formed to a thickness of 2 μm.
Form on the entire surface. Next, the insulating film layer 16 is removed by dry etching using CHF3 gas or ion beam etching using Ar gas, and the plated portion 15 is removed.
When the etching operation is stopped when the upper surface of the semiconductor device is exposed, the structure shown in FIG. 1(c) is obtained, and the manufacturing of the semiconductor device of the present invention is completed.
［発明の効果］
本発明は、半導体装置の電極用金バンプの製造方法に関
するもので、密着金属膜層、拡散バリア裏層及びバンプ
部側面を絶縁族で被覆する製造方法を用いることにより
、高湿度雰囲気で使用しても各薄膜が腐食することなく
、高い信頼性の金バンプ電極を得ることができた。さら
に、使用電圧も従来より高く、より有用で使用性が高い
ばかりか、簡単で生産性の高い製造方法を実現すること
ができた。[Effects of the Invention] The present invention relates to a method for manufacturing gold bumps for electrodes of semiconductor devices, and by using a manufacturing method in which the adhesion metal film layer, the diffusion barrier back layer, and the side surfaces of the bump portions are coated with an insulating group, high performance can be achieved. Even when used in a humid atmosphere, each thin film did not corrode and a highly reliable gold bump electrode could be obtained. Furthermore, the operating voltage is higher than before, making it not only more useful and easier to use, but also a simple and highly productive manufacturing method.
第１図（ａ）〜（Ｃ）は、本発明の実施例による半導体
装置製造方法の断面図。
第２図は、従来の半導体装置製造方法の断面図。
１１・・・アルミ電極パッド
１２・・・パッシベーション膜
１３・・・クロム膜層
１４・・・銅膜層
１５・・・メツキ部
１６・・・絶縁Ｍ（シリコン酸化Ｍ）
２１・・・アルミ電極パッド
２２・・・パッシベーション膜
２３・・・クロム膜層
２４・・・銅膜層
２５・・・メツキ部
以上
出願人 セイコーエプソン株式会社FIGS. 1A to 1C are cross-sectional views of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a conventional semiconductor device manufacturing method. 11... Aluminum electrode pad 12... Passivation film 13... Chrome film layer 14... Copper film layer 15... Plated portion 16... Insulation M (silicon oxide M) 21... Aluminum electrode Pad 22... Passivation film 23... Chrome film layer 24... Copper film layer 25... Plated portion and above Applicant: Seiko Epson Corporation
Claims (1)
ンプ型電極において ａ）密着金属膜層、拡散バリア膜層及びバンプ部を絶縁
膜で覆う工程 ｂ）異方性エッチングにより、前記密着金属膜層、前記
拡散バリア膜層及び前記バンプ部側面に絶縁膜を残し、
前記バンプ部上面を露出させる工程から成ることを特徴
とする半導体装置の製造方法。[Claims] In a bump type electrode formed on an electrode pad and an insulating film of an integrated circuit, a) a step of covering an adhesion metal film layer, a diffusion barrier film layer, and a bump portion with an insulating film b) anisotropic etching by leaving an insulating film on the adhesion metal film layer, the diffusion barrier film layer, and the side surface of the bump part,
A method for manufacturing a semiconductor device, comprising the step of exposing the upper surface of the bump portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32804790A JPH04196434A (en) | 1990-11-28 | 1990-11-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32804790A JPH04196434A (en) | 1990-11-28 | 1990-11-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04196434A true JPH04196434A (en) | 1992-07-16 |
Family
ID=18205922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32804790A Pending JPH04196434A (en) | 1990-11-28 | 1990-11-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04196434A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6232563B1 (en) * | 1995-11-25 | 2001-05-15 | Lg Electronics Inc. | Bump electrode and method for fabricating the same |
| US6958539B2 (en) * | 2000-08-29 | 2005-10-25 | Au Optronics Corporation | Metal bump with an insulating sidewall and method of fabricating thereof |
-
1990
- 1990-11-28 JP JP32804790A patent/JPH04196434A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6232563B1 (en) * | 1995-11-25 | 2001-05-15 | Lg Electronics Inc. | Bump electrode and method for fabricating the same |
| US6958539B2 (en) * | 2000-08-29 | 2005-10-25 | Au Optronics Corporation | Metal bump with an insulating sidewall and method of fabricating thereof |
| US7041589B2 (en) * | 2000-08-29 | 2006-05-09 | Au Optronics Corp. | Metal bump with an insulating sidewall and method of fabricating thereof |
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