JPH04111334A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04111334A JPH04111334A JP23225290A JP23225290A JPH04111334A JP H04111334 A JPH04111334 A JP H04111334A JP 23225290 A JP23225290 A JP 23225290A JP 23225290 A JP23225290 A JP 23225290A JP H04111334 A JPH04111334 A JP H04111334A
- Authority
- JP
- Japan
- Prior art keywords
- measuring
- small
- measured
- chip
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000005259 measurement Methods 0.000 claims abstract description 46
- 238000012360 testing method Methods 0.000 abstract description 18
- 239000000523 sample Substances 0.000 abstract description 16
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 1
- 238000013100 final test Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に関し、特に被測定項目毎に最
適なテスト条件を得ることのできる半導体装置に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device that can obtain optimal test conditions for each item to be measured.
第２図は従来普通に行われているＩＣチップのチップ状
態における電気的特性の測定（以下ウェハテストと称す
）を行う様子を示す図であり、図において、ｌはＩＣチ
ップ、２，２ｂは電極パッド、３は電極パッド２に接触
して電気信号を伝達するプローブ針、４は電気信号を伝
送する信号ケーブル、６． ７． ８はＩＣＣチップ上
電気的特性を測定する測定系であり、該測定系６． ７
． ８は普通その用途や仕様が全く異なるか、あるいは
類似のものである。また、５は１つのＩＣＣチップ上複
数の測定系６． ７． ８間で電気信号を仲介して切替
えるマルチプレクサである。FIG. 2 is a diagram showing how to measure the electrical characteristics of an IC chip in its chip state (hereinafter referred to as a wafer test), which is conventionally commonly performed. In the figure, l is an IC chip, and 2 and 2b are electrode pad; 3 is a probe needle that contacts the electrode pad 2 and transmits an electrical signal; 4 is a signal cable that transmits an electrical signal; 6. 7. 8 is a measurement system for measuring the electrical characteristics on the ICC chip; 7
．． 8 are usually completely different or similar in their uses and specifications. Further, 5 is a plurality of measurement systems 6 on one ICC chip. 7. This is a multiplexer that mediates electrical signals to switch between 8 and 8.
次に動作について説明する。Next, the operation will be explained.
ＩＣチップｌ上に形成された電気回路は電極パッド２を
介して測定系Ａ６等と電気的に接続される。例えば、Ｉ
ＣＣチップ上ある種の電気的特性を測定する場合を想定
する。この特性を測定する最適または測定可能な測定系
か測定系Ａ６とすれば、マルチプレクサ５は信号ケーブ
ル４と測定系Ａ６とを接続する様に動作する。通常、こ
のマルチプレクサ５は例えばリレーマトリックスの様な
機能を有していて電気信号を切替える。従って、当該Ｉ
Ｃチップｌについて別の種類の電気的特性を測定する場
合には、マルチプレクサ５を切替えることにより、別の
測定系、例えば測定系Ｂ７で測定できる。但し、マルチ
プレクサ５によって測定系へ６と測定系Ｂ７とは切替え
ることかできても、プローブ針３及び信号ケーブル４は
同一のものを使用している。The electric circuit formed on the IC chip 1 is electrically connected to the measurement system A6 etc. via the electrode pad 2. For example, I
Assume that a certain type of electrical characteristic on a CC chip is to be measured. If the measurement system A6 is an optimal or measurable measurement system for measuring this characteristic, the multiplexer 5 operates to connect the signal cable 4 and the measurement system A6. Normally, this multiplexer 5 has a function such as a relay matrix, and switches electrical signals. Therefore, the I
When measuring another type of electrical characteristic for the C chip I, by switching the multiplexer 5, the measurement can be performed using another measurement system, for example, measurement system B7. However, although the measurement system 6 and the measurement system B7 can be switched by the multiplexer 5, the same probe needle 3 and signal cable 4 are used.
従来の半導体装置は以上のように構成されているので、
ＩＣチップの各種電気的特性を測定するに際しては、い
くつかの必要な測定系をマルチプレクサを切替えて、使
い分けなければならず、また上記ＩＣチップと上記マル
チプレクサとを結ぶプローブ針及び信号ケーブルは同一
のものを使わなければならないので、被測定項目によっ
て測定系を切替えて使い分けるので測定に要する時間が
かかり、また上記マルチプレクサの信頼性或いは測定に
及ぼす影響を考慮せねばならず、またプローブ針や信号
ケーブルが被測定項目や測定系にとって必ずしも最適な
ものとすることか極めてむずかしく、良好なテスト条件
を得るのか困難である等の問題点かあった。Conventional semiconductor devices are configured as described above, so
When measuring various electrical characteristics of an IC chip, it is necessary to use several necessary measurement systems by switching multiplexers, and the probe needles and signal cables that connect the IC chip and the multiplexer must be the same. Since the measurement system must be switched and used depending on the item to be measured, it takes time to complete the measurement, and the reliability of the multiplexer and its effect on the measurement must be taken into consideration. There have been problems such as it is extremely difficult to make the test conditions optimal for the item to be measured and the measurement system, and it is difficult to obtain good test conditions.
この発明は上記のような問題点を解消するためになされ
たもので、ＩＣチップの被測定項目のもつ特性を考慮し
てそれに見合う良好なテスト条件を得ることのできる半
導体装置を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and its purpose is to provide a semiconductor device that can take into account the characteristics of the item to be measured on an IC chip and obtain good test conditions commensurate with the characteristics. shall be.
この発明に係る半導体装置は、集積回路の所定の端子に
ついて、１つの端子に対して２つ以上設けられた電極パ
ッドを備え、該２つ以上のパッドの各々を異なる電気的
特性を測定する全く別の測定系との媒介として用いるよ
うにしたものである。The semiconductor device according to the present invention includes two or more electrode pads provided for one terminal with respect to a predetermined terminal of an integrated circuit, and a semiconductor device that measures different electrical characteristics for each of the two or more pads. It is designed to be used as an intermediary with another measurement system.
この発明においては、集積回路の所定の端子について、
１つの端子に対して２つ以上設けられた電極パッドを備
え、該２つ以上のパッドの各々を異なる電気的特性を測
定する全く別の測定系との媒介として用いるようにした
から、上記２つ以上の電極パッドを被測定項目の特性や
種類に応じて使い分けることにより、これにより良好な
テスト条件を得ることができる。In this invention, for a predetermined terminal of an integrated circuit,
Two or more electrode pads are provided for one terminal, and each of the two or more pads is used as an intermediary with a completely different measurement system that measures different electrical characteristics. By using three or more electrode pads depending on the characteristics and type of the item to be measured, it is possible to obtain good test conditions.
以下、この発明の一実施例を図について説明する。第１
図は本発明の実施例における複数電極パッドの使い分け
によるテスト状態を示す図であり、図において、第２図
と同一符号は同−又は相当部分を示し、また２ａは電極
パッド２と同一端子から取り出されている電極パッド、
３ａはプローブ針、４ａは信号ケーブルである。なお、
プローブ針３，３ａ及び信号ケーブル４，４ａはその仕
様や用途は異なっていてもよ（、測定系Ａ６及び測定系
Ｂ７もその仕様や用途が異なっていてもよい。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a diagram showing a test state by selectively using multiple electrode pads in an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 2 indicate the same or corresponding parts, and 2a is from the same terminal as the electrode pad 2. The electrode pad being taken out,
3a is a probe needle, and 4a is a signal cable. In addition,
The probe needles 3, 3a and the signal cables 4, 4a may have different specifications and uses (and the measurement systems A6 and B7 may also have different specifications and uses).
次に動作について説明する。Next, the operation will be explained.
ある任意の回路端子を取り出す電極パッド２及び電極パ
ッド２ａを配しこれら各パッド２，２ａに各々プローブ
針３及びプローブ針３ａを当て、信号ケーブル４及び信
号ケーブル４ａを介して測定系６，７へ到る場合におけ
る一つの例として、ＩＣチップ１の電極パッド２，２ａ
を介し微少電流（例えばμＡオーダー）と大電流（例え
ば数１００ｍＡオーダー）とを測定するとする。ここで
、プローブ針３．信号ケーブル４、測定系へ６を用いて
微少電流を、同じくプローブ針３ａ、信号ケーブル４ａ
、測定系Ｂ７を用いて大電流を測定するとすれば、上記
微小電流または上記大電流を測定する仕様（スペック）
を考慮して、それに最適と思えるプローブ針、信号ケー
ブル、測定系を準備し、実際の測定に供すればよい。こ
れによって、微少電流測定のための、接触抵抗の小さい
プローブ針３．浮遊容量の小さな信号ケーブル４．電流
測定レンジの精度や分解能の小さな測定系Ａ６を有する
第１の測定ラインと、大電流測定のための、接触抵抗の
大きいプローブ針３ａ、浮遊容量の大きい信号ケーブル
４ａ、電流測定レンジの精度や分解能の大きな測定系Ｂ
７を有する第２の測定ラインとを別々に得ることができ
る。もちろん各測定ラインのいずれでも同様の測定条件
が得られることが期待できる被測定項目の場合は、どち
らの測定ラインを利用してもよい。An electrode pad 2 and an electrode pad 2a are arranged to take out a certain arbitrary circuit terminal, and a probe needle 3 and a probe needle 3a are applied to these pads 2 and 2a, respectively, and a measurement system 6 and 7 is connected via a signal cable 4 and a signal cable 4a. As an example of the case where the electrode pads 2, 2a of the IC chip 1
Suppose that a minute current (eg, on the order of μA) and a large current (on the order of several 100 mA, for example) are to be measured. Here, the probe needle 3. A small current is applied to the signal cable 4 and the measurement system using the probe needle 3a and the signal cable 4a.
, if a large current is to be measured using measurement system B7, the specifications for measuring the above-mentioned minute current or the above-mentioned large current are
All you have to do is take this into consideration, prepare the probe needle, signal cable, and measurement system that seem most appropriate for that purpose, and then use them for actual measurement. This allows the probe needle 3. with low contact resistance for minute current measurements. Signal cable with low stray capacitance 4. The first measurement line has a measurement system A6 with a small accuracy and resolution of the current measurement range, a probe needle 3a with a large contact resistance for high current measurement, a signal cable 4a with a large stray capacitance, and a measurement system A6 with a small accuracy and resolution of the current measurement range. Measurement system B with high resolution
7 can be obtained separately. Of course, in the case of an item to be measured for which similar measurement conditions can be expected to be obtained on any of the measurement lines, either measurement line may be used.
このように本実施例によれば、ＩＣチップ１上の所定の
端子について、１つの端子に対して複数の電極パッド２
，２ａを設けたから、被測定項目の特性などに応じて測
定ラインを別々に設けて、上記被測定項目毎に最適なテ
スト条件を得ることができ、これにより測定精度の良い
安定したテスト結果が得られ、また上記被測定項目の条
件によっては測定に要するテスト時間を短縮することが
できる。As described above, according to this embodiment, for a given terminal on the IC chip 1, a plurality of electrode pads 2 are provided for one terminal.
, 2a, it is possible to set up separate measurement lines according to the characteristics of the item to be measured, and to obtain the optimal test conditions for each item to be measured, which results in stable test results with good measurement accuracy. Furthermore, depending on the conditions of the item to be measured, the test time required for measurement can be shortened.
なお、上記実施例では、ＩＣチップ１上のある１つの端
子から取り出す２つの電極パッド２，２ａを設けたもの
を示したが、ＩＣチップ１上のある１つの端子から取り
出す電極パッドを必要に応じて３つ以上としてもよく、
また２つ以上の電極パッドを取り出す端子かＩＣチップ
上で２つ以上あってもよい。もちろん上記２つ以上の電
極パッドを使い分ける被測定項目としては微少電流や大
電流以外の項目であってもよい。In the above embodiment, two electrode pads 2 and 2a are provided which are taken out from one terminal on the IC chip 1, but it is not necessary to provide an electrode pad which is taken out from one terminal on the IC chip 1. Depending on the situation, there may be three or more.
Further, there may be two or more terminals on the IC chip from which two or more electrode pads are taken out. Of course, the items to be measured using the two or more electrode pads may be items other than minute current and large current.
また、上記実施例ではテスト条件としてウェハ状態での
いわゆるウェハテストを想定した場合について説明した
が、ＩＣチップをアセンブリした後のいわゆる最終検査
（ファイナルテスト）の場合てあってもよく、上記実施
例と同様の効果を奏する。Furthermore, in the above embodiments, a case was explained assuming a so-called wafer test in a wafer state as a test condition, but it may also be a so-called final inspection (final test) after IC chips are assembled. It has the same effect as.
以上のように本発明の半導体装置によれば、集積回路の
所定の端子について１つの端子に対して複数の電極パッ
ドを設け、被測定項目の特性などに応じて測定ラインを
別々に設けることができるようにしたから、上記被測定
項目毎に最適なテスト条件を得る事かでき、これにより
測定精度の良い安定したテスト結果が得られ、また上記
被測定項目の条件によっては測定に要するテスト時間を
短縮することができる効果がある。As described above, according to the semiconductor device of the present invention, a plurality of electrode pads can be provided for one predetermined terminal of an integrated circuit, and measurement lines can be provided separately depending on the characteristics of the item to be measured. This makes it possible to obtain the optimal test conditions for each item to be measured, which allows stable test results with good measurement accuracy to be obtained, and also reduces the test time required for measurement depending on the conditions of the item to be measured. It has the effect of shortening the
第１図はこの発明の一実施例による半導体装置の複数電
極パッドの使い分けによるテスト状態を示す図、第２図
は従来の単一電極パッドスト状態を示す図である。
図において、１はＩＣチップ、２． ２ａ、 ２ｂは
電極パッド、３，３ａはプローブ針、４，４ａは信号ケ
ーブル、５はマルチプレクサ、６は測定系Ａ、７は測定
系Ｂ、８は測定系ｎである。
なお図中同一符号は同−又は相当部分を示す。
第１図FIG. 1 is a diagram showing a test state in which a plurality of electrode pads are selectively used in a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional single-electrode pad test state. In the figure, 1 is an IC chip, 2. 2a and 2b are electrode pads, 3 and 3a are probe needles, 4 and 4a are signal cables, 5 is a multiplexer, 6 is a measurement system A, 7 is a measurement system B, and 8 is a measurement system n. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1
Claims (1)
回路外部との電気信号の入出力を媒介する電極パッドと
を有する半導体装置において、上記集積回路の所定の端
子について、１つの端子に対して２つ以上設けられた電
極パッドを備え、該２つ以上のパッドの各々を、それぞ
れ上記チップの異なる電気的特性を測定する全く別の測
定系との媒介として用いることを特徴とする半導体装置
。(1) In a semiconductor device having an integrated circuit on a chip and electrode pads that mediate input/output of electrical signals between the inside of the integrated circuit and the outside of the integrated circuit, one terminal for a predetermined terminal of the integrated circuit. The chip is characterized in that it has two or more electrode pads provided for the chip, and each of the two or more pads is used as an intermediary with a completely different measurement system that respectively measures different electrical characteristics of the chip. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23225290A JPH04111334A (en) | 1990-08-30 | 1990-08-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23225290A JPH04111334A (en) | 1990-08-30 | 1990-08-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04111334A true JPH04111334A (en) | 1992-04-13 |
Family
ID=16936362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23225290A Pending JPH04111334A (en) | 1990-08-30 | 1990-08-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04111334A (en) |
-
1990
- 1990-08-30 JP JP23225290A patent/JPH04111334A/en active Pending
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