JPH0398140A - Parallel bus system - Google Patents

Abstract

PURPOSE:To facilitate the maintenance and the check in the occurrence of troubles in a parallel bus system by storing the error information in an error information store part of a master device if the errors occur in the writing and reading states. CONSTITUTION:A data error detecting part 12 of a slave device SR checks the errors for the data received from a master device MS in a writing state and for the stored data including the code information in a reading state respectively. An error information returning part 13 returns the error information obtained from an error checking operation to the device MS. An error information store part 22 of the device MS stores the error information transferred from the device SR. The information stored in the part 22 of the device MS can be read out via a microprocessor 21 or the outside. Thus the check/ maintenance is facilitated with regard to the occurrence of troubles.

Description

[Detailed Description of the Invention] Industrial Application Fields The present invention relates to a parallel bus system that uses a parallel bus to exchange data between a plurality of devices, and more specifically, to a parallel bus system that uses a parallel bus to exchange data between a master device and a slave device. The present invention relates to a parallel bus system in which a parallel bus is connected via a parallel bus, and relates to improving maintainability in the event of a system failure.

Conventional technology> In a parallel bus system that uses a parallel bus to exchange data between multiple devices, error checks have traditionally been performed by adding parity pits to ensure data reliability. method is used.

The operation according to this method is as follows in response to data writing/reading.

(a) From a master device such as a CPU to a memory device or I
When writing data to a slave device such as a /O device, the master device adds barity to the data, and the slave device that receives this checks the data, and if it is normal, sends a bus control signal to the master device. and returns a response, as well as storing data internally. If an error is detected in the check, no response signal is returned to the master device, and no data is stored internally.

(b) When reading data in the slave device from the master device If parity is added to the storage means in the slave device, the slave device reads the data from the internal storage means and performs an error check to see if it is normal. For example, data is sent back to the master device along with a response signal. If an error is detected in the error check, no response is returned to the master device.

If parity pits are not added to the storage means, parity is added and the data is sent back to the master device. The master device performs an error check on the returned data, and if it is normal, the data is imported internally.

Problems to be Solved by the Invention In such a system, when a failure occurs and the slave device becomes unresponsive to access from the master device to the slave device, it is necessary to identify the location of the failure and perform maintenance. There is.

However, the causes of a slave device becoming unresponsive include a failure in the control unit that controls the bus, or an error being detected in the data transmission unit, making maintenance and inspection difficult in the event of a failure. .

The present invention has been made in view of these points, and is designed to transmit as much detailed information as possible in the event of a failure in a system that uses a parallel bus to exchange data. The purpose is to make inspection and maintenance of the equipment easier.

Means for Solving the Problems> The present invention for solving the above-mentioned problems is a parallel bus system in which a master device and a slave device are connected via a multiplex parallel bus, the slave device having: When access is received from the master device, the data error detection unit checks for errors the data sent by the master device if it is a write operation, or the data stored internally including code information if it is a read operation. When the data error detection section detects an error, error information is returned to an address signal not used during data transfer together with a response signal to the master device, and when no error is detected, normal information is returned. an information reply section; the master device includes: a microprocessor that instructs the slave device to read/write data; an error information storage section that stores error information when there is a response from the slave device; The microprocessor is configured to include a readout means that allows the microprocessor to read out the information stored in the information storage section.

Function> The data error detection section in the slave device checks for errors the data sent by the master device in the case of a write operation, and the data stored internally including code information in the case of a read operation.

The error information return unit returns error information obtained as a result of the error check to the master device.

The error information storage section within the master device stores error information transferred from the slave device.

By reading the information stored in the error information storage section from the microprocessor in the master device or from outside, it becomes possible to know detailed information at the time of failure.

Example Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, MS is a master device, SR is a slave device, and BS is a parallel bus connecting the two, with a signal line L1 responsible for transferring 1 to m bits, a signal line L2 responsible for transferring m+1 to n bits, It is composed of a signal IIIL3 that is responsible for transferring check bits, and a signal line L4 that is responsible for transferring control signals.

This parallel bus BS uses signal line L1 and signal line L2 to transfer n-bit address information, and uses m-bit (n
>m), the signal line L1 of address n bits is used to transfer the data information. Also, at least during data transfer, code information k for error checking is provided.
The bits are transferred using signal line L3.

In the slave device SR, 11 is an internal storage section in which various internal information and data are stored, and 12 is an internal storage section in which various internal information and data are stored; and 12, when accessed from the master device, if it is a write operation, it also reads the data sent by the master device. In the case of operation, a data error detection section 13 checks for errors in data stored including code information, and when the data error detection section 12 detects an error, it transfers the data together with a response signal to the master device MS. This is an error information return unit that returns error information to the (n−m) bits of the address signal that are not used when the error is detected, and returns normal information when no error is detected.

In the master device MS, 21 is a microprocessor that instructs the slave device to read/write data, 22 is an error information storage unit that stores error information when there is a response from the slave device SR, and 23 is an error information storage unit. The information stored in the section 22 is transferred to the microprocessor 21.
Alternatively, it is a reading means that can be read from an external device (not shown).

The operation of the system configured as described above will be explained separately in write operation and read operation as follows.

(Write Operation) FIG. 2 is a time chart showing an example of the operation in this state.

(a) to (e) are all control signals transferred via signal line L4, including address strobe AS, address acknowledge ATACK, and data strobe D.
S, data ● Acknowledgment DTACK and write operation instruction WRITE are both low active.

First, master device MS uses signal lines L1 and L2 to send address information to slave device SR as shown in (f) and (g), and also instructs a write operation as shown in (e).

Next, when the address information is settled, the address strobe AS7' becomes active/alive as shown in (a), and the slave device SR receives this strobe AS and sends the address acknowledge ATACK as shown in (b). Activate and respond as shown.

Next, the master device MS pulls up the address information, sends the write data using the signal line L1 as shown in (f), and sends the check information using the signal line L3 as shown in (h). Send out. Then, when these are stabilized, as shown in (C), the data ◆ strobe DS
Activate.

In the slave device SR, an error check is performed from the write data and check information transferred using the signal lines L1 and L3, and if the check is normal, the transferred data is taken into the internal storage unit 11, and ( As shown in g), a normal code is returned to the error information. Also,(
d) Activate the data●acknowledgment DTACK as shown in d).

On the other hand, if an error is detected as a result of the error check, the transferred data is not taken in, a code indicating a write data error is returned as error information, and data acknowledgment DTACK is activated.

The master device MS receives data acknowledgment DTACK.
The response and the normal code of the error information are recognized and the cycle ends. If the error information is a code indicating a data error, predetermined error processing will be performed.

(Read operation) FIG. 3 is a time chart showing an example of the operation in this state.

(a) to (e) are all control signals transferred via the signal line L4, except that the WRITE signal shown in (e) is inactive. This is done in the same way as the write operation.

After pulling up the address information, the master device MS activates the data strobe DS as shown in (C). In response to the activation of the data strobe DS, the slave device SR reads the contents of the internal data storage section 11 from the transferred corresponding address, and the data error detection section 12 performs an error check.

If the result of the error check is normal, a normal code is returned to the read data and error information, and the data acknowledge DTACK is activated as shown in (d). If an error check error is detected,
Reply the code of the read data error in the error information.

The master device MS stores the transferred error information in the error information storage unit 22 and sends a data acknowledgment DTACK.
When the error information is received, if the error information is normal, the read data is taken internally and the cycle ends. If the error information indicates an error, predetermined error handling is performed.

In this case, the error information can be read out from the microprocessor 21 or externally through the reading means 23, and the cause of the error can be analyzed.

Although the above embodiment shows an example in which only one slave device SR is connected to the parallel bus, it is assumed that a plurality of slave devices are actually connected.

Effects of the Invention> As explained in detail above, according to the present invention, when an error occurs during a write operation or a read operation,
Error information is stored in the error information storage section of the master device MS, and errors in write data sent by the master device and errors in read data from slave devices can be accurately known, and errors in system failure can be detected. This makes maintenance and inspection easier. Furthermore, since address signal lines that are not used during data transfer are used, the number of physical signal lines does not increase. Furthermore, no special control signal is required for transmitting error information, and error information can be transmitted using only a control signal for realizing the original function, so the overall circuit can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG.
3 and 3 are time charts of write operations and read operations in the system of the present invention. MS...Master device SR...Slave device B
S...Parallel bus 11...Internal storage section 12.
...Data error detection section 13...Error information reply section 21...Microprocessor 22...Error information storage section 23...Reading means

Claims (1)

[Claims] A parallel bus system in which a master device and a slave device are connected via a multiplex parallel bus, and when the slave device receives access from the master device, it performs a write operation. If it is a read operation, the data sent by the master device is checked for errors, and if the data is stored internally including code information. , an error information return unit that returns error information to an address signal not used during data transfer together with a response signal to the master device, and returns normal information when no error is detected; A microprocessor instructs the device to read/write data, an error information storage section that stores error information when there is a response from the slave device, and a microprocessor that reads the information stored in the error information storage section. 1. A parallel bus system characterized by being provided with a readout means that allows the output of the parallel bus.