JPH039551B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording disk rotation control system,
In particular, the present invention relates to a recording disk rotation servo system for controlling the rotation of a disk on which digital signals are recorded.

In recent years, analog information such as audio signals has been converted to PCM.
(pulse code modulation) and recording on a recording medium in a digital signal format of 1 or 0 is being researched and put into practical use. In this case, in order to facilitate the demodulation of the digital signal, a so-called self-clocking modulation method is used, and in order to achieve higher density recording, the linear velocity of all recording tracks is fixed at a constant speed instead of a constant rotational angular velocity method. It is often recorded using the linear velocity (CLV) method. It takes
When playing a CLV disk, it is necessary to control the rotation of the disk to maintain a constant linear velocity.
For this purpose, it is common to extract reproduced clock information of a predetermined frequency from the reproduced signal and perform spindle servo based on this clock signal.

An example of this modulation method is EFM (Eight to
There is a fourteen modulation system, which has a format as shown in FIG. That is, one frame consists of, for example, 588 bits, and the data signal is converted to 14 bits every 8 bits using the EFM method according to a predetermined conversion table (not shown), and 3 adjustment bits are added to make 17 bits. It is recorded as a unit, and when it is 1, there is an inversion from a logic H level to a logic L level or vice versa, and when it is 0, there is no inversion, that is, it is recorded in the form of NRZI.

At the beginning of each frame, the first bit is 1, the second
The 11th bit is 0, the 12th bit is 1, and the 11th bit is 0.
The frame sync signal is recorded so that the 13th to 22nd bits are 0 and the 23rd bit is 1. A control signal is placed at a predetermined position of 588 bits based on this frame sync signal. Throughout the signal processing, signal processing is performed such that 2 or more and 10 or less 0's are placed between 1's. That is, the minimum inversion interval of the signal level is 3T (T is the length of a bit cell), and the maximum inversion interval is 11T.
Further, in parts other than the frame sync signal, the maximum inversion interval is prevented from occurring two or more times in succession.

A signal equivalent to a full-wave rectified version of this modulated signal is input to a PLL (phase locked loop) to extract clock information and perform signal reproduction processing. In some cases, the musical tone data becomes a fixed pattern corresponding to the zero level. In this case, the EFM signal is inverted every 7T, 3T, and 7T, for example, and becomes a time-series signal that includes many repetitive waveforms with one period of 17T. In addition to the spectrum of the clock information frequency (4.3218MHz), the input signal of the PLL in the above-mentioned non-musical band part contains spurious signals with a high energy level at a frequency that is shifted from the bright line spectrum by an integer multiple of 1/17 of the clock frequency (254KHz). has. Since the frequency of this spurious is close to that of the positive phase clock, it is difficult to distinguish between the two based on the frequency. Therefore, the PLL for clock extraction may mislock due to this large spurious energy level, making accurate clock extraction and, ultimately, accurate data reproduction impossible. Furthermore, if the input signal frequency of the PLL deviates significantly from the correct frequency, no locking will be possible.

Therefore, when starting up, especially when starting up a non-musical part, or when moving the pick-up largely and quickly in the radial direction of the disk to search for address information, the rotational speed of the disk may be significantly lower than the predetermined speed. If the clock speed is different, it may be impossible to extract the correct clock, and as a result, there is a drawback that it takes a long time to control the rotation speed of the disk to the correct rotation speed so that the correct clock can be extracted again.

The present invention has been developed in view of this situation, and its purpose is to quickly escape from the mislock state and accurately detect the disk even when a recovered clock cannot be extracted due to the above-mentioned PLL mislock or the like. An object of the present invention is to provide a rotation control method that allows rotation control.

The rotation control method according to the present invention is a rotation control method for a recording disk on which a digital signal including clock information of a predetermined frequency and a synchronization signal in which the maximum interval is inverted n times (n is an integer) consecutively is recorded. A period of time n times the maximum inversion interval is detected from the signal, and the detected signal is used to control the disk rotation, and the reproduction signal is sent to the PLL circuit that can be locked within a predetermined frequency range that includes the frequency of the clock information. to extract the clock signal, use the extracted clock signal to demodulate the synchronization signal, and forcefully sweep the oscillation frequency of the voltage controlled oscillator of the PLL circuit if the synchronization signal is not demodulated. It is characterized by

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 2 is a schematic block diagram of an embodiment of the present invention, mainly depicting a spindle control system for disk rotation control. Before explaining Figure 2,
The main operating functions of the spindle control system will be described. The first function is acceleration function (ACC function)
The second function is the holding function (HLD function), which is an operation that increases the motor rotation speed by passing a large constant current through the spindle motor. Therefore, it is possible to maintain a constant rotational speed against the frictional force of the rotating system. The third function is the frame sync servo function (SYNC servo function), which detects frame sync directly from the reproduced RF signal (without extracting the reproduced clock) and adjusts the rotation speed so that the linear velocity is approximately accurate. This is a function to control the The fourth function is a quartz servo function (QRTZ servo function), which generates a frequency error signal obtained by comparing a signal corresponding to the frequency of the reproduced clock signal extracted from the reproduced RF signal with a reference signal, and a reproduced clock signal. Demodulate the EFM signal using the signal,
Using the phase error signal obtained by comparing the phase of the frame sync detected from this demodulated signal and the phase of the reference frame sync (7.35KHz), the disk rotation speed is controlled to obtain accurate linear velocity. It is something.

These four functions are the system controller 1
ACC, HLD, SYNC from (see Figure 2),
It operates selectively depending on each QRTZ control signal. When the disk does not need to rotate (during stop and eject operations), none of these control signals are output, and the spindle motor drive current is set to zero.

Referring to Figure 2, the reproduced RF signal from the pickup 2 is shaped by the waveform shaper 3.
It becomes an EFM signal. This signal is input to the frame sync servo device 4 and a frame sync servo signal is generated. This servo signal is applied to the spindle driver 6 via the switch 5, thereby making the spindle motor a SYNC servo.

In the case of ACC operation, a constant voltage +V is applied to the spindle driver 6 via the low resistance Ro ₁ .
A large constant current (or constant voltage) is supplied to the spindle motor, resulting in ACC operation. Furthermore, in the case of HLD operation, the value of resistor Ro ₂ is selected to be larger than that of resistor Ro ₁ so that a small constant current (or constant voltage) is supplied to the spindle motor, thereby enabling HLD operation.

The output of the waveform shaper 3 is input to a clock extractor 7, and this extractor 7 has a PLL (phase locked loop) circuit configuration that locks to clock information of a predetermined frequency included in reproduction information.
The recovered clock signal extracted in the PLL 7 and the previous waveform shaping output are both input to the demodulator 8, where they are converted into a predetermined digital signal (NRZ) signal. The demodulated output is input to a RAM (random access memory) 9, read out by a constant read clock pulse, and converted into analog information by a D/A converter 10 to be output as audio.

11 is an error corrector, which detects and corrects bit errors and burst errors;
The operations of this error corrector 11 and RAM 9 are controlled by a RAM controller 12.

The demodulator 8 also has a sync detection function for detecting frame sync from the EFM signal using a reproduced clock, and the RAM controller 12 is controlled by the timing of occurrence of this reproduced frame sync. On the other hand, the frequency divided output from the frequency divider 13 of this reproduction frame sync is one input of the phase comparator 14, and the other inputs include the frequency divider 1 of the reference frame signal generated from the reference signal generator 14.
A frequency divided output by 5 is provided. The phase comparison output is level-adjusted in a level shifter 16 and then becomes one input of an adder 17 as a phase error signal.

The output of the level shifter 18 that compares the output of the loop filter (see 73 in FIG. 6) in the PLL 7 with a predetermined reference voltage and adjusts the level of the comparison output is sent to the adder 17 as a frequency error signal.
The output of this adder 17 becomes a quartz servo signal and is sent to the spindle driver 6.
It is now applied to Also, the demodulator 8
The frame sync detection output of is supplied to the system controller 1. This detection output controls the state of the switching device 5 and switches the spindle servo operation, which will be described in detail later. Furthermore, from the system controller 1, the VCO (6th
A control signal for sweeping or forced sweeping the oscillation frequency (see 74 in the figure) or a forced sweep control signal is supplied, and the operation in this case will also be described later.

Note that 19 indicates a keyboard, which means an operation panel or a remote control board of the playback device. Reference numerals 20 and 21 indicate tracking servo and focus servo systems, the operations of which are also controlled by the system controller 1.

FIG. 3 is a block diagram showing a specific example of the frame sync servo device 4, and is a block diagram showing a specific example of the frame sync servo device 4, which is used for playback as shown in FIG.
The EFM signal is input to retriggerable MMVs (monostable multivibrators) 41 and 42. It is assumed that the MMV 41 is triggered when the input signal is reversed in the positive direction, and the MMV 42 is triggered when the input signal is reversed in the negative direction, and each outputs a logic L signal of To for a certain period of time. The output of both MMVs is OR gate 43
It becomes the trigger input of the retriggerable MMV 44 via the LPF 45, and the output of this MMV 44 is converted to a DC level in the LPF 45. This DC level is level-compared with a reference level 47 in a comparator 46, and this comparison output becomes a sink servo signal.
This becomes the input to the switch 5 shown in FIG. still,
A reset signal is supplied to the MMV44 and LPF45 from the outside, and when the sync servo is off, the timing of this reset signal causes the MMV44 and LPF45 to reset.
The capacitors of the time constant circuits of LPF 44 and LPF 45 are discharged to return to the initial state. Therefore, the settling time when the sync servo is next turned on is shortened.

Here, the output pulse width To of MMV41 and 42 is
is the period of the frame synchronization signal (2 times the maximum inversion interval)
times) is set approximately equal to 22T (strictly speaking
20-30ns shorter than 22T). Further, it is assumed that the output pulse width T ₁ of the MMV 44 is set to be smaller (for example, 1/2 of the frame synchronization signal frequency) than the cycle of the frame synchronization signal (for example, 1/7.35 KHz≈136 μs). As shown in FIG. 1, it is not determined whether the frame sync of the EFM signal starts from the rising edge or from the falling edge, and this is due to the nature of the EFM signal. For this purpose, MMV41, which is triggered by the rising edge and falling edge of the input signal, respectively,
42 are provided.

Now, the only time the interval from one rising edge of the input signal to the next rising edge or from one falling edge to the next falling edge is 22T is in the case of frame sync, so if the disk rotates at the correct linear speed. If so, this 22T interval would be approximately 5.09μs, so the retriggerable MMV4
The output pulse width To of 1 and 42 is set to be approximately 20 to 30 ns (width as a pulse capable of triggering the next stage MMV 44) shorter than this 5.09 μs.

Figure 4 shows the operation timing chart of the circuit in Figure 3, where A is when the linear velocity is greater than the specified value, B is when it is approximately at the specified value, and C is when it is less than the specified value. are shown respectively. In other words, when the linear velocity is large as in A, the next rising edge always arrives before 5.09 μs has elapsed since the input rising edge (the same applies to falling edges, and the same applies hereafter), so MMV41 is not triggered. The output continues to remain at a low level. In a substantially proper case as shown in B, the rising edge interval only in the frame sync portion is 5.09 μs, so a narrow pulse of about 20 to 30 ns can be obtained at the output of the MMV 41 in synchronization with the frame sync. Next, when the linear velocity is small as in C, pulses are obtained in the output of the MMV 41 both in the frame sync part and in other parts.

In this way, depending on the linear velocity, the OR gate 4
Since the number of output pulses of 3 changes, if the MMV 44 is triggered by this gate output to generate a pulse train of a predetermined width and then converted to DC by the LPF 45, the output of the LPF 45 will eventually reflect the F/V of the reproduced signal.
A converted signal will be obtained.

In other words, if the linear velocity of the disk is correct, the MMV
Since MMV44 is triggered only in the frame sync part, the F/V conversion signal shows a predetermined value, but if it is earlier, MMV44 is not triggered and the F/V conversion signal shows a predetermined value.
The V conversion signal becomes zero, and if it is slower, MMV4
4 is triggered in the frame sync portion and other portions as well, so the F/V conversion signal becomes larger than the predetermined value. A servo signal is obtained by comparing this F/V conversion output with a level 47 corresponding to a normal linear velocity.

By the way, how the output voltage of the LPF (45 in FIG. 3), which is an F/V conversion signal, changes with respect to a change in the linear velocity of the disk will be explained based on FIG. 5.

If the disk is rotating faster than the correct linear velocity γ ₂₂ , no trigger pulse of the MMV 44 is generated as shown in FIG. 4A, so the output voltage is also zero. Also, if the rotation is very slightly slower than the correct linear velocity γ ₂₂ , each frame sync
A trigger pulse of MMV44 is generated, and therefore the output voltage becomes a value corresponding to the frame sync frequency of 7.35 KHz. As the linear velocity gradually becomes slower than _γ22 , the frame sync frequency itself decreases from 7.35KHz, so the output voltage also decreases accordingly. However, the linear velocity is correct when the linear velocity γ ₂₂
When γ ₂₁ becomes about 4.5% slower than
In addition to the 22T frame sync, the MMV 44 trigger pulse also occurs at the 21T transition interval included in the signal, so the output voltage suddenly increases. A similar change occurs as the linear velocity gradually decreases. Additionally, when the linear velocity becomes very slow, the next trigger pulse will arrive between the time the MMV44 is triggered and the end of the output pulse, so the MMV44 will continue to be triggered, and the output voltage will saturate to its maximum value. .

In this way, it has the characteristics shown in Figure 5.
The difference signal between the LPF output voltage and level 47 is used as a servo signal.If level 47 is set to a value corresponding to the correct frame sync frequency of 7.35KHz (predetermined value a in Figure 5), the LPF output voltage is the predetermined value a at linear velocities such as γ ₂₁ and γ ₂₀ in addition to γ ₂₂ .
Since it becomes equal to , there are many stable points, and correct servo cannot be performed. But level 4
If 7 is set sufficiently lower (for example, about half) than the value corresponding to 7.35KHz, as shown in b in Figure 5, the stable point will be only at one point at the correct linear velocity γ ₂₂ ,
Therefore, almost accurate linear velocity servo can be performed.

That is, the circuit system shown in FIG. 3 detects a period that is n times the maximum inversion interval of the reproduced signal (n=2 in the embodiment) by comparing it with a reference period, and detects a signal corresponding to this detection signal, that is, A frame sync servo signal is obtained by generating an F/V conversion signal and comparing this signal with a reference value. By driving the spindle motor using this servo signal, the recording disk can be driven at a substantially accurate linear velocity. This frame sync servo is extremely useful when clock information cannot be extracted from the reproduced signal, such as during startup or search (search for address information) operations.

Next, details of the quartz servo function will be explained. Digital information reproduced from a rotating recording disk with wow and flutter is written into the RAM 9 (see Figure 2), read out using a constant clock signal, and subjected to D/A conversion. This results in a high quality audio signal without wow and flutter. In this case, since the capacity of the RAM is limited, if the read speed and the write speed are not exactly equal on average, the stored information in the RAM will become empty or vice versa.
In this case, the reproduced sound becomes choppy.

Therefore, when reproducing musical tone signals, the quartz servo is operated to maintain the disk linear velocity constant and to always match the writing speed with the reading speed. That is, the phase comparator 1 detects the phase of the frequency-divided output of the reproduction frame sync obtained from the demodulator 8 in FIG. 2 and the frequency-divided output of the reference frame sync signal.
4 (of course, if the frequencies are appropriate, the reproduction and reference frame sync signals may be directly compared), and a signal corresponding to this phase difference is applied to the spindle motor as a servo signal. However, since this phase error alone does not provide adequate damping characteristics for a servo,
Furthermore, it is necessary to introduce a frequency error and mix it with the phase error.

Therefore, since the LPF output voltage of the clock extraction PLL 7 corresponds to the frequency of the reproduced clock signal, this voltage is compared with the reference voltage and the comparison output is used as frequency error information and added to the phase error information in the adder 17. This is how the quartz servo signal is obtained. By applying this quartz servo, it becomes possible to perform accurate linear velocity servo in which the reading and writing speeds of the RAM 9 are exactly equal on average. Therefore, upon startup, an acceleration (ACC) operation followed by a holding (HLD) operation is performed to bring the rotational speed of the spindle motor to a certain level, and after that, even if no clock signal is extracted, the speed is close to the specified linear velocity to some extent. Frame sync (SYNC) servo operation that allows speed control. Thereafter, after confirming that playback frame sync has been detected, the system switches to quartz servo (QRTZ) servo operation to maintain a constant prescribed linear velocity.

FIG. 6 is a block diagram of the PLL 7 for extracting self-clock information from the reproduced EFM signal.
The reproduced signal A is input to an edge detector 71, and a pulse B synchronized with the level transition timing of the reproduced signal A is generated. This edge pulse B is set to have a pulse width approximately equal to a half cycle of a regular clock signal. This edge pulse becomes one input of the phase comparator 72, and the output C of the VCO 74
The phase is compared with This phase difference output is LPF73
The signal is converted into a direct current and becomes a control signal for the VCO 74.
The output of this VCO 74 is converted into pulses by a waveform shaper 75 and output as a reproduced clock signal. In addition, in order to quickly lock the PLL,
Sweep control is performed using the output of the LPF 73, and the sweep controller 76 controls the oscillation frequency of the VCO 74 to sweep between predetermined upper and lower limits. In addition, in order to release the PLL mislock, a forced sweep control signal is applied to the sweep controller 76 in order to apply a disturbance to the PLL 7 and perform a forced sweep that is faster than the previous sweep operation. The forced sweep control is performed by commands from the system controller 1 shown in FIG.

FIG. 7 is the operating waveform of PLL7 in FIG. 6,
A to C correspond to the waveforms of signals A to C of the block in FIG. As you can see from the diagram, VCO7
4 output has 4.3218MHz at normal linear velocity.
A sine wave of (emission line spectrum component) is obtained, and clock extraction becomes possible.

FIG. 8 is a circuit diagram of the frame sync detector included in the demodulator 8 of FIG. 2. The reproduced EFM signal is input to the edge detector 81, and pulses are generated in response to the level transition timing of the reproduced signal. Ru. These edge pulses are sequentially written into a 23-bit shift register 82 operated by a regenerated clock signal. A total of 10 bits output from the 2nd bit to the 11th bit of the shift register 82 is input to a NAND gate 83, and a total of 10 bits output from the 13th bit to the 22nd bit of the shift register is input to a NAND gate 84. ing. The outputs of both NAND gates and the outputs of the 1st, 12th, and 23rd bits of the shift register 82 are input to a 5-input AND gate 85, and the output of this gate serves as a reset signal for the counter 86. The counter receives the reproduced clock as an input, and the output of this counter is derived as a frame sync detection signal and supplied to the system controller 1.

When the frame sync signal is included in the reproduced EFM signal and the frame sync signal has finished being input, the contents of the shift register 82 are as shown in the figure. Therefore, the output of the AND gate 85 at this point shows a logic H (1) level, and in all other cases shows a logic (0) level. Therefore, if the counter 86 is a 588-bit counter equivalent to one frame of the reproduced signal, the counter 86 is
is always reset to zero, so the frame sync detection signal is derived as a logic L level when the reproduction frame sync is detected. On the other hand, when the counter 86 counts 588 reproduced clocks, if no frame sync arrives, the counter 86 is not reset and outputs a logic H signal. It becomes possible to identify whether the correct recovered clock has been extracted or not.

Switching from frame sync servo to quartz servo is performed only when this playback frame sync is detected, and if playback frame sync is not detected during frame sync servo, the transition to quartz servo is not possible. Since this is impossible, the PLL 7 is forcibly swept to control the forced pull-in to clock information.

FIG. 9 is a diagram showing a specific example of the sweep controller 76 in FIG. 6. In both figures, equivalent parts are designated by the same reference numerals and explanations will be omitted. The DC voltages Vg and Vh with different levels are
1,702 and further through resistors R ₃ and R ₄ ,
It is applied to the negative phase input of the amplifier OP ₁ constituting the loop filter 73 . In addition, the filter 73 is an amplifier
It has an active filter configuration including resistors R ₁ and R ₂ in addition to OP ₁ and capacitor C ₁ . For controlling the switches 701 and 702, an R-S flip-flop 70 consisting of 3-input NOR gates G ₁ and G ₂
3, the switch 701 is turned on and off by the output C of the gate _G1 , and the switch 702 is turned on and off by the output D of the gate _G2 .

Furthermore, the output H of the loop filter 73, that is,
Level comparators 704 and 705 are provided to determine the upper and lower limits of the control input voltage level of the VCO 74. A voltage Vm that determines the upper limit level is applied to the negative phase input of one comparator 704, and a voltage that determines the lower limit level is applied to the positive phase input of the other comparator 705.
Vn is applied. Both comparators 704, 705
The output H of the LPF 73 is supplied to the positive phase and negative phase inputs of the LPF 73. The outputs I and J of both comparators 704 and 705 are respectively output from the gates of flip-flop 703.
It becomes one input for _G2 and _G1 , and is used as a set and reset input. A sweep control signal A is applied to the remaining inputs of gates _G1 and _G2 to perform sweep control.

A switch 706 is provided across the resistor _R4 , and is turned on by the forced sweep control signal B to short-circuit the resistor _R4 .

FIG. 10 is a diagram showing the operation of the circuit of FIG. 9, and A to J indicate the waveforms of signals A to J of the circuit of FIG. 9, respectively. Note that E and F are charts showing the on/off timing of the switches 701 and 702, and G is a waveform showing the charging/discharging current of the capacitor _C1 of the filter. When sweep control signal A is at H level, flip-flop 703 is clamped in the reset state, so no sweep operation occurs. The signal A is L
When the level is reached, the flip-flop 703 is released from the reset state and can be swept. Assume now that the forced sweep control signal B is at H level and the switch 706 is turned off. At this time, if switch 701 is turned on, capacitor C ₁
A charging/discharging current indicated by G flows through the gate, and the output of the LPF 73 gradually decreases as indicated by H. When this output level reaches the lower limit level Vn (4V), the comparator 705
An output is generated from J to set flip-flop 703. Therefore, the output of the flip-flop 703 is inverted as C and D, and the switch 701 is turned off and the switch 702 is turned on, so that a negative voltage Vh is applied to the capacitor _C1 , and the capacitor _C1 is discharged as shown in G. will be held. As a result, the output of LPF73 is at the lower limit level Vn like H.
The voltage gradually rises from there to the upper limit level Vm (6V).

When the upper limit level Vm is reached, the comparator 704 operates and resets the flip-flop 703, so the on/off states of switches 701 and 702 are reversed, and the LPF output goes high again from the upper limit to the lower limit.
changes. In this way, the oscillation output frequency of the VCO 74 repeatedly increases and decreases within a certain range, creating a so-called sweep operation. For example, 4.3218MHz±200K
The Hz range is swept in approximately 10ms. This sweep is relatively slow;
Since it is only a small disturbance to PLL, PLL
Once it locks to the reproduced clock frequency, it will never lose lock again. Also, the sweep range is ±200KHz, and the spurious interval (254K
Hz), so as long as the disk is rotating at the correct linear velocity, the PLL will not mislock due to spurious forces.

When this PLL mislocks due to spurious signals during a search, etc., and in order to release the mislock, the forced sweep control signal B goes to the L level and the switch 706 is turned on. Therefore, the resistor R ₄ is short-circuited, and the charging/discharging current to the capacitor C ₁ becomes large, and the sweep speed becomes faster (for example, about 100 times the normal sweep). The timing chart for each part in this case is shown as a forced sweep at the right end of FIG. In other words, a large disturbance is applied to the PLL, and the PLL is no longer able to maintain lock, the mislock is released, and a forced sweep is started. This forced sweep signal B only needs to remain low for a time width long enough for the PLL to escape from the mislock (for example, about several tens of microseconds), so the system controller can set the forced sweep signal B to high within a few tens of microseconds after setting it low. Return to After that, the sweep speed becomes normal. Then, the system controller again monitors the presence or absence of frame sync for a predetermined period of time (for example, about 10ms, which is one sweep cycle in Figure 9).
If frame sync is still not detected after a while, force sweep is performed again. By repeating this operation until frame sync is detected, the PLL can be correctly locked.

Examples of flowcharts for operating the spindle motor from startup to a stable state at normal linear velocity using the above configuration are shown in 11th and 12th flowcharts.
As shown in the figure. The pick-up laser diode LD is activated in response to the activation command. After this diode stabilization time (approximately 200ms) is taken into account, the spindle motor acceleration ACC
At the same time as the operation is started, the focus servo pull-in operation is also started. This ACC operation is performed for approximately 500ms, and then a hold HLD operation is performed to maintain the rotation speed approximately constant. The focus servo locks at the earliest after 100ms after the focus servo pull-in command is generated (this 100ms
is the period during which the focus lens moves from the farthest position to the disk to approach the disk)
During this period, the ACC operation causes the disk rotation speed to rise to some extent, reaching approximately 500 rpm after 500ms. This is close to the rotational speed at which the specified linear velocity is achieved at the track radius (approximately 24 mm) of the innermost circumference of the disk (the pick-up is always at this radius position at startup).

During the HLD operation after the ACC operation, the focus servo lock state is detected, but since activation is always performed at a position where a track exists, this detection is performed by detecting the level of the reproduced RF signal. At this point, if the focus servo is not locked, the tracking servo cannot operate and extraction of the reproduced clock is also impossible, so the focus servo loop is opened and the focus servo pull-in operation is repeated again. It is.
If it is not possible to pull the focus even after two attempts, it will be deemed unable to activate and will be ejected.

If the focus servo is locked, the tracking servo loop is then turned on, and after a certain period of time (after the lock is stabilized), the frame sync (SYNC) servo operation is switched to. During the SYNC servo, the demodulator 8 determines whether or not a playback frame sync is detected. If frame sync is not detected, the disk rotation speed will still deviate significantly from the correct value (approximately ±4.6
%, and this range roughly matches the PLL sweep range of 4.3218MHz ± 200KHz), or there is a mislock due to spurious, so naturally the transition to quartz servo is not possible. It's impossible. Therefore, the RF signal is checked again (this is to check whether the focus has been lost due to strong external vibrations, etc.) to see if the focus servo is locked. If it is out of lock, it becomes stop mode. If the reproduced RF signal is good,
Forced sweep control of the PLL (the forced sweep control signal in FIG. 8 is supplied) is performed,
As described above, the presence or absence of frame sync detection is determined again after, for example, 10 ms has elapsed.

That is, since frame sync is detected when the PLL locks to the reproduced clock information, this forced sweep control operation is repeated until then. For example, if frame sync cannot be detected even after repeating this loop a predetermined number of times, the process shifts to eject mode. This is to take into account cases where the disk is extremely dirty or the disk is installed upside down. When frame sync is detected, the system switches to quartz servo for the first time, and thereafter operates at a constant linear velocity.

As mentioned above, even if the reproduced RF signal is good after the frame sync servo is turned on, it may not be possible to detect frame sync. This is because the linear velocity does not become correct instantly after the frame sync servo is turned on, but due to the inertia of the disk. This is because it takes a certain amount of time depending on the moment, etc., and the reason why the clock is not simply put into a standby state until then is to extract the clock as quickly as possible.

Next, operation control of the spindle servo during a so-called search operation in which desired information is reproduced by searching for address information will be explained. One bit of this address information is recorded at a specific location in one frame, and one address unit is made up of 98 frames, that is, 98 bits.
The last 16 bits of 98 bits are CRC (Cyclic
Redundancy Check) code and is designed to be able to detect errors.

At the time of search, a target search address is specified, and the addresses are compared while performing a fast forward operation (slider control) of the relative position in the disk radial direction between the recording disk and the pick-up information detection point. More specifically, the process repeats a few fast-forward operations, then stops, applies tracking servo, extracts the reproduced clock, reads address information, and compares it with the search address. Therefore, in order to shorten the search operation, it is desirable to shorten the time required until the address information becomes readable after fast-forwarding is stopped. On the other hand, during fast forwarding, the pick-up crosses the track one after another,
Since the RF signal waveform is very disturbed, the servo signal of frame sync servo also has a large error, so it is not a good idea to apply sync servo. Therefore, during fast forwarding, the sync servo is turned off and the rotation speed is maintained.
Switch to HLD operation.

After fast-forwarding a predetermined distance, it is necessary to read the address information and compare it with the search address, but this address reading period needs to be controlled to a predetermined linear velocity or a speed close to it because of the need to extract the reproduced clock. arise. Therefore, during this period, the frame sync servo operation is switched. That is, while performing the HLD operation, fast-forwarding a predetermined distance is performed to approach the search address, the HLD operation is turned off, and then the frame sync servo operation is switched to read and compare the addresses.

Here, during fast forwarding, the error of the frame sync servo becomes large as described above, and therefore, during this time, this large error voltage is applied to the capacitors such as the LPF 45 in FIG. 3. In this case, a large current will be supplied to the spindle motor when fast forwarding is stopped and switched to frame sync servo operation, and correct servo operation will be performed after the linear velocity has once deviated greatly. Therefore, it takes a long time until the clock extraction PLL 7 locks again, which causes a long search operation. Therefore, in order to prevent this drawback, when the sync servo is off, the system controller 1 generates a reset signal to discharge the capacitor of the frame sync servo system shown in FIG.

FIG. 13 is a chart showing an example of a search operation, and shows a case where the search is started from an address portion smaller than the target search address. The period from t ₀ to _{t 1} is a forward fast forward operation (FAST
FWD1) period, during which the disk moves a predetermined distance in the radial direction while maintaining a constant rotation speed by HLD operation. Between _t1 and _t2 , the address is read and compared with the search address while performing the sync servo operation. Since the search address is larger, FAST is performed while performing HLD operation from t ₂ to _{t 3} .
FWD1 is performed again, and address comparison is performed while performing sync servo operation from _t3 to _t4 . At this point, the search address is exceeded, so between t ₄ and t ₅ ,
Fast forwarding in the reverse direction (FAST RVS) of a predetermined distance is performed while performing HLD operation, and address comparison is performed by sync servo operation between _t5 and _t6 . Since the address is smaller than the search address, the HLD operation is performed between t ₆ and _{t 7} , and the FAST FWD2 operation is performed to send the pick-up a predetermined distance shorter than the forward or reverse fast forward operation (FAST FWD1 or FAST RVS). .

Between _t7 and _t8 , addresses are compared using the sync servo, and when it is detected that the search address has been exceeded, a so-called jump operation using a tracking mirror or the like is performed instead of a fast forward operation. That is, the rotation angle of the tracking mirror is changed instantaneously to cause the spot light, which is the information detection point, to jump over the adjacent track. This jump operation is divided into two stages. First t ₈ ~ _{t 9}
During this time, a jump reverse (jump to an adjacent track in the opposite direction) is performed for several to several tens of tracks (this is called a multi-jump reverse), and then an address comparison is performed. The jump operation for one track is performed instantaneously (about 100 to 500 μs). Therefore, the time during which the reproduced signal is disturbed is also within that range. Therefore, if jumps of several to several tens of tracks are performed at intervals of several milliseconds as described above, the reproduced signal will have a waveform that is disturbed by several hundred microseconds every few milliseconds, and if the disturbance is of this degree, the sync servo will It is fully possible to control the linear velocity by Therefore, during multi-jump reverse, disk rotation is controlled by the sink servo. Perform a multi-jump reverse and compare addresses between t ₉ and t ₁₀ , and if you find that the search address has been exceeded,
At transition to _t10 , the operation of jumping forward one track (jumping to an adjacent track in the forward direction) and comparing addresses is performed until the search address is reached. Of course, the rotation is controlled by the sync servo during the jump forward period as well.
After reaching the search address at t ₁₁ ,
If PLAY mode is specified, the quartz servo will be used for normal playback, and if PAUSE mode is specified, it will be a pause operation. What is a pose action?
The operation of jumping and reversing one track at that search address point is repeated. During the pose movement, one rotation time is several 100ms like this
The playback signal is only disturbed by a few hundred microseconds, which is the jump time for each jump, and with this level of disturbance, it is sufficient to control the rotation with a quartz servo, and therefore the disk rotation The control may be switched to quartz servo or may remain as sync servo.

Note that each step in FIG. 13 is repeated until the search address is exceeded.

Note that the example shown in Fig. 13 is just one example, and various modifications are possible.
It is significant that it uses HLD operation and uses frame sync servo operation when reading an address.

As described above, according to the present invention, if frame sync demodulation is not performed during frame sync servo operation, disturbance is forcibly applied to the clock extraction PLL to enable it to lock to a normal clock frequency. Therefore, it is possible to extract a normal clock signal from now on, and it is convenient to shift to quartz servo.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a partial format example of an EFM signal, FIG. 2 is a block diagram for an embodiment of the present invention, FIG. 3 is a block diagram of a frame sync servo circuit, and FIG. 4 is a diagram showing a frame sync servo circuit. A block diagram of the frame sync servo circuit, Figure 4 is a diagram explaining the operation of the circuit in Figure 3, Figure 5 is a characteristic diagram of the frame sync servo, Figure 6 is a block diagram of the PLL, and Figure 7 is a diagram explaining the operation of the circuit in Figure 3. The operating waveform diagram of the circuit shown in the figure, Figure 8 is the frame sync signal detection circuit diagram, Figure 9 is the PLL sweep circuit diagram,
Figure 10 is a diagram explaining the circuit operation of Figure 9;
1 and 12 are flowcharts showing the operation at the time of disk startup, and FIG. 13 is a diagram explaining an example of the operation at the time of search. Explanation of symbols of main parts, 1... System controller, 2... Pickup, 4... Frame sync servo device, 6... Spindle driver, 7...
PLL, 8...Demodulator, 9...RAM, 14...Phase comparator.

Claims (1)

[Claims] 1 A rotation control system for a recording disk on which a digital signal is recorded, including self-clock information of a predetermined frequency and a synchronization signal in which the maximum interval is inverted n times (n is an integer of 1 or more), which While detecting a period n times the reversal interval and controlling the rotation of the disk using the detection signal, the PLL circuit, which can lock within a predetermined frequency range including the frequency of the clock information, outputs the reproduction signal. A signal is supplied to extract the clock signal, the extracted clock signal is used to demodulate the synchronization signal, and if the synchronization signal is not demodulated, the oscillation frequency of the voltage controlled oscillator of the PLL circuit is determined. A method characterized by forced sweep.