JPH037962Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an MIS type semiconductor memory device that shortens access time by increasing the transfer speed of information from a bit line to a data bus.

[Technical background] Generally, in a MIS type semiconductor memory device, a memory cell selected by a row decoder among memory cells arranged in a matrix is connected to a corresponding bit line, and the memory cell selected by a row decoder is connected to a corresponding bit line. It is connected to a data line through a transfer gate controlled by a column decoder, and read data is taken out from the data line. Therefore, the performance of the transfer gate, such as the rise speed when the transfer gate changes from off to on, affects the access time.

[Problems to be solved by the prior art and the invention]

In a conventional MIS type semiconductor memory device, an enhancement type transistor having the same threshold voltage as other circuit parts of the memory device has been used as a transfer gate provided between a bit line and a data line. Therefore, in the conventional type, the threshold voltage of the transistor constituting the transfer gate is high, and therefore, unless the gate-source voltage of the transistor is sufficiently large, the transistor will not conduct. The transistor did not conduct until the applied column select signal was at a fairly high level. As a result, the transfer speed of information from the bit line to the data line becomes slow, resulting in an inconvenience that the access time of the semiconductor memory device becomes long.

The purpose of the present invention is to construct a transfer gate provided between a bit line and a data line in an MIS type semiconductor memory device using an enhancement type transistor with a low threshold value, in view of the problems with the conventional type mentioned above. Based on this idea, the aim is to increase the speed of information transfer from the bit line to the data line and shorten the access time of the storage device.

[Means for solving problems]

And this purpose, according to the present invention, includes a plurality of bit lines, a plurality of word lines, flip-flop type memory cells arranged at the intersections of the bit lines and the word lines, a data bus line, and each of the bit lines. and the data bus line, and by turning on the transfer gate transistors, the information signal from the memory cell is transferred to the data via the bit line. An MIS type semiconductor memory device that reads data onto a bus line, characterized in that the transfer gate transistor is configured with an MIS type transistor having a lower threshold voltage than enhancement type transistors used in other circuit parts in the memory device. This is achieved by providing a MIS type semiconductor memory device that performs the following steps.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 partially shows the configuration of an MIS type semiconductor memory device according to an embodiment of the present invention. In the figure, BL, is a pair of bit lines, and the bit lines BL and BL are connected to the load transistor Q ₁ , respectively.
and is tangential to the power supply V _CC through Q ₂ . Transistors Q ₃ to Q ₆ and resistors R ₁ and R ₂ constitute a so-called flip-flop type memory cell, and transistors Q ₃ and Q ₄ constitute a gate circuit connecting the memory cell and the bit line pair BL. . The transistors Q ₃ and Q ₄ are word
WL, and word line WL is connected to row decoder RD. Further, the bit line BL is tangentially connected to each data line DB forming a data line pair via transistors _Q7 and _Q8 forming a transfer gate, respectively. The gates of transistors _Q7 and _Q8 are both tangential to the column decoder CD. Also, the gate-source voltage threshold of transistors _Q7 and _Q8 is
It is lower than the threshold voltage of enhancement mode transistors used in other circuit parts of the semiconductor memory device. That is, although the threshold voltage of an enhancement type transistor generally used in a semiconductor memory device as shown in FIG. 1 is, for example, _0.7 to _0.9V , The threshold value is set to a value lower than this value and greater than or equal to 0.

The operation of the circuit shown in FIG. 1 will be explained. When reading information from a certain memory cell, the corresponding row decoder
The word line WL is set to high level by RD, and the signal from the memory cell is taken out to the bit lines BL and BL through transistors _Q3 and _Q4 , and the column decoder CD outputs the signals from transistors _Q7 and composing the transfer gate. _Q8 is made conductive and information from the memory cell is taken out from the bit line BL and data line DB and output via a sense amplifier (not shown).

In this case, as shown in FIG. 2a, for example, in the conventional type, the threshold voltages of transistors _Q7 and _Q8 are large, so the voltage of the memory cell is taken out by the row decoder RD to the bit lines BL and From the point at which the voltages on the bit lines BL and BL cross, the voltage change on the bit lines changes to the data lines DB and DB.
The time td ₁ from when data is transferred to DB until the voltages of data lines DB and DB intersect is quite long.
That is, only when the output voltage Y of the column decoder CD rises and the difference with the voltage of the bit line BL exceeds the gate-source voltage threshold of transistors _Q7 and _Q8 , transistors _Q7 and _Q8 become conductive. death,
The voltage on the bit line is transferred to the data line, but because the gate-source voltage thresholds of transistors _Q7 and _Q8 are large, the difference between the output voltage of the column decoder CD and the voltage on the bit line BL is quite large. Transistors Q ₇ and Q ₈ do not conduct until Therefore, transistors Q ₇ and Q ₈ become conductive only after a considerable amount of time has elapsed since the output voltage Y of the column decoder CD began to rise, resulting in a considerably long access time.

On the other hand, in the semiconductor memory device according to the embodiment of the present invention, the threshold voltages of the transistors _Q7 and _Q8 are set low, so that the output voltage of the column decoder CD is reduced as shown in FIG. 2b. Within a short time after Y starts rising, the difference between the voltage Y and the voltage on the bit line BL becomes larger than the threshold voltage of the transistors Q ₇ and Q ₈ , and the transistors Q ₇ and Q ₈ immediately start conducting. . Therefore, the voltage change on bit line BL and data line DB and
The time td ₂ from the bit line voltage intersection to the data line voltage intersection becomes very small.
In addition, by reducing the threshold voltages of transistors _Q7 and _Q8 , the gm of the transistor can be increased compared to the conventional type for the same gate-source voltage. Information transfer speed can be further increased. Although the above description has been given of an example of a MIS static random access memory, the present invention is not limited to this and can be applied to any memory device that includes a transfer gate transistor between a bit line and a data bus. it is obvious.

[Effect of idea]

As described above, according to the present invention, the transfer speed of information from the bit line to the data bus can be increased without changing the circuit configuration at all, and the access time of the semiconductor memory device can be shortened.

[Brief explanation of drawings]

FIG. 1 is a partial block circuit diagram showing the configuration of an MIS type semiconductor memory device according to an embodiment of the present invention, and FIGS. 2a and 2b are semiconductor memories according to a conventional type and an embodiment of the present invention, respectively. FIG. 3 is a waveform diagram for explaining the operation of the device. BL,...Bit line, WL...Word line,
DB,...Data bus, _Q1 , _Q2 ...Load transistor, _Q3 , _Q4 , _Q5 , _Q6 ...Memory cell transistor, _Q7 , _Q8 ...Transfer gate transistor, _R1 , _R2 ...Load resistance, RD...Row decoder, CD...Column decoder.

Claims (1)

[Scope of utility model registration request] A plurality of bit lines, a plurality of word lines, a flip-flop type memory cell disposed at the intersection of the bit line and the word line, a data bus line, and a plurality of memory cells arranged between each bit line and the data bus line. A connected transfer gate transistor is provided, and by turning on the transfer gate transistor, an information signal from the memory cell is read out to the data bus line via the bit line.
An MIS type semiconductor memory device, characterized in that the transfer gate transistor is composed of an MIS type transistor having a lower threshold voltage than enhancement type transistors used in other circuit parts in the memory device. Storage device.