JPH0378083A - Double precision arithmetic system and arithmetic unit for sum of products - Google Patents

Abstract

PURPOSE:To decrease the number of arithmetic cycles by adding partial products whose digits are matched, each other in one arithmetic cyle while executing shift processing to the partial product. CONSTITUTION:Data read from data buses 4 and 5 can be parallelly supplied to a multiplier 6 and an arithmetic theory computing element 7 and the arithmetic result of the multiplier 6 is held in a buffer register 8 for one instruction cycle period and applied to the computing element 7. The computing element 7 executes addition and subtraction, etc., to the data, which are selectively applied from the register 8 or a data bus 3 through a selector 15, and a result is once held in accumulators 9A and 9B and returned to the bus 3 afterwards. When a carry is generated in the addition processing of the computing element 7 and the state is held in carry flags 16A and 16B and transmitted at prescribed timing as the carry signal of the prescribed input bit of the computing element 7. Thus, the number of the arithmetic cycles can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to arithmetic techniques in microprocessors, particularly to double-precision arithmetic systems and multiply-accumulate arithmetic devices, and relates to techniques that are effective when applied to, for example, digital signal processing processors.

[Prior art]

Digital signal processing includes filtering, equalization, modulation,
Digital signal processing processors, which are used for Freeier transform, signal characteristic parameter extraction, prediction, image enhancement, etc., are specialized processors for the purpose of digital signal processing, and have high processing capabilities in the application field of digital signal processing. Therefore, it is necessary to separate the instruction control system and the arithmetic execution system so that each cycle of instruction fetch, instruction decode, and arithmetic execution can be processed in parallel in a pipeline manner, or to provide separate multipliers and adders. There is a contradictory relationship between arithmetic speed and arithmetic accuracy in such digital signal processing processors, which have a unique architecture that makes it possible to execute frequently occurring multiply-accumulate operations in parallel. Floating-point arithmetic is desirable for increasing the number of points, but it comes at the cost of computation speed, and if fixed-point arithmetic is used to achieve high-speed computation, there is a tendency for computation accuracy to be sacrificed. Therefore, real-time processing can be ensured by fixed-point arithmetic, and double-precision arithmetic can be performed when high arithmetic precision is required.For example, when the single-precision data word length is 16 bits,
3 by double precision multiplication to obtain higher arithmetic precision.
When multiplying 2-bit data by 32-bit data, multiplication is required to obtain partial products between single-precision 16-bit data, and shift operations are required to align digits or decimal points for partial products. , and addition processing is required for the digit-aligned partial products. Conventionally, this shift operation is performed by an arithmetic shift of an arithmetic logic unit, and this arithmetic shift is performed by executing an independent arithmetic shift instruction apart from an addition instruction.

An example of a document describing digital signal processing processors is "Hitachi Digital Signal Processor HD61810B User's Manual" (1978).
(Published by Hitachi, Ltd., January 2015).

[Problem to be solved by the invention]

However, in double precision multiplication to obtain arithmetic precision greater than the data word length of single precision, multiplication of partial products by single precision, digit alignment or decimal point alignment for partial products, and partial products aligned by one digit When addition processing becomes necessary, the number of calculation cycles increases significantly compared to single-precision multiplication, and there is a problem that it cannot meet the demands for high-speed calculation.0For example, when processing 32-bit data AB (
When multiplying the 32-bit data CD (A is the upper 16 bits, B is the lower 16 bits) and 32-bit data CD (C is the upper 16 bits, D is the lower 16 bits) in double precision, 32-bit partial products BXD, AXD, and BXC are respectively generated. , AXC are required, as well as one cycle of addition of partial products AXD and BXC with the same decimal point positions, a shift calculation cycle between this addition result and the partial product BXD, and subsequent cycles of both. 1 cycle of addition, and 1 partial product A
A shift calculation cycle between the addition result of XD and BXC and the partial product B×D, and one cycle of subsequent addition of both are required, resulting in a total of 9 cycles of calculation processing, and single-precision multiplication. The number of calculation cycles is nine times that of .

An object of the present invention is to provide a double-precision arithmetic method that can reduce the number of arithmetic cycles in fixed-point arithmetic. Another object of the present invention is to provide a product-sum calculation device that can perform double-precision calculations with a small number of calculation cycles.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, in a double-precision arithmetic method for multiplying data with a word length multiple times the unit word length, there is a multiplication cycle to obtain partial products between unit word lengths, and an addition cycle between partial products. The addition cycle includes:
During that one operation cycle, a digit alignment shift process necessary before adding the partial products is included, and the shift process is performed by a selector provided on one input side of the adder for the unit word length. This process gives an instruction to shift to the right, shift to the left, or simply pass.

In the double-precision arithmetic operation, it is necessary to transmit the carry to a predetermined digit and reflect it in the subsequent addition process for a carry generated in the addition process between partial products. At this time, in order to facilitate the carry transfer operation, it is preferable to include an instruction for such carry transfer processing in the corresponding addition instruction.

In addition, in order to configure a product-sum operation device that performs the above-mentioned double-precision operation, including a multiplier and an adder that can perform multiplication of data having a word length multiple times the unit word length by a product-sum operation,
A selector is placed on a transmission path that leads the calculation result of the multiplier to one input of the adder, or a transmission path that leads the calculation result of the adder to the other input of the adder, and Before the addition process, the shift process is performed by selecting a right shift, a left shift, or a simple pass by the unit word length.

At this time, in order to enable the addition cycle and the multiplication cycle to be executed in parallel, it is preferable to provide a data buffer that holds the operation result of the multiplier for one instruction cycle period and supplies it to the adder.

[For production]

According to the above-mentioned means, in the addition cycle, an independent shift operation cycle for digit alignment is performed by performing addition of digit-aligned partial products in one operation cycle while performing a shift process on the partial products. This serves to reduce the number of calculation cycles in fixed-point double-precision calculations.

Further, in the product-sum operation device capable of performing multiplication of data having a word length multiple times the unit word length by a product-sum operation, the selector arranged on the data transmission path to the adder is configured to transmit data to the adder. It acts to perform digit alignment for partial products during data transfer, thereby omitting an independent shift operation cycle for digit alignment, and thereby performing a product-sum operation that performs fixed-point double-precision multiplication with a reduced number of operation cycles. This is to achieve an arithmetic device.

〔Example〕

FIG. 1 shows a digital signal processor that is an embodiment of the present invention. The digital signal processing processor 1 shown in the figure is formed on a single semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited.

The digital signal processing processor 1 shown in FIG. 1 basically has an instruction control system and an arithmetic system separated in order to enable high-speed processing of multiply-accumulate operations in real time, and handles instruction fetch, instruction decoding, and data transfer. It is now possible to execute instructions such as and operations using parallel pipeline processing.

The arithmetic system includes a multi-board RAM (Random Access Memory) 2A for storing variable data etc. in digital signal processing such as filtering processing, and a coefficient ROM (Read) for storing coefficient data used in digital signal processing.・It has data memory 2 including 2B (only memory), and multiple data buses 3 to 5.
are connected to each port of the data memo 2 to enable data transfer in parallel, and are further provided with separate multipliers 6 and arithmetic and logic units 7 to perform frequently used multiply-accumulate operations in parallel. is made possible. For example, the write port of the multiport RAM 2A (1) is coupled to the data bus 3. The two read ports of the multi-board RAM 2A and the two read ports of the coefficient ROM 2B are connected to data buses 4 and 5, respectively, and the data read from the data buses 4 and 5 is sent to the multiplier 6 and the arithmetic logic unit 7. can be supplied in parallel. The operation result of the multiplier 6 is held in the buffer register 8 for one instruction cycle period and is applied to the arithmetic and logic unit 7. This arithmetic logic operator 7
The arithmetic and logic unit 7 performs addition and subtraction on data selectively provided from the buffer register 8, data memory 2, and data bus 3 via the selector 15. After being held, it is returned to the data bus 3.

When a carry occurs in the addition process by the arithmetic and logic unit 7, its status is the carry flag 16A.

16B, and is transmitted as a carry signal of a predetermined input bit of the arithmetic and logic unit 7 at a predetermined timing. The selector 15 and carry flags 16A and 16B will be described in detail later.

The data bus 3 also includes an address pointer 10.
．． Status register 11, control register 12
, and an input/output circuit 14 are connected thereto.

The address pointer 10 is a multi-board RAM 2A.
The address information is provided via the data bus 3 or by information contained in the address field of the instruction. The status register 11
holds a flag that reflects the internal state of the digital signal processor 1, such as the data input/output state by the input/output circuit 14 and the interrupt mask state. The control register 12 is a digital signal processing processor 1.
maintain conditions to control the behavior of The input/output circuit 14 exchanges parallel data DATA and serial data Sin and 5out with external modules such as a host processor and a serial interface circuit (not shown), and includes an input register and an output register in parallel or serial format.

The instruction control system includes, but is not particularly limited to, a program counter 20 that holds the address of the instruction to be executed first, and a stack register 21 that saves the value of the program counter 20 when an interrupt occurs and a subroutine jump instruction is executed. , an instruction ROM 22 that holds the operating program of the digital signal processor 1 as a plurality of microinstruction sequences and is addressed by the output of the program counter 20, an instruction register 23 that fetches instructions output from the instruction ROM 22, and this instruction register 23. An instruction decoder and controller 24 that decodes instructions output from the controller and generates various internal control signals, etc.
, and an address control circuit 25.

The address control circuit 25 stores external control information 26 that is regarded as an external interrupt signal, internal control information 27 for instructing conditions for one branch, and information such as a branch included in an instruction held in the instruction register 23. Address information 28 for an unconditional branch is supplied, branch destination attrace information according to the information is given to the program counter 20, and when a -cut branch is not instructed, an increment operation is performed for the program counter 20. instruct.

The digital signal processor 1 of this embodiment is as follows.

Although there are no particular restrictions, floating-point operations and fixed-point operations are performed;
In addition to single-precision operations on 6-bit unit word length data, double-precision operations are performed on data with a maximum precision of 32 bits. Multiplication using double-precision operations (hereinafter simply referred to as double-precision multiplication) will be explained below. .

FIG. 2 shows the flow of data during double precision multiplication in the arithmetic system. The number of bits of data to be transmitted is added to the bus connecting each functional block.

FIG. 3 shows a conceptual diagram of double-precision multiplication of 32-bit data AB consisting of upper 16 bits A and lower 16 bits B and 32-bit data CD consisting of upper 16 bits C and lower 16 bits D. . In such double precision multiplication, four partial products BXD are obtained by multiplying unit word lengths.
, AXD, BXC, and AXC are obtained, and their partial products are digit-aligned and added, thereby obtaining a 64-bit multiplication result.

The selector 15 is specially provided for digit alignment between the partial products, and according to this embodiment.

Before addition processing by arithmetic logic operation II7, 16-bit right shift (2-”) and 16-bit left shift (2+1@) for the 32-bit input data by the unit word length.
, or just pass (2').

In particular, the simple pass operation is a mode that takes other single-precision operations and floating-point operations into consideration.

FIG. 4 shows an example of the selector 15. This selector 15 includes three gate circuits 15A to 15G each having 32 bits as a unit.
Bit data D31-D0 are given. The logic value 0 is given to the upper 16 bits of the gate circuit 15A, and the upper 16 of data D, 1 to D0 are given to the lower 16 bits.
Bits D1, .about.D0 are provided. The gate circuit 15
32-bit data D, □ to D are given to B as they are. The upper 16 bits of the gate circuit 15G contain data D, and the lower 16 bits D of □ to Dll.

~D, and its lower 16 bits are given a logic value of 0. When the gate circuit 15A is selected, the output of the selector 15 is the 32-bit input data D, 1 to D.
, shifted to the right by 16 bits, and when the gate circuit 15C is selected, the output of the selector 15 is 3.
The value is obtained by shifting the 2-bit input data D31 to D6 to the left by 16 bits. When the gate circuit 15B is selected, 32-bit data D, 1-D is output as is without being subjected to shift processing.

The digital signal processor 1 of this embodiment has a horizontal microinstruction system so that multiple operations are executed during the same instruction cycle in order to improve the throughput of arithmetic instructions, and the instructions are stored in the instruction R○M 22. has been done.

Operations that can be executed in parallel in one instruction cycle are multiplier 6.
Multiplication by 0, which is used for operations, operations of the arithmetic and logic unit 7, read/write of the data memory 2, etc.

It is possible to operate in every instruction cycle, and 1 multiplier 6
Multiplication is performed when the input data of is selected by the instruction.The 0 multiplication result is stored in the buffer register 8, and the arithmetic and logic operator 7 performs addition and subtraction using the multiplication result in the next instruction cycle. become. This allows multiplication and addition to be executed in parallel in a pipelined manner,
The product-sum operation is apparently performed in one instruction cycle.

FIG. 5 shows an example of an instruction format used for double precision multiplication. This command format is not particularly limited, but includes an operation code designation field 3O for instructing the operation of the arithmetic and logic unit 7, an input designation field 31 for the arithmetic and logic unit 7, an input/output selection designation field 32 for the accumulators 9A and 9B, and a selector 15. operation specification field 33, carry flag transmission specification field 3
4, the addressing field 35 of the data memory 2, etc.

Next, the double precision multiplication procedure will be explained according to the example shown in FIG. FIG. 6 shows an example of the multiplication procedure. In the multiplication procedure shown in FIG. 6, the double-precision multiplication of 32-bit data AB and CD requires five instruction cycles CY01 to CYC5.
achieved by.

■Instruction cycle CYC1 The upper 16 bits A of the 32-bit data AB and the lower 16 bits D of the 32-bit data CD are supplied to the multiplier 6 to calculate the partial product AXD of both, and the result of the calculation is stored in the buffer. It is held in register 8.

■Instruction cycle CYC2 The operation result of the partial product AXD held in the buffer register 8 in the instruction cycle CYCI is directly passed through the non-operation arithmetic and logic unit 7 to the accumulator 9A.
sent to. In parallel with this, the lower 16 bits B of the 32-bit data AB and the upper 16 bits C of the 32-bit data CD are supplied to the multiplier 6, and the partial product B of both is supplied.
XC is calculated and the result of the calculation is held in buffer register 8.

■Instruction cycle CYC3 The operation result of the partial product BXC held in the buffer register 8 in the instruction cycle CYC2 and the instruction cycle CYC
2, the partial product AXD stored in the accumulator 9A
The arithmetic and logic unit 7 adds the result of the operation. At this time, since the decimal point positions of both partial products AXD and BXC match, the data led from the accumulator 9A to the arithmetic and logic unit 7 passes through the selector 15, but the selector 15 has no input data through state. Selected. As a result, both partial products AXD and BXC are added as they are, and the addition result is stored in the accumulator 9A.

Furthermore, if a carry occurs in this addition process, the carry sets the carry flag 16B. In parallel with this addition process, the lower 16 bits B of the 32-bit data AB and the lower 16 bits D of the 32-bit data CD are
are supplied to the multiplier 6 to calculate their partial product BXD, and the result of the calculation is held in the buffer register 8.

■Instruction cycle CYC4 The operation result of the partial product BXD held in the buffer register 8 in the instruction cycle CYC3 and the instruction cycle CYC
3, the data stored in the accumulator 9A (partial product A
The result of addition of XD and partial product BXC) is added by the arithmetic and logic unit 7, but at this time, the 16-bit left shift operation has been selected in the selector 15 by the instruction.
The decimal point position of the data supplied from the accumulator 9A through the selector 15 is matched with the decimal point position of the partial product BXD. Therefore, the data stored in the accumulator 9A whose decimal point position is shifted from the data stored in the data buffer 8 is automatically digit-aligned by the selector 15 while being supplied to the arithmetic and logic unit 7 in the addition cycle.
It is added to the data stored in the data buffer 8. The addition result is stored in another accumulator 9B. Further, if a carry occurs in this addition process, the carry sets the carry flag 16A. In parallel with this addition process, the upper 16 bits A and 32 of the 32 bit data AB
The upper 16 bits C of the bit data CD are input to the multiplier 6.
The partial product AXC of both is calculated, and the result of the calculation is held in the buffer register 8.

■Instruction cycle CYC5 The calculation result of the partial product AXC held in the buffer register 8 in the instruction cycle CYC4 and the instruction cycle CYC
3, the data stored in the accumulator 9A (partial product A
The result of addition of XD and partial product BXC) is added by the arithmetic and logic unit 7, but at this time, since the selector 15 has been instructed to perform a 16-bit right shift operation,
The decimal point position of the data supplied from the accumulator 9A through the selector 15 is automatically adjusted to the decimal point position of the partial product AXC. Therefore, the accumulator 9 has a decimal point position shifted from the data stored in the data buffer 8.
The data stored in A is automatically digit-aligned by the selector 15 while being supplied to the arithmetic and logic unit 7 in the addition cycle, and added to the data stored in the data buffer 8.

At this time, the contents of the carry flags 16A and 16B are transmitted to the arithmetic and logic unit 7 and used to carry the corresponding bits. In this explanation, the carry flag 16A is used as a carry signal for the least significant bit in the arithmetic logic unit 7, and the carry flag 16B is used as a carry signal for the 16th bit from the lowest order. This addition result is stored in accumulator 9A.

These instruction cycles CYCI to CYC5 result in 3
The result of double-precision multiplication of 2-bit data AB and CD is 2.
accumulators 16A and 16B. The lower 32 bits are stored in accumulator 9B, and the upper 32 bits are stored in accumulator 9A. The number of calculation cycles required for this double-precision multiplication is 4 cycles of multiplication to obtain the partial product and 3 cycles of addition including digit alignment processing.
At this time, if the digit alignment process is performed by an arithmetic shift using the arithmetic and logic unit 7 as in the past, at least two additional shift operation cycles are required. The number of cycles also increases.

According to the above embodiment, the following effects can be obtained.

(1) When 32-bit data is mutually multiplied by a multiplication cycle to obtain a partial product between unit word lengths of 16 bits and an addition cycle between partial products, the values of accumulators 9A and 9B are calculated using arithmetic logic. A 16-bit right shift, a 16-bit left shift, or a simple pass instruction is given to the selector 15 placed on the data transmission path returning to the arithmetic unit 7, and necessary information is given to the selector 15 disposed on the data transmission path returning to the arithmetic unit 7. Since digit alignment shift processing is included, addition of digit aligned partial products is performed in one operation cycle while performing shift processing on one partial product, and an independent shift operation cycle for digit alignment, for example, arithmetic logic operator 7 It is possible to omit the arithmetic shift calculation cycle that uses fixed-point numbers, thereby reducing the number of calculation cycles for fixed-point double-precision calculations. You can get the equipment.

(2) Based on the above effects, a digital signal processing processor that adopts an architecture that prioritizes speeding up calculations through single-precision fixed-point calculations and performs double-precision calculations only when high calculation precision is required. It is possible to achieve an improvement in the overall processing power of a microprocessor or microcomputer.

(3) In the above-mentioned double-precision arithmetic, it is necessary to transmit the carry that occurs in the addition process of the partial product to a predetermined digit and reflect it in the subsequent addition process. By performing the carry transfer process according to the corresponding addition instruction, the operation can be made easier or more flexible.

(4) Data buffer 8 that holds the operation result of the multiplier 8 for one instruction cycle period and provides it to the arithmetic and logic operator 7.
By providing this, it becomes possible to execute addition cycles and multiplication cycles in parallel in a pipeline manner, thereby further speeding up double precision multiplication.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited thereto and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, the selector 15 is arranged so as to shift the values of the accumulators 9A and 9B, but it may be arranged so as to shift the value of the buffer register 8 as shown in FIG. Note that when adopting such an arrangement of the selector 15, the shift direction and the partial products to be shifted will be different from the calculation procedure shown in FIG. 6, but the number of calculation cycles should be the same as in the above embodiment. I can do it.

Furthermore, the selector is not limited to the configuration of the above embodiment; for example, as shown in FIG.
Buffer register 8 that holds 2-bit data as is
In addition, the upper 16 bits of the 32-bit data output from the buffer register 40 and the 1 multiplier 6 are stored in the lower order, and logic 0 is forcibly inserted into the upper 16 bits. It is also possible to provide a buffer register 41 in which bits are stored in the upper part and a logic O is forcibly inserted into the lower 16 bits.

Further, the double-precision operation is not limited to multiplication of 32-bit data by 32-bit data, but can be used for operations between data having an appropriate number of bits multiple times the unit word length.

Furthermore, double-precision arithmetic is not necessarily limited to the method of performing multiplication and addition in a pipeline manner as in the above embodiment.

In the above explanation, the invention made by the present inventor was mainly applied to a digital signal processing processor, which is the background field of application, but the present invention is not limited thereto, and It can also be widely applied to computers, microprocessors, etc.

The present invention can be applied to at least double-precision calculations and even product-sum calculations.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, when performing double-precision arithmetic using a multiplication cycle to obtain partial products between unit word lengths and an addition cycle between the partial products, the necessary digit alignment shift processing before addition of the partial products is added to the addition cycle. , and the shift process is performed by giving an instruction to right shift, left shift, or simply pass by the unit word length to a selector provided on one input side of the adder. In the addition cycle, addition of partial products whose digits have been aligned while performing shift processing on the partial products is performed in one operation cycle, eliminating the need for an independent shift operation cycle for digit alignment. This has the effect of reducing the number of calculation cycles in precision calculation.

In the double-precision arithmetic operation, when a carry generated in the addition process between partial products is transmitted to a predetermined digit and reflected in the subsequent addition result, an instruction for the carry transmission process is included in the corresponding addition instruction. This makes it possible to facilitate the carry transfer operation.

a transmission path that leads the calculation result of the multiplier to one input of the adder in a product-sum calculation device including a multiplier and an adder;
Alternatively, a selector is placed in the transmission path that leads the operation result of the adder to the other input of the adder, and this selector is shifted to the right, shifted to the left, or simply passed by the unit word length before the addition processing by the adder. By selecting and enabling shift processing, the selector performs digit alignment for the partial product during data transfer to the adder during fixed-point double-precision arithmetic, and thereby performs an independent shift for single-digit alignment. This has the advantage that arithmetic cycles can be omitted, thereby providing a product-sum arithmetic device that performs fixed-point double-precision arithmetic operations with a small number of arithmetic cycles.

By providing a data buffer that holds the operation result of the multiplier for one instruction cycle period and supplies it to the adder, addition cycles and multiplication cycles can be executed in parallel, further speeding up double-precision operations. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a digital signal processor that is an embodiment of the present invention. FIG. 2 is a block diagram showing the shape of data during double-precision multiplication in the arithmetic system of the digital signal processor shown in FIG. 1, and FIG. 3 is a conceptual diagram of the double-precision multiplication procedure. FIG. 4 is a block diagram of m selectors. FIG. 5 is a format diagram of m instructions used for double precision multiplication. FIG. 6 is a flowchart of an example of a double-precision multiplication procedure, and FIG. 7 is a block diagram showing another example of the arrangement of selectors in the product-sum operation system. FIG. 8 is a block diagram showing another configuration example of the selector in the product-sum calculation system. DESCRIPTION OF SYMBOLS 1... Digital signal processing processor, 3... Data bus, 6... Multiplier, 7... Arithmetic logic unit, 8
...Buffer register, 9A, 9B...Accumulator, 15...Selector, 15A-15C...Gate circuit, 16A, 16B...Carry flag, 22.
...Instruction ROM. Figure 2 Figure 3

Claims (1)

[Claims] 1. A double-precision arithmetic method for performing multiplication of data having a word length that is multiple times the unit word length, including a multiplication cycle for obtaining partial products between unit word lengths. and an addition cycle between partial products, and the addition cycle includes a digit alignment shift process necessary before adding the partial products together during one calculation cycle, and the shift process includes a digit alignment shift process that is necessary before performing the addition of the partial products. A double-precision arithmetic method that is performed by giving a right shift, left shift, or simple pass instruction for the unit word length to a selector provided on one input side. 2. The addition cycle includes a process of transmitting a carry generated and held by the previous addition process of partial products to a predetermined digit according to the instruction.
Double precision arithmetic method described. 3. Includes a multiplier and an adder that can perform multiplication of data having a word length multiple times the unit word length by a product-sum operation, and guides the operation result of the multiplier to one input of the adder. A selector is disposed on a transmission path or a transmission path that leads the calculation result of an adder to the other input of the adder, and the selector shifts the right shift by the unit word length and the left shift by the unit word length before addition processing by the adder. A product-sum operation device that performs shift processing by selecting a shift or a simple pass. 4. Claim 3 further comprising a data buffer that holds the operation result of the multiplier for one instruction cycle period and supplies it to the adder.
The product-sum calculation device described above.