JPH0377377A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device having a sufficiently high breakdown strength even if a fine transistor design rule is applied by a method wherein, after a well part is formed as a transistor forming region, ions are implanted in a self-alignment manner to increase the impurity concentration at a channel part. CONSTITUTION:Implanted boron ions and phosphorus ions are subjected to a driving treatment to form a twin-well structure composed of a P-type well 6 and an N-type well 7 on the side of a thick LOCOS oxide film 5. Further, phosphorus ions are additionally implanted into the N-type well 7 in a self- alignment manner with the thick LOCOS oxide film 5 as a mask. If ion implantation energy at that time is so selected as the peak value of the impurity concentration is in the range of 0.3-0.5mum in a substrate, a high impurity concentration region 10 having the impurity concentration not less than 10<17>cm<-3> is formed. Therefore, punch-through can be avoided and a sufficiently high breakdown strength between a source and a drain can be obtained.

Description

Detailed Description of the Invention [Industrial Application Field 1] The present invention relates to a method of manufacturing a semiconductor device, and more specifically, in a method of manufacturing a semiconductor device including a MOS transistor, This relates to improvement of the forming method.

[Prior Art] FIG. 3 fal to dl shows this kind of (7) MOSI-transistor according to the conventional method, in particular, CMO8 configuration 1.
FIG. 4 is a cross-sectional view sequentially showing the manufacturing process of a semiconductor device including a PMOS transistor in FIG.

That is, in the conventional example shown in FIG. 3, the method for manufacturing a semiconductor device is to first deposit a thin oxide film 2 on a p-type silicon substrate l by thermal oxidation. Nitrided i13 by CVD method
Then, the area other than the area that will later become the N-well portion is covered with a resist pattern 4 by photolithography (see Fig. 3, fal!), and using this resist pattern 4 as a mask, dry etching is performed. After the nitride film 3 is selectively removed to form an opening, phosphorus ions are implanted into the removed portion (FIG. 3(b)).

Next, after removing the resist pattern 4 used as the mask, the nitride film 3 is used as an oxidation-resistant mask, and 110
By performing thermal oxidation and drive treatment at a high temperature of about 0°C to 1200°C, a thick oxide layer 1 [5] is formed together with the N-well part 7, which will be the formation region of the PMOS transistor (FIG. 3(C)), and then Locos After forming a thick field oxide film 8 for isolation between elements by the method, the following steps are performed.
As is well known, the gate electrode, source/drain, etc. of the PMOS transistor are formed, but at this time, the PMOS transistor
By implanting boron ions into the channel 9 of the S transistor (see Figure 4(d)), an appropriate threshold voltage can be obtained. PMOS with an impurity profile of
They manufacture transistors.

[Problems to be Solved by the Invention] The manufacturing of the device configuration according to the conventional example described above has mainly been applied to transistors with a gate length of about 1.5 μm or more, but the current design rules for transistors are As the size of transistors becomes sub-micron, down to about 1.0 μm or less, it becomes difficult to obtain desired transistor characteristics using the conventional manufacturing method described above.
In some cases, especially in the aforementioned PMOS transistors, the deterioration of the source/drain withstand voltage due to bunch-through due to short channelization becomes noticeable, which hinders the miniaturization of device configurations. .

This invention was made to solve these conventional problems, and its purpose is to make it possible to obtain a sufficiently high source-drain breakdown voltage even under the design rules of minute transistors. did. An object of the present invention is to provide a method for manufacturing this type of semiconductor device.

[Means for Solving the Problems 1] In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes: 1. After forming a well portion as a transistor formation region, impurities are implanted in a channel portion by self-alignment ion implantation. It is designed to increase the concentration.

That is, the present invention provides a method for forming a well portion serving as a MOS transistor formation region in a method of manufacturing a semiconductor device including a MOS transistor, in which a portion other than the MO3I-transistor formation region on a semiconductor substrate of a first conductivity type is formed. selectively forming a thick field oxide film by the LOCO3 method; using the field oxide film as a mask, ion-implanting a second conductivity type impurity into the MOS transistor formation region; A process of diffusing impurities by high-temperature heat treatment to form a well part, and again using the field oxide film as a mask, applying high energy impurities of a second conductivity type to a region corresponding to the channel part in the well part by self-aligning. This is a method for manufacturing a semiconductor device, characterized in that it includes at least a step of additionally implanting the material.

[Effect 1] Therefore, in the method of the present invention, after forming a well portion as a transistor formation region, impurity ions are additionally implanted using the self-alignment line to increase the impurity concentration in the channel portion where bunch-through is likely to occur. In addition, by adopting simple means during manufacturing, even in the increasingly miniaturized MOS transistor configuration, it is possible to prevent the occurrence of bunch through due to the short channel effect, and to obtain a sufficiently high source-drain breakdown voltage. At the same time, the impurity concentration under the field oxide film for element isolation is also increased, and the isolation breakdown voltage can be improved.

[Example] Hereinafter, an example of the method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 and 2.

FIGS. 1A to 1E are cross-sectional views sequentially schematically showing the manufacturing process of a semiconductor device including a MOS transistor, particularly a PMOS transistor in a CMOS configuration, to which an embodiment of the method of the present invention is applied, Also,
Figures 2 (al and 2) are explanatory diagrams showing the impurity profiles under the channel part (corresponding to the A-A line part) and the field oxide film part (corresponding to the B-811 part) in the same PMOS transistor as above. In the method of the embodiment shown in FIG. 1, the same reference numerals as in the conventional method shown in FIG. 3 indicate the same or corresponding parts.

That is, as shown in FIG. 1 as well, the method for manufacturing a semiconductor device according to this embodiment is to first form a thin oxide film 3 on a p-type semiconductor substrate 1 using a thermal oxidation method and a nitride film 3 using a CVD method. Then, the area that will later become the N-well portion is covered with a resist pattern 4 by photolithography (FIG. 1(a)), and using this resist pattern 4 as a mask, the nitride film is removed by dry etching. After selectively removing the resist pattern 3, boron ions are implanted into the removed portion (FIG. 3(b)). Also, after removing the resist pattern 4 used as the mask, this is LOCO
An oxidation process is performed using the S method to form a thick LOCOS oxide film 5 on the boron implanted region (FIG. 4(C)).

Subsequently, after removing the nitride film 3, the remaining thick LO
By using the GO3 oxide film 5 as a mask, ion-implanting phosphorus into the removed portion and heat-treating it at a high temperature of about 1100° C. to 1200° C., the boron and phosphorus ion-implanted into each of the regions are subjected to a drive treatment. , thick L
A twin well structure is formed with a P well part 6 on the OGO3 oxide 1115 side and an N well part 7 on the removed part side which will be the formation region of the PMO3) transistor, and then the thick LOCO3 oxide 1115 is formed again. Phosphorus is added and ion-implanted into the N-well portion 7 using Selfaline using the film 5 as a mask, and the ion implantation energy at this time is such that the impurity concentration peaks in the substrate from 0.3 to 0. By selecting a value within the range of 5 am, a high concentration region 10 having a high concentration of 1.0"cm-3 or more is formed in the region corresponding to the channel part in the N well part 7. ((d) in the same figure).

After that, a thick field oxide film 8 for isolation between elements is formed by the LOCO3 method, and boron ions are implanted for threshold voltage adjustment corresponding to the channel part 9 of the PMOS transistor (see (e) in the same figure). ), and then the gate electrode, source/drain, etc. of the PMOS transistor are formed using a known flow.

Therefore, I) MO3 produced by this example method
In the I-transistor, the profile at the channel part shown in Fig. 2fa, I is obtained6, so in this case, additional injection of phosphorus using the Selfa line after driving phosphorus at a high temperature causes the inside of the substrate to be increased. 0 in,
The region corresponding to the channel part of 3 to 0.5 μm is lQI
'lc has a high concentration of 3 or more, and thus conventionally the channel length is 1. By increasing the impurity concentration in the region where bunch-through occurred when the size became sub-micron or smaller, bunch-through can be prevented and a sufficiently high source/drain breakdown voltage can be obtained. At the same time, as shown in FIG. 2 fbl, the impurity concentration under the field oxide film is increased compared to the conventional structure, and the amount of elements i! It is possible to achieve the opposite direction of pressure.

Although phosphorus is used as an ion species to improve the impurity concentration in the N-well region in the method of the embodiment, other ion species having similar properties may also be used. In the example method, a twin-well structure is described, but the same effect can be obtained even with a single-well structure.

[Effect of the invention] As detailed above, according to the method of this invention, MO3I
- In a method for forming a well portion that will be a MOS transistor formation region in a semiconductor device including a transistor, after forming a well portion as a transistor formation region by implantation of impurity ions and heat treatment, additional implantation of impurity ions by self-alignment is performed to form a bunch. By increasing the impurity concentration in the channel area where through-through is likely to occur,
By adopting simple means during manufacturing, it is possible to prevent bunch-through caused by short channel effects and obtain sufficiently high source-drain breakdown voltage even in the increasingly miniaturized MOS transistor configuration. Since the high-concentration region in the area is formed by Self-Line, there is no need for an additional photolithography process to form the high-concentration region, and it is only necessary to add an ion implantation process. At the same time, the impurity concentration under the field oxide film for element isolation can also be increased, and the isolation breakdown voltage can be improved, which is extremely useful for miniaturizing MOS transistor structures.

[Brief explanation of drawings]

1 (al to el are sectional views and 2) schematically showing sequentially the manufacturing process of a semiconductor device including a MOS transistor, in particular a PMOSI-transistor in a CMO3 configuration, to which an embodiment of the method of the present invention is applied; FIG. Figure fa)
, (bl is an explanatory diagram showing the impurity profile under the channel part (corresponding to the A-A line part) and the field oxide film part fB-B line part in the same PMOS transistor), and the third Figure (al to dl is P in the same CMOS configuration according to the conventional method)
Each figure is a cross-sectional view schematically showing the manufacturing process of a semiconductor device including a MOS transistor, and FIG.
FIG. 2 is an explanatory diagram showing an impurity profile of a channel portion of a transistor. l...P-type semiconductor substrate, 2...Thin oxide film, 3
...Nitride film, 4...Resist pattern, 5...
...Thick LOCO3 oxide film, 6...P well part, 7
. . . N well portion, 8 . . . thick field oxide film, 9 . . . channel portion, 10 . . . high concentration region portion.

Claims (1)

[Claims] A method for forming a well portion serving as a MOS transistor formation region of a semiconductor device including a MOS transistor, the method comprising:
A step of selectively forming a thick field oxide film by LOCOS method on a conductive type semiconductor substrate in a portion other than the MOS transistor formation region, and using the field oxide film as a mask, forming a thick field oxide film in the MOS transistor formation region. 2
A step of ion-implanting a conductivity type impurity, a step of diffusing the second conductivity type impurity by high-temperature heat treatment to form a well portion, and again using the field oxide film as a mask to form a channel in the well portion. 1. A method of manufacturing a semiconductor device, comprising at least the step of additionally implanting a second conductivity type impurity with high energy into a region corresponding to a portion by self-alignment.