JPH0369131A - Probe for semiconductor integrated circuit test use; manufacture of semiconductor device including test process using same probe - Google Patents

Probe for semiconductor integrated circuit test use; manufacture of semiconductor device including test process using same probe

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Publication number
JPH0369131A
JPH0369131A JP1205301A JP20530189A JPH0369131A JP H0369131 A JPH0369131 A JP H0369131A JP 1205301 A JP1205301 A JP 1205301A JP 20530189 A JP20530189 A JP 20530189A JP H0369131 A JPH0369131 A JP H0369131A
Authority
JP
Japan
Prior art keywords
needle
integrated circuit
probe
semiconductor substrate
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1205301A
Other languages
Japanese (ja)
Inventor
Motoo Nakano
元雄 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1205301A priority Critical patent/JPH0369131A/en
Publication of JPH0369131A publication Critical patent/JPH0369131A/en
Pending legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To ensure a high-reliability contact with pads which are arranged in a pitch of 10mum order on a high-density integrated circuit chip by providing the following: a semiconductor substrate; a plurality of needle-shaped protrusions formed by selectively etching one surface of the substrate; a means to electrically separate the individual needle-shaped protrusions from each other; and a connection means. CONSTITUTION:The following are provided: a semiconductor substrate 10; a plurality of needle-shaped protrusions 11 formed on the semiconductor substrate 10 by selectively etching one surface of the semiconductor substrate 10; a separation means used to electrically separate the individual needle-shaped protrusions 11 from each other; and connections means 12, of a beam lead structure, used to connect the needle-shaped protrusions 11 to an external circuit. For example, a plurality of contactors 11 formed by etching a silicon chip 10 are arranged on one surface of the silicon chip 10 whose size is about the same as that of an integrated circuit chip to be inspected. The individual contactor 11 is provided with needle-shaped protrusions at their tip; they are installed so as to correspond, in a one-to-one manner, to pads on the integrated circuit chip to be inspected; the individual contactor 11 is separated electrically by a means of a P-N junction or the like. A window 14 for visual observation use is formed in the chip 10.

Description

【発明の詳細な説明】 〔概 要〕 ウェハまたはチップ状態の半導体集積回路の試験に用い
るプローブに関し。
[Detailed Description of the Invention] [Summary] This invention relates to a probe used for testing semiconductor integrated circuits in the form of wafers or chips.

高密度集積回路チップに10umオーダの配列されるパ
ッドに対して高信頼度の接触を確保可能とすることを目
的とし。
The purpose is to ensure highly reliable contact with pads arranged on the order of 10 um on a high-density integrated circuit chip.

半導体基板と、該半導体基板の有する一表面を選択的に
エツチングして該半導体基板上に形成された複数の針状
突起と、各々の該針状突起を互いに電気的に分離する分
離手段と、咳針状突起を外部回路に接続するビームリー
ド構造の接続手段とを備えることから構成される装 〔産業上の利用分野〕 本発明は、ウェハまたはチップ状態の半導体集積回路の
試験工程ににおいて用いられる試験用プローブに関する
A semiconductor substrate, a plurality of needle-like protrusions formed on the semiconductor substrate by selectively etching one surface of the semiconductor substrate, and a separating means for electrically separating each of the needle-like protrusions from each other; A device comprising a connecting means having a beam lead structure for connecting a needle-like protrusion to an external circuit. related to test probes.

〔従来の技術〕[Conventional technology]

半導体集積回路の製造工程は、ウェハ上のチップ領域に
半導体集積回路を完成するまでの前工程と、前工程が終
了したウェハをチップごとに分離し2個々のチップのパ
ッケージングを完了するまでの後工程とに大別される。
The manufacturing process of semiconductor integrated circuits consists of a pre-process to complete the semiconductor integrated circuit in the chip area on the wafer, and a process to separate the wafer after the pre-process into chips and complete the packaging of each individual chip. It is broadly divided into post-processing.

前工程が終了した段階におけるウェハ状態の集積回路に
ついて、静的および動的特性試験を行い、後工程を行う
集積回路チップを選別する。上記特性試験において信号
源や電源等の外部回路と被試験集積回路との一時的な電
気的接続を行う手段として、複数の針状金属接触端子を
有するプローブが用いられる。
Static and dynamic characteristic tests are performed on integrated circuits in a wafer state at the stage where the pre-process has been completed, and integrated circuit chips to be subjected to the post-process are selected. In the characteristic test described above, a probe having a plurality of needle-shaped metal contact terminals is used as a means for temporarily electrically connecting an external circuit such as a signal source or a power source to the integrated circuit under test.

上記目的に使用されていた従来のプローブの構造を第6
図に示す。同図(a)に示すように、中央部に直径30
mm程度の貫通孔2が設けられたプリント配線基板1の
上面には、タングステン(囚)から成る先端が針状に尖
った複数の接触子3が固定されている。接触子3として
パラジウム(Pd) 、ベリリウムffiM(Be−C
u)等が用いられることもある。接触子3の先端は、第
6図中)に示すごとく2貫通孔2からプリント配線基板
1の下面に突出するように湾曲しており、各々の接触子
3の最先端が、被検査集積回路チップに設けられている
パッドに対応して9例えば200μmのピッチで四辺形
の辺上に配列されている。接触子3の他端は1プリント
配線基板l上の配線4を通じて、プリント配線基板1の
コネクタ接続端子5に接続されている。
The structure of the conventional probe used for the above purpose was changed to the sixth
As shown in the figure. As shown in the same figure (a), the center part has a diameter of 30 mm.
A plurality of contacts 3 made of tungsten and having needle-like tips are fixed to the upper surface of a printed wiring board 1 in which a through hole 2 of approximately mm size is provided. Palladium (Pd) and beryllium ffiM (Be-C) are used as the contactor 3.
u) etc. may also be used. The tips of the contacts 3 are curved so as to protrude from the two through holes 2 to the bottom surface of the printed wiring board 1, as shown in FIG. They are arranged on the sides of a quadrilateral at a pitch of 9, for example, 200 μm, corresponding to the pads provided on the chip. The other end of the contactor 3 is connected to a connector connecting terminal 5 of the printed wiring board 1 through a wiring 4 on the printed wiring board 1.

試験は、ウェハ状態の集積回路チップ領域の一つが貫通
孔2内に表出するように位置合わせし。
In the test, the wafer was aligned so that one of the integrated circuit chip areas was exposed in the through hole 2.

この集積回路チップの周辺部に設けられている各々のパ
ッドに接触子3の先端を押圧接触させ、コネクタ接続端
子5から試験信号や電源電圧を供給して行う。
The tip of the contactor 3 is pressed into contact with each pad provided on the periphery of the integrated circuit chip, and a test signal and power supply voltage are supplied from the connector connection terminal 5.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来の試験用プローブの主な問題点として。 The main problems with the above conventional test probes are as follows.

次の二点が挙げられる。The following two points can be mentioned.

■集積回路チップ10上のパッドにプローブの接触子3
の先端を押圧接触させると、上記従来構造の接触子3の
先端部は、第7図に示すように、パッド11を擦るよう
な横方向の変位を生じる。点線は移動を起こす前の接触
子3を示す。このために。
■Probe contact 3 is attached to the pad on the integrated circuit chip 10.
When the tip of the contactor 3 of the conventional structure is pressed into contact with the pad 11, the tip of the contactor 3 of the conventional structure is displaced in the lateral direction so as to rub against the pad 11, as shown in FIG. The dotted line shows the contact 3 before movement occurs. For this.

At等の金属層から成るパッド11が損傷を受けやすい
。パッド11の損傷が大きい場合には、後工程における
ボンディングに支障が生じることがある。
Pad 11 made of a metal layer such as At is easily damaged. If the pad 11 is severely damaged, bonding in a subsequent process may be hindered.

と(に、バンプ方式の結線方法により集積回路チップ1
0と外部回路とを接続しようとする場合には。
(Integrated circuit chip 1 is connected using bump type wiring method.)
When trying to connect 0 to an external circuit.

ボンディングが不可能となる場合がある。Bonding may become impossible.

■接触子3は、一端が固定された長さ数cmの複数のタ
ングステン線等の先端部を、200μm程度のピッチで
配列したものであるため、被検査集積回路チップ上のパ
ッドに対して位置精度を確保するのが困難である。また
1機械的強度が充分と言い難く2機械的衝撃を受けたり
あるいは接触子3の先端部に引っ掛けたりすると変形し
やすい。
■The contactor 3 is made by arranging the tips of multiple tungsten wires, etc., each several centimeters long with one end fixed, at a pitch of about 200 μm, so that it can be positioned relative to the pad on the integrated circuit chip to be tested. It is difficult to ensure accuracy. In addition, 1) the mechanical strength is not sufficient, and 2) it is easily deformed when subjected to mechanical shock or caught on the tip of the contactor 3.

しかも、半導体集積回路の大規模化にともなって外部回
路との結線数が増加し、このために、集積回路チップ上
のパッド数も増加する傾向にある。
Moreover, as the scale of semiconductor integrated circuits increases, the number of connections to external circuits increases, and as a result, the number of pads on integrated circuit chips also tends to increase.

その結果、集積回路チップ上においてパッドが占める面
積が増大することになる。パッドの占有率を増大させな
いためには、パッド面積と配列ピッチの%縮小が必要と
なる。
As a result, the area occupied by the pads on the integrated circuit chip increases. In order not to increase the pad occupancy rate, it is necessary to reduce the pad area and arrangement pitch by %.

この要求に対して、集積回路チップ側では、パッド面積
および配列ピッチの縮小は比較的容易であり、また、そ
の寸法制御もμmオーダで可能であるが、第6図のよう
な従来の試験用プローブでは、接触子3の先端部の配列
ピッチと位置精度を上記の要求に応じられるように維持
することが困難であり、従来のような前工程段階での動
作試験の実施が危ぶまれていた。
In response to this requirement, on the integrated circuit chip side, it is relatively easy to reduce the pad area and array pitch, and it is also possible to control the dimensions on the μm order. With the probe, it is difficult to maintain the array pitch and positional accuracy of the tip of the contactor 3 to meet the above requirements, making it difficult to conduct operation tests at the pre-process stage as in the past. .

本発明は上記従来の問題点を解決可能な試験用プローブ
を提供し、かつ、このプローブを用いることにより大規
模集積回路チップの前工程段階での動作試験を可能とす
ることを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a test probe capable of solving the above-mentioned conventional problems, and to make it possible to test the operation of large-scale integrated circuit chips in the pre-processing stage by using this probe.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的は、半導体基板と、該半導体基板の有する一表
面を選択的にエツチングして該半導体基板上に形成され
た複数の針状突起と、各々の該針状突起を互いに電気的
に分離する分離手段と、該針状突起を外部回路に接続す
るビームリード構造の接続手段とを備えたことを特徴と
する本発明に係る半導体集積回路試験用プローブ、およ
び、ウェハまたはチップ状態の半導体集積回路に形成さ
れているパッドに上記のプローブにおける該針状突起を
接触させて試験を行う工程を含むことを特徴とする本発
明に係る半導体装置の製造方法によって遠戚される。
The above object is to electrically isolate a semiconductor substrate, a plurality of needle-like protrusions formed on the semiconductor substrate by selectively etching one surface of the semiconductor substrate, and each of the needle-like protrusions from each other. A probe for testing a semiconductor integrated circuit according to the present invention, comprising a separation means and a connection means having a beam lead structure for connecting the needle-shaped protrusion to an external circuit, and a semiconductor integrated circuit in the form of a wafer or chip. It is distantly related to the method for manufacturing a semiconductor device according to the present invention, which includes a step of performing a test by bringing the needle-like protrusion of the probe into contact with a pad formed in the probe.

〔作 用〕[For production]

本発明の試験用プローブにおける接触子の形成は、半導
体集積回路の製造において確立された微細加工技術を用
いて複数の微細な針状突起状の接触子を微小な配列ピッ
チで一体化形成するするものである。具体的には。
The contacts in the test probe of the present invention are formed by integrating a plurality of fine acicular protrusion-like contacts at a minute arrangement pitch using microfabrication technology established in the manufacturing of semiconductor integrated circuits. It is something. in particular.

■半導体基板のサイドエツチング効果または半導体結晶
の面方位によるエツチング速度差を利用して針状突起状
の接触子を形成する ■各々の接触子は、半導体集積回路における素子分離技
術を利用して互いに電気的に分離されている ■各々の接触子と外部回路との接続は半導体集積回路の
ボンディング技術の一種であるビームリード法を用いて
行われる 等である。
■Using the side-etching effect of the semiconductor substrate or the difference in etching speed due to the plane orientation of the semiconductor crystal, a needle-shaped contact is formed.■Each contact is separated from each other by using element isolation technology in semiconductor integrated circuits. (1) Each electrically isolated contactor is connected to an external circuit using the beam lead method, which is a type of bonding technology for semiconductor integrated circuits.

したがって、被検査集積回路チップにおけるパッドやそ
の配列ピッチの縮小に対応する接触子が高精度で形成さ
れ、ウェハ状態にある大規模集積回路に対しても、従来
と同様に、プローブを用いた動作試験が実施可能となる
。さらに、すべての接触子の先端部が同一平面に維持さ
れるので、被検査集積回路チップ上のパッドに余分な押
圧力を加える必要がない。しかも、従来のプローブにお
けるような押圧時に横方向の変位を生じないために、チ
ップ上のパッドに与える損傷も低減され。
Therefore, contacts that correspond to the reduced pad and arrangement pitch of the integrated circuit chip to be tested can be formed with high precision, and even large-scale integrated circuits in the wafer state can be operated using probes in the same way as in the past. Tests can now be conducted. Furthermore, because the tips of all contacts are maintained in the same plane, there is no need to apply extra pressure to the pads on the integrated circuit chip under test. Moreover, since no lateral displacement occurs during pressing unlike in conventional probes, damage to pads on the chip is reduced.

製品の歩留りおよび信頼性が向上される。Product yield and reliability are improved.

〔実施例〕〔Example〕

以下本発明の実施例を図面を参照して説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の半導体集積回路試験用のプローブの要
部斜視図であって、被検査集積回路チップと同程度の大
きさのシリコンチップ10の一表面には、シリコンチッ
プ10をエツチング加工して形成された複数の接触子1
1が配列されている。各々の接触子11は、その先端に
針状突起を有し、被検査集積回路チップ上に形成されて
いるパッドに一対一で対応するように設けられている。
FIG. 1 is a perspective view of a main part of a probe for testing semiconductor integrated circuits according to the present invention, in which a silicon chip 10 is etched on one surface of a silicon chip 10 of approximately the same size as the integrated circuit chip to be tested. A plurality of contacts 1 formed by
1 are arranged. Each contact 11 has a needle-like protrusion at its tip, and is provided in one-to-one correspondence with the pads formed on the integrated circuit chip to be tested.

各々の接触子11どうしは、後述する手段により電気的
に分離されている。
The respective contacts 11 are electrically isolated from each other by means described later.

シリコンチップ10上には、各々の接触子11を外部回
路に接続するための接続手段として9例えば周知のビー
ムリード構造の電極12が設けられている。また、シリ
コンチップ10の中央部には、目視観察用窓14が設け
られている。目視観察用窓14は。
On the silicon chip 10, electrodes 12 of a well-known beam lead structure are provided as connection means for connecting each contactor 11 to an external circuit. Further, a visual observation window 14 is provided in the center of the silicon chip 10. The visual observation window 14 is.

被検査集積回路チップと本発明のプローブとの位置合わ
せを行う際の窓として用いられる。
It is used as a window when aligning the integrated circuit chip to be tested and the probe of the present invention.

接触子11は、その形成時のエツチング加工において特
別の工夫をしない限り8円錐形を威している。そして、
これらが被検査集積回路チップ上のパッドに押圧される
と、アルミニウム等の金属から成るパッドに食い込む。
The contact 11 has an eight-conical shape unless special measures are taken in the etching process during its formation. and,
When these are pressed against pads on the integrated circuit chip under test, they bite into pads made of metal such as aluminum.

したがって、押圧力が過大である場合、パッドを槽底す
る金属層を突き破って、その下の絶縁層や半導体基板に
形成されている不純物拡散層を損傷する可能性がある。
Therefore, if the pressing force is excessive, the pad may break through the metal layer forming the bottom of the tank, damaging the underlying insulating layer or impurity diffusion layer formed on the semiconductor substrate.

このような危険を回避し、試験における操作を容易にす
るために、第2図(a)に示すような接触子20の構造
が有効である。
In order to avoid such dangers and facilitate operations during testing, the structure of the contactor 20 as shown in FIG. 2(a) is effective.

すなわち、第2図(a)に示す接触子20は、シリコン
チップ10を選択的にエツチングして形成された平坦面
を有する複数の突起21上に、針状突起22が形成され
た構造を有する。第2図(a)の接触子20は第2図(
b)に示すように、被検査集積回路チップ24上に形成
されたパッド25に押圧された場合、突起21の平坦面
がパッド25の上表面により突き当たると、それ以上は
針状突起22がパッド25中に食い込むことが阻止され
る。
That is, the contact 20 shown in FIG. 2(a) has a structure in which needle-like protrusions 22 are formed on a plurality of protrusions 21 having flat surfaces formed by selectively etching the silicon chip 10. . The contactor 20 in FIG. 2(a) is shown in FIG.
As shown in b), when the flat surface of the protrusion 21 is pressed against the pad 25 formed on the integrated circuit chip 24 under test, when the flat surface of the protrusion 21 abuts against the upper surface of the pad 25, the needle-like protrusion 22 will no longer touch the pad. 25 is prevented from digging into the inside.

上記本発明のプローブの作製方法を第3図を参照して説
明する。
The method for manufacturing the probe of the present invention will be explained with reference to FIG.

例えばシリコンウェハの一表面を酸化し、 SiO□膜
を形成したのち2周知のリソグラフ技術を用いてこのS
iO□膜をエツチングし、第3図(a)に示すように、
前記シリコンウェハ30表面に直径約20μmの5i0
2マスク1331を形成する。第3図(b)は同図(a
)のX−X断面を示す。5in2マスク層31の配列ピ
ッチは1図示しない被検査集積回路チップ上のパッドの
配列ピッチと同じであり1例えば40μmである。
For example, one surface of a silicon wafer is oxidized to form a SiO□ film, and then this S
By etching the iO□ film, as shown in FIG. 3(a),
5i0 with a diameter of about 20 μm on the surface of the silicon wafer 30.
2 masks 1331 are formed. Figure 3(b) is
) is shown. The arrangement pitch of the 5in2 mask layer 31 is the same as the arrangement pitch of pads on an integrated circuit chip to be tested (not shown), and is, for example, 40 μm.

次いで1例えばHNO3と)IPの混合溶液から成る。It then consists of a mixed solution of IP (for example with HNO3).

シリコンに対する周知の等方性エツチング液を用いて5
iOzマスク層31から表出しているシリコンウェハ3
0を、その表面から深さ約10μmエツチングする。こ
のエツチングにおいて、シリコンウェハ30は縦方向に
エツチングされるとともに、 Singマスク層31下
におけるサイドエツチング効果により横方向にもエツチ
ングされる。この横方向のエツチング量は、シリコンウ
ェハ30表面に近いほど多いため5表面から10μmの
深さのエツチングが行われると、 SiO□マスク層3
1下には、第3図(C)に示すように1円錐形の突起、
すなわち、針状突起32が残る。針状突起32の高さは
約10μmである。
5 using a well-known isotropic etching solution for silicon.
Silicon wafer 3 exposed from iOz mask layer 31
0 is etched to a depth of about 10 μm from its surface. In this etching, the silicon wafer 30 is etched not only in the vertical direction, but also in the horizontal direction due to the side etching effect under the Sing mask layer 31. The amount of etching in the lateral direction increases as it approaches the surface of the silicon wafer 30, so when etching is performed to a depth of 10 μm from the surface of the silicon wafer 30, the SiO□ mask layer 3
As shown in Fig. 3 (C), below 1 there is a conical protrusion,
That is, the needle-like protrusion 32 remains. The height of the needle-like protrusion 32 is approximately 10 μm.

なお、 (100)面が表出するシリコンウェハ30を
用い、エツチング速度がシリコンウェハの面指数に依存
する9例えばKOHのようなエツチング液を用いても同
様な針状突起32を形成可能である。この場合には、針
状突起32は必ずしも円錐形とはならず1例えば角錐形
となる。また、基部とは異なる不純物種を含有する厚さ
10μmの表面層をシリコンウェハ30表面にあらかじ
め形成しておけば。
Note that similar needle-like protrusions 32 can also be formed by using a silicon wafer 30 with an exposed (100) plane and using an etching solution such as KOH whose etching rate depends on the plane index of the silicon wafer. . In this case, the needle-like protrusion 32 does not necessarily have a conical shape, but has a pyramidal shape, for example. Moreover, if a surface layer with a thickness of 10 μm containing an impurity species different from that of the base layer is previously formed on the surface of the silicon wafer 30.

針状突起32を形成するためのエツチング量の制御が容
易に行える。このような表面層は、シリコンウェハ30
表面にエピタキシャル成長させて形成する。
The amount of etching for forming the needle-like protrusions 32 can be easily controlled. Such a surface layer is formed on the silicon wafer 30.
It is formed by epitaxial growth on the surface.

なお、第2図に示す構造の接触子20の形成は。Note that the contact 20 having the structure shown in FIG. 2 is formed as follows.

針状突起22を形成したのち、針状突起22を含む突起
21の領域をマスクするレジスト層を設け1表出するシ
リコンウェハ表面を異方性エツチングすることにより可
能である。
This can be achieved by forming the needle-like projections 22, then providing a resist layer to mask the area of the projections 21 including the needle-like projections 22, and anisotropically etching the exposed silicon wafer surface.

SiO□マスク層31を除去したのち、シリコンウェハ
30表面を熱酸化して5i02膜を形成し、この上にレ
ジストを塗布する。そして、このレジスト層を露光・現
像して、第3図(d)に示すように、針状突起32およ
びこれに隣接するコンタクト領域34に対応する開口を
有するレジストマスク35を形成する。
After removing the SiO□ mask layer 31, the surface of the silicon wafer 30 is thermally oxidized to form a 5i02 film, and a resist is applied thereon. Then, this resist layer is exposed and developed to form a resist mask 35 having openings corresponding to the needle-shaped projections 32 and the contact regions 34 adjacent thereto, as shown in FIG. 3(d).

この開口内に表出する前記Si0g膜をエツチング除去
する。第3図(e)は、同図(d)のY−Y断面を示し
The SiOg film exposed within this opening is removed by etching. FIG. 3(e) shows the YY cross section of FIG. 3(d).

符号36は前記5in2膜である。レジストマスク35
のパターンニングは、針状突起32を含む10μm程度
の段差を有する領域で行われるが、ポジレジストとEB
露光法ないし縮小投影露光法を用いれば容易に可能であ
る。
Reference numeral 36 is the 5in2 film. resist mask 35
The patterning is performed in a region having a step of about 10 μm including the needle-like protrusions 32.
This is easily possible using an exposure method or a reduction projection exposure method.

次いで、レジストマスク35を除去し、 SiO□膜3
6をマスクとして3表出するシリコンウェハ30表面。
Next, the resist mask 35 is removed and the SiO□ film 3 is removed.
The surface of a silicon wafer 30 where 3 is exposed using 6 as a mask.

すなわち、針状突起32およびコンタクト領域34表面
に不純物を拡散する。この不純物は、シリコンウェハ3
0がp型である場合には、n型である。その結果、第3
図(f)に示すように、針状突起32の表面およびコン
タク) 6N域34にn型領域38が形成される。
That is, impurities are diffused into the surfaces of the needle-like protrusions 32 and the contact regions 34. This impurity is removed from the silicon wafer 3.
If 0 is p-type, it is n-type. As a result, the third
As shown in Figure (f), an n-type region 38 is formed on the surface of the needle-like protrusion 32 and the contact region 34.

上記ののち、第3図(8)の平面図および(ロ)の断面
図に示すように、コンタクト領域34に接続された電極
39を形成する。電極39は1例えばAu薄膜から成り
、後述するように1周知のビームリード技術にもとづき
外部回路との接続に用いられる。なお。
After the above, as shown in the plan view of FIG. 3(8) and the cross-sectional view of FIG. 3(b), an electrode 39 connected to the contact region 34 is formed. The electrode 39 is made of, for example, an Au thin film, and is used for connection to an external circuit based on a well-known beam lead technique, as will be described later. In addition.

Auから成る電極39とシリコンウェハ30との共晶合
金化を防止するために、電極39とシリコンウェハ30
間に周知のバリヤ層(図示省略)を設けることは通常の
集積回路と同様である。電極39は、検査時に被検査集
積回路チップに接触しないように。
In order to prevent the electrode 39 made of Au and the silicon wafer 30 from forming a eutectic alloy, the electrode 39 and the silicon wafer 30 are
Providing a well-known barrier layer (not shown) in between is similar to a typical integrated circuit. The electrode 39 should not come into contact with the integrated circuit chip to be tested during testing.

針状突起32の高さより充分に低く形成されていること
が必要である。
It is necessary that the height is sufficiently lower than the height of the needle-like projection 32.

次いで、シリコンウェハ30を1個々のプローブごとに
分離する。この分離は1例えばシリコンウェハ30にお
ける針状突起32等が形成されている表面全体をレジス
ト層によりマスクし、一方1M面側におけるプローブに
対応する領域にレジストマスフを形成し1表出するシリ
コンウェハ30をエツチング除去する方法を用いるのが
適当である。このとき、シリコンウェハ30の裏面側に
おけるレジストマスクに、前記目視観察用窓14(第1
図参照)に対応する開口を設けておくことにより、目視
観察用窓14が同時に形成される。
Next, the silicon wafer 30 is separated into individual probes. This separation is carried out by masking the entire surface of the silicon wafer 30 on which the needle-like protrusions 32 and the like are formed with a resist layer, and forming a resist mask in the area corresponding to the probe on the 1M surface side to expose the silicon wafer 30. It is appropriate to use a method of etching away. At this time, the visual observation window 14 (first
By providing an opening corresponding to the window (see figure), the visual observation window 14 is formed at the same time.

上記のようにして、第3図(i)に示すように1本発明
のプローブが形成される。電極39は、プローブの基体
であるシリコンチップ10から横方向に突出したビーム
リード構造を威している。
In the manner described above, one probe of the present invention is formed as shown in FIG. 3(i). The electrode 39 has a beam lead structure that protrudes laterally from the silicon chip 10 that is the base of the probe.

上記本発明のプローブを、第7図に示した従来の試験用
プローブにおけるプリント配線基Fi1に接着固定し、
電極39を配線4にボンディングすればよい、あるいは
1第4図に示すように、シリコンチップ10を嵌挿可能
な凹部を有するセラミック基Fi40を用意し、これに
シリコンチップ10を接着固定し、セラミック基板40
上に形成されている配線41と電極39とをボンディン
グする。セラミック基板40は、−船釣なプリント配線
基板に比べて剛性がすぐれており、プローブを設定する
ときの位置精度、ウェハとの平行度を確保するのを容易
にする。
The probe of the present invention is adhesively fixed to the printed wiring board Fi1 in the conventional test probe shown in FIG.
The electrode 39 may be bonded to the wiring 4, or as shown in FIG. Substrate 40
The wiring 41 and the electrode 39 formed above are bonded. The ceramic substrate 40 has superior rigidity compared to a standard printed wiring board, and makes it easy to ensure positional accuracy and parallelism with the wafer when setting the probe.

上記実施例のプローブにおいては、針状突起32とコン
タクト領域34は、これらの表面に形成されたn型領域
38によって接続されている。そこで。
In the probe of the above embodiment, the needle-like protrusion 32 and the contact region 34 are connected by an n-type region 38 formed on their surfaces. Therefore.

シリコンチップ10に対して、測定電圧範囲より低い電
圧(負電位および接地電位を含む)を印加しておけば、
シリコンチップ10とn型領域38との間は逆バイアス
電圧が印加されたことになるため。
If a voltage lower than the measurement voltage range (including negative potential and ground potential) is applied to the silicon chip 10,
This is because a reverse bias voltage is applied between the silicon chip 10 and the n-type region 38.

各々の針状突起32どうしを互いに電気的に分離するこ
とができる。なお、針状突起32の表面を覆う。
Each needle-like projection 32 can be electrically isolated from each other. Note that the surface of the needle-like protrusion 32 is covered.

例えばタングステンのような金属薄膜またはタングステ
ンシリサイドのような金属シリサイド薄膜を形成するこ
とにより、針状突起32の接触抵抗を低くすることがで
きる。
For example, by forming a metal thin film such as tungsten or a metal silicide thin film such as tungsten silicide, the contact resistance of the needle-like projections 32 can be lowered.

針状突起32相互間の電気的分離方法として、絶縁分離
構造を用いてもよい。このような絶縁分離構造の形成に
5例えば周知の5ol(Silicon on In−
5ulator)技術を用いると都合がよい。すなわち
周知のシリコンウェハの貼り合わせ技術により形成され
た第5図(a)に示すようなSOI基板50を用意する
。SO■基Fi50は1通常の厚さのシリコンウェハ5
1と、その表面を熱酸化して形成されたSiO□膜52
と、 5iOz膜52を介してシリコンウェハ51との
間に高電圧を印加した状態で熱圧着されたシリコン層5
3とから構成されている。シリコン層53は1例えば機
械研磨により12μm程度の厚さに仕上げられており、
あらかじめn型にされているか、上記研磨後に不純物を
拡散して少なくとも表面がn型にされている。
An insulating isolation structure may be used as a method for electrically isolating the needle-like protrusions 32 from each other. For example, the well-known 5ol (Silicon on In-
It is convenient to use the 5ulator technique. That is, an SOI substrate 50 as shown in FIG. 5(a), which is formed by a well-known silicon wafer bonding technique, is prepared. SO■ based Fi50 is 1 normal thickness silicon wafer 5
1 and a SiO□ film 52 formed by thermally oxidizing its surface.
The silicon layer 5 is bonded by thermocompression with a high voltage applied to the silicon wafer 51 via the 5iOz film 52.
It is composed of 3. The silicon layer 53 is finished to a thickness of about 12 μm, for example, by mechanical polishing.
Either the surface is made n-type in advance, or at least the surface is made n-type by diffusing impurities after the polishing.

シリコンJW53表面に、第3図で説明したと同様の手
法を用い、第5図(b)に示すようにStO□マスク層
54層形4したのち、シリコン層53をエツチングして
針状突起55を形成する。次いで、残りのシリコン層5
3を選択的にエツチングし、第5図(C)に示すように
1個々の針状突起55を分離する。針状突起55に対応
して、シリコン層53から成るコンタクト領域56が設
けられる。コンタクト領域56に、前記実施例と同様に
して、ビームリード構造の電極(図示省略)を形成した
のち、シリコンウェハ51を個々のプローブに分離する
。第5図に示す構造によれば、突起55は、 Sin、
膜52により互いに絶縁分離されており、シリコンウェ
ハ51から成るプローブ基板に印加する電圧に対して特
別の制約がなくなる。
Using the same method as explained in FIG. 3, a StO□ mask layer 54 is formed on the surface of the silicon JW 53 as shown in FIG. form. Next, the remaining silicon layer 5
3 is selectively etched to separate one individual needle-like protrusion 55 as shown in FIG. 5(C). A contact region 56 made of silicon layer 53 is provided corresponding to needle-like protrusion 55 . After forming electrodes (not shown) having a beam lead structure in the contact region 56 in the same manner as in the previous embodiment, the silicon wafer 51 is separated into individual probes. According to the structure shown in FIG. 5, the protrusion 55 has Sin,
They are insulated from each other by the film 52, and there are no special restrictions on the voltage applied to the probe substrate made of the silicon wafer 51.

[発明の効果〕 本発明によれば、高密度集積回路チップにおけるパッド
に対応する配列ピッチの接触子を有する試験用プローブ
が容易に作製可能であり、従来のプローブに比べて、接
触子間の位置精度および平面度が優れているばかりでな
く、m1tt的衝撃にも強いプローブを提供でき、また
、被試験集積回路チップに上のパッドに与える損傷も低
減され、高密度集積回路製品の歩留りおよび信頼性を向
上可能とする効果がある。
[Effects of the Invention] According to the present invention, a test probe having contacts with an array pitch corresponding to pads on a high-density integrated circuit chip can be easily manufactured, and compared to conventional probes, the test probe has It not only has excellent positional accuracy and flatness, it also provides a probe that is resistant to m1tt impact. It also reduces damage to the pads on the integrated circuit chip under test, improving the yield of high-density integrated circuit products. This has the effect of improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の半導体集積回路試験用プローブの要部
斜視図。 第2図は本発明のプローブのにおける接触子の構造の変
形例。 第3図は本発明のプローブの作製方法の実施例第5図は
本発明のプローブにおける接触子の別の分離方法説明図
。 第6図は従来の半導体集積回路試験用プローブの構造説
明図。 第7図は従来のプローブの問題点説明図。 である。 図において。 1はプリント配線基板、  2は貫通孔。 3は接触子、  4と41は配線。 5はコネクタ接続端子、IOはシリコンチップ。 11と20は接触子、12と39は電極。 14は目視観察用窓、21は突起 22と32と55は針状突起。 24は被検査集積回路チップ、25はパッド。 30と51はシリコンウェハ。 31と54はSiO□マスク層。 34と56はコンタクト領域。 35はレジストマスク、36と52は5in2膜。 38はn型領域、40はセラごツタ基板。 50はsor基板、53はシリコン層。 である。 (0−) (b) 木金明の4−譚体薬横回昂信ゎ成用ブH−フ゛ひ要部斜
視国策1圀 未発↓月のフ゛H−フ゛1:あ゛げろ捜す映子の構造の
・斐ブ形伊1第2図 本斧明のアロー7′の作製方法の犬橙例第3図(千の1
) 14 木幣明のア0−7I)倍製布法0貢袴例亭3図(モの2
) 0 本斧明のアローブ°の完へ°因 /を争研のアローアj:お1プろ芙触干の5りのオ離々
法第5図
FIG. 1 is a perspective view of a main part of a probe for testing a semiconductor integrated circuit according to the present invention. FIG. 2 shows a modification of the structure of the contact in the probe of the present invention. FIG. 3 is an embodiment of the probe manufacturing method of the present invention. FIG. 5 is an explanatory diagram of another method for separating the contact in the probe of the present invention. FIG. 6 is a structural explanatory diagram of a conventional semiconductor integrated circuit testing probe. FIG. 7 is a diagram illustrating problems with a conventional probe. It is. In fig. 1 is a printed wiring board, 2 is a through hole. 3 is a contact, 4 and 41 are wiring. 5 is a connector connection terminal, and IO is a silicon chip. 11 and 20 are contacts, and 12 and 39 are electrodes. 14 is a window for visual observation; 21 is a projection 22, 32 and 55 is a needle-like projection. 24 is an integrated circuit chip to be tested, and 25 is a pad. 30 and 51 are silicon wafers. 31 and 54 are SiO□ mask layers. 34 and 56 are contact areas. 35 is a resist mask, and 36 and 52 are 5in2 films. 38 is an n-type region, and 40 is a ceramic substrate. 50 is a SOR substrate, and 53 is a silicon layer. It is. (0-) (b) Mogaki Jinmei's 4-Tan body medicine horizontal circulation message formation book H-Phi main part squinting national policy 1 has not been released Fig. 2 Example of how to make the arrow 7' of the structure Fig. 3 (1,000 1
) 14 A0-7I of Kimei Ming
) 0 Main Ax Akira's Arrow to completion

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板と、 該半導体基板の有する一表面を選択的にエッチングして
該半導体基板上に形成された複数の針状突起と、 各々の該針状突起を互いに電気的に分離する分離手段と
、 該針状突起を外部回路に接続するビームリード構造の接
続手段 とを備えたことを特徴とする半導体集積回路試験用プロ
ーブ。
(1) A semiconductor substrate, a plurality of needle-like protrusions formed on the semiconductor substrate by selectively etching one surface of the semiconductor substrate, and separation for electrically separating each of the needle-like protrusions from each other. 1. A probe for testing a semiconductor integrated circuit, comprising: a connecting means having a beam lead structure for connecting the needle-like protrusion to an external circuit.
(2)該針状突起は、該半導体基板表面を選択的にエッ
チングして形成された平坦面を有する複数の突起におけ
る該平坦面に形成されていることを特徴とする請求項1
の半導体集積回路試験用プローブ。
(2) Claim 1 characterized in that the needle-like protrusion is formed on the flat surface of a plurality of protrusions each having a flat surface formed by selectively etching the surface of the semiconductor substrate.
probe for testing semiconductor integrated circuits.
(3)ウェハまたはチップ状態の半導体集積回路に形成
されているパッドに請求項1または2に記載のプローブ
における該針状突起を接触させて試験を行う工程を含む
ことを特徴とする半導体装置の製造方法。
(3) A semiconductor device characterized by comprising the step of performing a test by bringing the needle-like protrusion of the probe according to claim 1 or 2 into contact with a pad formed on a semiconductor integrated circuit in the form of a wafer or chip. Production method.
JP1205301A 1989-08-08 1989-08-08 Probe for semiconductor integrated circuit test use; manufacture of semiconductor device including test process using same probe Pending JPH0369131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1205301A JPH0369131A (en) 1989-08-08 1989-08-08 Probe for semiconductor integrated circuit test use; manufacture of semiconductor device including test process using same probe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1205301A JPH0369131A (en) 1989-08-08 1989-08-08 Probe for semiconductor integrated circuit test use; manufacture of semiconductor device including test process using same probe

Publications (1)

Publication Number Publication Date
JPH0369131A true JPH0369131A (en) 1991-03-25

Family

ID=16504694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1205301A Pending JPH0369131A (en) 1989-08-08 1989-08-08 Probe for semiconductor integrated circuit test use; manufacture of semiconductor device including test process using same probe

Country Status (1)

Country Link
JP (1) JPH0369131A (en)

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US5483741A (en) * 1993-09-03 1996-01-16 Micron Technology, Inc. Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice
US5487999A (en) * 1991-06-04 1996-01-30 Micron Technology, Inc. Method for fabricating a penetration limited contact having a rough textured surface
US5497104A (en) * 1992-06-03 1996-03-05 Itt Corporation Flexible interface IC test clip
US5585282A (en) * 1991-06-04 1996-12-17 Micron Technology, Inc. Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor
US5592736A (en) * 1993-09-03 1997-01-14 Micron Technology, Inc. Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads
US5634267A (en) * 1991-06-04 1997-06-03 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US5781022A (en) * 1991-06-04 1998-07-14 Micron Technology, Inc. Substrate having self limiting contacts for establishing an electrical connection with a semiconductor die
US6040702A (en) * 1997-07-03 2000-03-21 Micron Technology, Inc. Carrier and system for testing bumped semiconductor components
US6060891A (en) * 1997-02-11 2000-05-09 Micron Technology, Inc. Probe card for semiconductor wafers and method and system for testing wafers
US6091251A (en) * 1991-06-04 2000-07-18 Wood; Alan G. Discrete die burn-in for nonpackaged die
US6094058A (en) * 1991-06-04 2000-07-25 Micron Technology, Inc. Temporary semiconductor package having dense array external contacts
US6127195A (en) * 1993-09-03 2000-10-03 Micron Technology, Inc. Methods of forming an apparatus for engaging electrically conductive pads and method of forming a removable electrical interconnect apparatus
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US6219908B1 (en) 1991-06-04 2001-04-24 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US6265245B1 (en) 1991-06-04 2001-07-24 Micron Technology, Inc. Compliant interconnect for testing a semiconductor die
US6340894B1 (en) 1991-06-04 2002-01-22 Micron Technology, Inc. Semiconductor testing apparatus including substrate with contact members and conductive polymer interconnect
US6414506B2 (en) 1993-09-03 2002-07-02 Micron Technology, Inc. Interconnect for testing semiconductor dice having raised bond pads
US6650133B1 (en) * 2000-10-25 2003-11-18 Intel Corporation Method and apparatus for buckling beam testing
US6763578B2 (en) 1988-09-30 2004-07-20 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US6798224B1 (en) 1997-02-11 2004-09-28 Micron Technology, Inc. Method for testing semiconductor wafers
US6828812B2 (en) 1991-06-04 2004-12-07 Micron Technology, Inc. Test apparatus for testing semiconductor dice including substrate with penetration limiting contacts for making electrical connections
US6900646B2 (en) 1998-04-03 2005-05-31 Hitachi, Ltd. Probing device and manufacturing method thereof, as well as testing apparatus and manufacturing method of semiconductor with use thereof
US6914275B2 (en) 2002-05-06 2005-07-05 Micron Technology, Inc. Semiconductor component with electrical characteristic adjustment circuitry
US6998860B1 (en) 1991-06-04 2006-02-14 Micron Technology, Inc. Method for burn-in testing semiconductor dice

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US6219908B1 (en) 1991-06-04 2001-04-24 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US6828812B2 (en) 1991-06-04 2004-12-07 Micron Technology, Inc. Test apparatus for testing semiconductor dice including substrate with penetration limiting contacts for making electrical connections
US5487999A (en) * 1991-06-04 1996-01-30 Micron Technology, Inc. Method for fabricating a penetration limited contact having a rough textured surface
US5634267A (en) * 1991-06-04 1997-06-03 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US5585282A (en) * 1991-06-04 1996-12-17 Micron Technology, Inc. Process for forming a raised portion on a projecting contact for electrical testing of a semiconductor
US6998860B1 (en) 1991-06-04 2006-02-14 Micron Technology, Inc. Method for burn-in testing semiconductor dice
US6265245B1 (en) 1991-06-04 2001-07-24 Micron Technology, Inc. Compliant interconnect for testing a semiconductor die
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