JPH0364913A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent deterioration of the efficiency of the title semiconductor device due to charge up when a high dosage is ion-implanted by a method wherein the amount of the electricity discharged into a substrate is reduced by the electric charges generated on the surface of ion irradiation when ions are implanted through the intermediary of the region which inflicts effect on the element efficiency in an element forming region. CONSTITUTION:A dummy region, where a field insulating film 2 is removed, is provided on a semiconductor substrate 1 in the vicinity of an element forming region 3 where impurities will be introduced, the above-mentioned dummy region 9 and the element forming region 3 are exposed together to one aperture 7 which will be used for the ion implantation of a resist mask 6, and the electric charges generated on the ion irradiation surface is preferentially discharged into the substrate from the dummy region 9 which has no field insulating film 2 and will be brought into a conductive state when ions are implanted. As a result, deterioration of efficiency of the title device, caused by the charge-up generated when high dosage ions are implanted, can be prevented.

Description

[Detailed Description of the Invention] [Summary] This invention relates to an improvement in a method for manufacturing a semiconductor device, particularly a method for implanting impurity ions using a resist as a mask, by reducing the amount of discharge passing through a region that affects device performance. In order to prevent deterioration of device performance due to charge-up during ion implantation, when selectively implanting impurity ions into a semiconductor substrate using a resist film as a mask, a field insulator is placed on the semiconductor substrate. forming an opening in the film to form a region into which an impurity is to be introduced and a dummy region, and forming a resist film having an integrated opening exposing both the region into which the impurity is to be introduced and the dummy region on the substrate; , a step of performing ion implantation using the resist film as a mask and causing charges generated on the ion irradiated surface during the ion implantation to flow into the semiconductor substrate through the dummy region;
A first aperture that exposes a scribe line formed by opening the field insulating film on the semiconductor substrate, and a second aperture that exposes a region into which impurities are to be introduced and extends to the first aperture. A resist film having openings is formed, and impurity ions are implanted into the semiconductor substrate using the resist film as a mask. Charges generated on the ion irradiation surface during the ion implantation are transferred through the scribe line. A step of draining into the semiconductor substrate, or forming a resist pattern that selectively covers areas on the semiconductor substrate where impurity introduction is avoided,
Ion implantation is performed using the resist pattern as a mask,
The method includes at least one step of causing charges generated on the ion irradiation surface during the ion implantation to flow into the semiconductor substrate through an exposed opening in a field insulating film on the semiconductor substrate.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to an improvement in a method of implanting impurity ions using a resist as a mask.

For example, in the manufacturing process of MO3IG, the problem of gate insulating film breakdown due to charge-up on the ion irradiation surface during high-dose ion implantation of impurities has arisen due to the miniaturization of elements accompanying higher integration.

To prevent this, ion implanters take measures such as irradiating the surface of the substrate to be processed with electrons to make it negatively charged, thereby neutralizing the charge of the implanted ions. However, it is still insufficient, and it is necessary to improve the charge-up resistance on the device side by improving the structure and process.

[Conventional technology]

In conventional ion implantation technology, as shown in a schematic plan view of a resist mask in FIG. A resist film 52 is formed, and an opening 53 is formed in this resist film 52 to selectively expose only the region where ions are to be implanted. In this process, selective impurity ion implantation was performed.

That is, when performing impurity ion implantation to form the source/drain region of a MOSFET, for example, FIGS.
As schematically shown in the cross-sectional view (C) taken along the -B arrow, a gate oxide film 4 is formed on an element formation region 3 defined by a field oxide film 2 on one surface of a p-type silicon (St) substrate. For example, a gate electrode 5 crossing the element shape tc9M region 3 is formed on the top.
After forming, a resist film 6 serving as a mask is formed on this substrate.
A hole 7 for ion implantation is formed in the resist film 6 to expose the element formation region 3 slightly wider, taking into account the alignment error, and the gate electrode 5 is inserted through the hole 7 as a mask. , a method was used in which n-type impurities such as arsenic (As") were ion-implanted at a high concentration through the gate oxide film 4. (108 is an As" implantation region) [Problem to be solved by the invention] However, the above-mentioned conventional method In this method, as shown in FIG. 7, which schematically shows the flow of charges, the escape route for positive charges (+) caused by ions directly implanted into the gate electrode 5 made of, for example, poly-Si, is indicated by the arrow PI. As shown in FIG. 2, the discharge occurs only through the gate oxide film 4 having a low dielectric breakdown voltage, so when the amount of charge-up increases due to high-dose ion implantation (1, 1), the gate oxide film 4 is discharged during this discharge. may be destroyed.

In addition, in the conventional method, as mentioned above, all areas other than the area where ions are implanted are covered with the resist film 6 (see Fig. 5, 52), so that ions are irradiated and charged up as shown in Fig. 7. Discharge of positive charges (+) from the surface of the resist film 6 (see FIG. 52) to the gate electrode 5 (
Considering the arrow pg), when the number of openings 7 per chip is small, the charge (+) on the surface of the resist film 6 is
The amount of charge supplied to the discharge directed toward the substrate l via the gate electrode 5 exposed in the opening 7 for ion implantation formed in the resist film 6 increases, and in this respect as well, the gate oxide film 4
There was a problem that dielectric breakdown easily occurred. (l is the semiconductor substrate, 2 is the field oxide film) Furthermore, although not shown, a potential is induced in the gate electrode under the resist film by the charge on the surface of the resist film, and electrons flowing from the substrate through the gate oxide film cause the gate electrode to There was also the problem that the oxide film deteriorated.

Therefore, an object of the present invention is to reduce the amount of discharge passing through a region that affects device performance, thereby preventing deterioration of device performance due to charge-up during ion implantation.

[Means to solve the problem]

The above problem occurs when selectively implanting impurity ions into a semiconductor substrate using a resist film as a mask. A resist film is formed on the substrate and has an integral opening that exposes both the region into which the impurity is to be introduced and the dummy region, and ions are implanted using the resist film as a mask. A step of causing charges generated on the ion irradiation surface during implantation to flow into the semiconductor substrate through the ladder region, and a scribe line formed by opening a field insulating film on the semiconductor substrate on the semiconductor substrate. forming a resist film having a first opening that exposes the impurity, and a second opening that exposes the region into which impurities are to be introduced and extends to the first opening; A step of implanting impurity ions into the semiconductor substrate using a mask and causing charges generated on the ion irradiated surface during the ion implantation to flow into the semiconductor substrate through the scribe line, and masking the resist film. When selectively implanting impurity ions into a semiconductor substrate, a resist pattern is formed on the semiconductor substrate to selectively cover areas where impurity introduction is avoided, and ions are implanted using the resist pattern as a mask. The step of causing the charges generated on the ion irradiated surface during the ion implantation to flow into the semiconductor substrate through the opening of the exposed field insulating film on the semiconductor substrate is performed. The problem is solved by a method of manufacturing a semiconductor device according to the present invention.

[For production]

That is, in the first invention, a dummy region (dummy field) from which a field insulating film is removed is provided in the vicinity of an element formation region into which impurities are introduced on a semiconductor substrate, and a part of the resist mask for ion implantation is provided. The dummy region and the element formation region are exposed together in one opening, and the charges generated on the ion irradiation surface are preferentially transferred from the dummy region, which does not have the field insulating film and becomes conductive during ion implantation. Discharge into the board. Further, in the second invention, the resist mask for ion implantation has a first opening exposing the scribe line, and a second opening for ion implantation over a region where impurities are to be introduced. Using a mask extended and connected to the first aperture, the surface of the field insulating film exposed at the extension of the second aperture and made conductive by ion irradiation is used as a discharge path, and ions are implanted during ion implantation. Charges generated in the region and its neighboring region including on the resist are discharged into the substrate via the discharge path. Further, in the third invention, by making the area covered by the resist mask the smallest area in which ion implantation is desired to be avoided, the total amount of charges generated on the resist surface is reduced, and the discharge current flowing from the resist surface into the substrate: Decrease the amount of ffL.

As a result, the amount of charge generated on the ion irradiation surface during ion implantation is discharged to the substrate through the region in the device formation region that affects device performance, and this reduces the amount of charge generated during high-dose ion implantation. Prevent deterioration of device performance due to upgrades.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

FIG. 1 is a schematic diagram of a first embodiment of the method of the present invention, (a
) is a plan view, (b) is a sectional view taken along A-A, (C) is B-
FIG. 2 is a schematic side sectional view of the semiconductor device according to the first embodiment, and FIG. 3 is a schematic diagram of the second embodiment. , (a) is a plan view, (c) is A
4 is a schematic diagram of the third embodiment;
a) is a plan view, (c) is a sectional view taken along the line A-A, and (C) is B
-B is a sectional view taken along the arrow, and (d) is a sectional view taken along the line C-C. Identical objects are indicated by the same reference numerals throughout the figures.

When forming, for example, an n-channel MO3FET by the method of the present invention, the element formation region 3 and the region surrounding it are surrounded by, for example, ordinary selective oxidation means on the p-type St substrate 1, leaving a region where the gate electrode 5 is disposed. Field oxide film 2 defining and exposing a dummy region (dummy field) 9
A gate electrode (made of poly-Si or the like) 5 having a gate oxide film 4 underneath and extending from above the element formation region 3 to the field oxide film 2 is formed on the element formation region 3, and the element formation Si exposed surfaces of region 3 and dummy region 9;
After forming a through oxide film 10 through which ion-implanted impurities can pass through on the surface of the gate electrode 5, an ion-implantation advisory hole is formed on the substrate 1 to expose the element type region 3 and the dummy region 9 together. 7 is formed, and using this resist film 6 as a mask, the entire surface is irradiated with As'' ions to selectively form source/drain (S) ions in the element formation region 3 that is not covered with the gate electrode 5. /D) As'' forming the TJ region is, for example, 1016 to 10'? Ion implantation is performed at a relatively high dose. At this time, As'' is similarly implanted into the dummy region 9. Note that 108A, 108B, 1
08c indicates the As'' implanted region.

At the time when ion implantation is being performed, the surface layer of the insulating film, that is, the surface layer of the field oxide film 2 into which ions are implanted, is in a conductive state due to the generation of positive and negative charge bears, and is a thin insulating film through which ions can pass. That is, the through oxide film 10 is completely made conductive up to the bottom surface. Therefore, the ions are discharged into the surface of the gate electrode 5 by ion implantation, and at the same time, the ions are discharged through the surface of the field oxide film 2 and the through oxide film 10.
+ I? , are discharged from the M region 9 into the substrate 1. Therefore, since almost no discharge occurs through the gate oxide film 4 having insulation resistance, dielectric breakdown of the gate oxide film 4 is prevented.

Also, a large amount of positive charge (+) generated on the surface of the resist film 6 that is irradiated with ions during ion implantation is discharged into the substrate 1 from the dummy region 9 surrounding the gate portion via the chemical film 10. Therefore, this charge hardly passes through the gate oxide film 4, and dielectric breakdown of the gate oxide film 4 is prevented.

FIG. 2 schematically shows a side sectional view of a semiconductor device formed according to a conventional method after the above ion implantation.
In the figure, 8A is an n" type source region, 8B is an n9 type drain region, 11 is an oxide film for impurity blocking, 12 is an insulating film between the eyebrows, 13 is a contact window, 14 is a source wiring, 15 is a drain wiring, and other symbols indicates the same object as in FIG.

FIG. 3 is a plan view (a) and a sectional view taken along the line A-A (b) schematically showing a second embodiment of the method of the present invention.

In this method, a resist film 6 formed as an ion implantation mask on the St substrate 1 has a first opening 107 that exposes the entire scribe line 17 that defines the chip region 16, and a first opening 107 that exposes the entire scribe line 17 that defines the chip region 16. A second opening 207 for ion implantation that exposes the element formation region 3 and extends above the scribe line 17 to connect to the first opening 107.
By irradiating the entire surface with impurity ions, impurity ions are implanted into the element formation region 3 through the through oxide film 10 through the first opening 207 of the resist film 6.

In this way, during ion irradiation, the charge (+) generated on the surface of the resist film 6 surrounding the element formation region 3 is exposed in the second opening 207 and becomes a conductor by the ion irradiation, as shown in the figure. The discharge reaches the first opening 107 on the scribe line 17 along the surface of the field oxide film 2, and is discharged into the St substrate 1 through the through oxide film 10, which has been made conductive to the bottom by ion irradiation, so that the device is formed. Area 3
This prevents dielectric breakdown from occurring in the gate oxide film 4 and the like formed therein.

FIG. 4 is a plan view (a) schematically showing a third embodiment of the method of the present invention when forming a CMO3IC, A-A
They are a cross-sectional view taken along arrows (b), a cross-sectional view taken along line B-B (c), and a cross-sectional view taken along line CC (d).

In this example, dummy regions 9A and 9B in which the field oxide film 2 is opened are formed on both sides of the gate electrode 5 between the n-channel MO3FET type tc%M region 3 Nch and the p-channel MO3FETO formation region 3 PchO. .

For example, an n-channel MO3FET formation region 3M
e) When ion-implanting n-type impurities for source/drain formation into i, a resist pattern 6P serving as a mask is formed only on the upper part of the p-channel MO3FET formation region 3Pch, where introduction of impurities must be avoided. Ion implantation is performed. By doing this, the gate electrode 5
Charges (+) generated by ion irradiation are discharged into the substrate l from the dummy regions 9A and 9B through the surface of the field oxide film 2 which becomes conductive as shown in the figure.

In addition, the surface area of the resist mask (resist pattern 6P) becomes significantly smaller and the total amount of charge generated by ion irradiation on the surface is significantly reduced, so the dummy area 9A
, 9B is rapidly generated, and dielectric breakdown of the gate oxide film (not shown) formed in the n-channel MO3FET formation region S Nch is more completely prevented.

Note that when ion-implanting p-type impurities for source/drain formation into p-channel MO3FET formation region 3Pch, n-channel MO3FET formation S'JA region 3N-
A resist pattern covering only the area h is formed.

〔Effect of the invention〕

As explained above, according to the present invention, the amount of charge generated on the ion irradiated surface during ion implantation is discharged into the substrate through the region in the device formation region that affects device performance, and thereby Deterioration of device performance due to charge-up during high-dose ion implantation is prevented.

Therefore, the present invention is effective in improving the manufacturing yield and reliability of highly integrated MO3ICs and the like.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a first embodiment of the method of the present invention, (a
) is a plan view, (b) is a sectional view taken along A-A, (C) is B-
2 is a schematic side sectional view of a semiconductor device according to the first embodiment of the method of the present invention, and FIG. 3 is a sectional view of the semiconductor device according to the first embodiment of the method of the present invention. A schematic diagram of the second embodiment of (a
) is a plan view, (c) is a sectional view taken along the line A-A, FIG. 4 is a schematic diagram of the third embodiment of the method of the present invention, and (a) is a plan view;
(Middle) is a cross-sectional view taken along A-A, (C) is a cross-sectional view taken along B-B,
(A) is a sectional view taken along the line C-C, FIG. 5 is a schematic plan view of a conventional resist mask, and FIG. 6 is a schematic diagram of a conventional method.
) is a plan view, (b) is a sectional view taken along A-A, (C) is B-
FIG. 7, a sectional view taken along arrow B, is a schematic diagram of the flow of charge in the conventional method. In the figure, 1 is a Si substrate, 2 is a field oxide film, 3 is an element formation region, 4 is a gate oxide film, 5 is a gate electrode, 6 is a resist film, 7 is an ion implantation hole, 8
A is an n-type source region, 8B is an n+-type drain region
8C is an n'' type region, 9 is a dummy region (dummy field), and 10 is a through oxide film. 'Face diagram' $ 2 Mouth (α) Plan of the uninvented desk/l Broom 2/) Shitang Yi 1's Rokukoufu 3 Figure (17nA-A'Aa##[2 (C)F3 - B matter hikimasu drawing (d) C-C husband's view @mezu 1000 □ Lee and Kazutsu no K111/) Sane-suke 1n Enoki old (α) Plan view CF)) A-A Emm Face view CC) B-B Yu (view d da Y detour (d) C-C ru (, 歿d斥dwatakeko 7!: During the implementation of the rod 3 of the method of Hatsuro In Gunroku old) 4th Regis) - Y Suku/l Enoki Roku Plan View Figure 5 (#) A-A arrow view 6 starting calculations 6 figures 1! 1lli” Usuki Mokuchi

Claims (3)

[Claims] (1) When selectively implanting impurity ions into a semiconductor substrate using a resist film as a mask, a region where the field insulating film is opened and where the impurity is to be introduced and a dummy region are formed on the semiconductor substrate. , forming a resist film having an integral opening exposing both the region into which the impurity is to be introduced and the dummy region on the substrate, performing ion implantation using the resist film as a mask, and performing ion implantation during the ion implantation. 1. A method of manufacturing a semiconductor device, comprising the step of causing charges generated on an ion-irradiated surface to flow into the semiconductor substrate through the dummy region. (2) When selectively implanting impurity ions into a semiconductor substrate using a resist film as a mask, a scribe line formed by opening a field insulating film on the semiconductor substrate is exposed on the semiconductor substrate. forming a resist film having a first opening and a second opening exposing a region into which an impurity is to be introduced and extending to the first opening; and using the resist film as a mask, forming the semiconductor. A method for manufacturing a semiconductor device, comprising the step of implanting impurity ions into a substrate and causing charges generated on an ion-irradiated surface during the ion implantation to flow into the semiconductor substrate through the scribe line. . (3) When selectively implanting impurity ions into a semiconductor substrate using a resist film as a mask, a resist pattern is formed on the semiconductor substrate to selectively cover regions where impurity introduction is avoided, and the resist pattern is The method includes the step of performing ion implantation using a mask and causing charges generated on the ion irradiated surface during the ion implantation to flow into the semiconductor substrate through an opening in the exposed field insulating film on the semiconductor substrate. A method for manufacturing a featured semiconductor device.