JPH03500585A - Enhanced input/output architecture for toroidally connected distributed storage parallel computers - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] This invention aims to improve the input/output capacity and efficiency of a toroidally connected distributed storage type parallel computer. Concerning rate improvement.

Background technology In an effort to achieve more processing power for computation, many computer designers Suitable for column processing. However, various computer architectures that employ parallel processing There is Kucha.

Parallel processing computers come in two general types: those with shared storage processing units; and distributed storage type processing devices. shared storage type A computer includes multiple processing units that can access the same storage device. contrast Generally speaking, a distributed storage computer has a processing unit with each independent storage device. ing. Communication between distributed storage type processing units is carried out by a communication interconnect. . This invention specifically relates to a distributed storage type parallel processing computer, and more specifically to a distributed storage type parallel processing computer. Regarding connected computers.

The performance of a toroidally connected distributed storage parallel computer depends on several factors: , the total storage capacity of the computer, the number of processing units in the computer, and the amount required by the given problem. communications between processing units that are limited by the degree. In most parallel computers, the number of processing units and their Storage capacity can be easily modified to suit whatever requirements exist. The first two factors are relatively unimportant. The third factor, processing equipment Communication between plants is the subject of extensive and intensive research (Lin and Maltpan "M 2 Mesh: Extended Mesh Architecture” 1st International Conference on Parallel Processing Minutes, page 306, and Carlson, “Metz with a Global Metz” "Flexible high-speed organization for parallel computing" 1st national conference on ultra-high-speed computing (See Minutes of the International Conference, page 618).

For use with large data sets (e.g. image processing or database inspection) In contrast, input/output (1/○) requirements are also important in regulating the overall throughput of parallel computers. This can be a sufficient factor.

In this specification, the word "toroidal" is understood to include the word "metsu". Ru.

Two common parallelism modes often used: distributed and pipelined There is. Distributed processing means that every processing device handles different subsets of data in the same way. Requires performing an action. Pipeline processing means that every processing device processes the same set of data. require different actions on the data. toroidally connected computation Although the machine is particularly suited to operating in both modes, there are problems.

Attempts to provide adequate Ilo generally include an I10 channel for each processing unit node. and writing to various processing devices via control channels. Including making. This method is suitable for distributed processing, but the chip cost (chjp cost) and circuit board area, it is relatively expensive (Nagi's US special Patent No. 4.514,807 “Parallel Computer” and Thinking Machines Inc. “ Connection Machine”, Intel Scientific Computers "Hyper Cube" manufactured by the company and "N Cube" manufactured by N cube (N cube) Ncube) / IOJ commercial products). Furthermore, on the I10 channel Feeding devices present another bottleneck.

An alternative approach that is sometimes taken up is to perform Ilo with only one processing unit and avoid parallel processing. further distributing data using an interconnected network of physical devices. This method is cheap However, it is subject to bandwidth constraints.

These general methods cannot perform Ilo with multiple data sources or destinations. stomach. This makes it useful when working with other computing and data storage or generation devices. Sexuality is restricted. Both of these methods involve pipelined and distributed parallel processing. cannot be equally valid for both. Both of these methods Unable to provide Bruna I/O speeds. The main advantages of parallel systems One is its performance flexibility (additional processing units can be added to improve calculation performance). I10 performance and hardware should be scaled in the same way. It is important to scale.

The purpose of this invention is to provide a toroidally connected distributed storage device which eliminates the above-mentioned problems. The purpose of this invention is to provide a more effective architecture for type parallel computers.

Disclosure of invention The goal is to create a Trojan with multiple rows of processing units, each with independent storage. In a parallel parallel computer with distributed memory connected in parallel, a) at least one common I10 channel; and b) said common I10 channel. a one-line processing device (1 10) connected to the C) a plurality of buffer mechanisms, each associated with a particular processing unit of said 110 lines. Thus, each buffer mechanism allows any given I10 processing unit of 110 rows to Regardless of the channel's access to the buffer mechanism, and line 110 above. that buffer, regardless of its access to the buffer mechanism of other processing units in Connect the ■10 channels to the processing unit so that you can access the mechanism. and a plurality of buffer mechanisms, which are configured to effectively facilitate data distribution. This is achieved through improvements.

A mesh or toroid is defined by its topological structure (topological structure). The structure can be resized or rotated without destroying it. , a reference to a processor in one row can be thought of as a reference to a processor in a column. Ru.

Brief description of the drawing FIG. 1 shows a prior art toroidal connection with a control processor inserted in one row. Shows a connected computer.

Figure 2 shows an input/output (Ilo) row with an I10 channel and one I10 channel. An associated I10 buffer is associated with each processing unit in line 110. A toroidally connected distributed storage parallel computer according to the present invention using a mechanism shows.

Figure 3 includes two rows of I10 processing units connected to separate I10 channels. 1 shows a toroidally connected computer according to this invention.

FIG. 4 shows the method used in accordance with this invention, using conventional storage, arbitration and busbar methods. The I10 buffer mechanism is shown.

FIG. 5 shows another example of a conventional dual-port storage device used in accordance with the present invention. The I10 buffer mechanism of FIG.

FIG. 6 shows a first-in, first-out buffer with handshake control logic. Connect high-speed parallel data I10 ports to processing equipment using bidirectional latches in 3 shows yet another I10 buffer scheme adapted to do so.

Figure 7 shows that one 110 row is connected to the I10 channel realized as a normal busbar. 3 shows an embodiment of the invention, similar to FIG.

Figure 8 shows that 110 rows are connected to high-speed parallel inputs and another 110 rows are connected to high-speed parallel outputs. 1 shows an embodiment of the invention with parallel processing devices connected;

Mode for carrying out the invention This invention provides improved input/output operation in a toroidally connected parallel meter W machine. related to the architecture of

FIG. 1 shows a number of processing units 12 interconnected with a communication channel 14, and one 1 shows a prior art array 10 with node controllers 16 inserted in rows; each Processing unit 12 has independent storage. The node controller 16 is toroidal Serves as an entry point to the closed side of the processing unit. 11 any row of the array It can be selected as row 0. The number of these lines depends on the particular application intended.

FIG. 2 shows 110 particular rows connected in accordance with the present invention. This process Device row 20 can be accessed directly from I10 channel 26. I10cha A channel is any mechanism that can rapidly transfer large amounts of information. Typically, I1 0 channel is the standard computer bus or parallel I10 board shown in Figures 4 and 5. It is. Line 110 connects each processing unit directly to a different buffer mechanism 24. It's set. Each buffer mechanism has ■10 channels fast with any one of the buffers Provides storage and control equipment so that communication can be performed independently.

Any given processing device can complete its input cycle or output cycle. Communicate with the associated buffer mechanism. Any processing device may have I1 with other buffer mechanisms. 0 accesses its associated buffer independent of channel or processing unit activity need to be able to. In addition to the related processing equipment, only the I10 channel has access to the buffer, and other processing units communicate only with its own buffer. be able to. The I10 channel and processing unit communicate with one buffer at a time. equipment to arbitrate these communications must be provided. Must be. The I10 channel or processing unit is the main buffer (fflaste). r of the buffer), and therefore an appropriate arbitration mechanism must include structure. While the processing unit is processing one data set, r The buffer is large enough that 10 channels can communicate different data sets. If made, it can also be useful.

I10 channels and processing units in each channel for any particular application. The combination of is a design consideration. Figure 3 shows that two rows are used for Ilo. It shows the form in which it is used. Connecting multiple rows to the same I10 channel It is also possible.

Turning to FIG. 4, a mechanism 24 with an arbitration and control circuit 32 and a storage device 34 is shown. It is. This configuration provides access to storage device 34 from processing unit 12 or channel 26. access. Such a configuration 24 has already been created and the storage device 34 Along with standard random access storage (RAM) for arbitration and control The standard bus request/grant and data read/write signals that implement the circuit 32 The tail is often used. The processing unit is the master of the circuit 24. to read and write information to the storage device.

For example, when I10 channel 26 desires to communicate with storage device 34, The I10 channel first sends a request signal to the processing unit. Therefore, the processing unit It stops communication with the device 34 and sends an acknowledge signal back to the I10 channel 26.

In FIG. 5, dual port storage 36 is double buffer storage (double buffer storage). cd-buffOred mcmory”). Double buffer storage , the two separate mechanisms (in this case the I10 channel and the processing unit) are the same. A storage device that can be accessed simultaneously and independently. This results in Figure 6. Eliminating the need for special arbitration and control circuitry as shown.

Figure 6 shows a latch/FIFO memory buffer that temporarily operates as shown below. Another mechanism 24 is shown including 38.

Data is transferred to buffer 38 by the processing unit or port depending on the direction of data transfer. Given. FIFO (first in, first out buffer) is used when receiving a data available signal. reads the data into the buffer.

Upon receiving a data request signal, the FIFO writes out the data.

Ports and processing units may communicate directly (using the handshake signals described above). However, the FIFO is not used by the processing unit or port until the buffer is full. allows clients to transfer data at different speeds for short periods of time.

The various elements constituting this invention are arranged in a modular manner, distributed type or pipeline type. can be interconnected to provide in-type operation. For example, a single printing layout A wire board is used to create a line of the processing unit and its associated buffer and control mechanism 24. 110 rows with channels can be provided. If the processing unit is a separate printing It can also be provided on a wire plate. In Figure 7, the distributed mode of operation is realized. . In Figure 8, various elements are shown in both distributed and pipelined modes. selected to provide a configuration that can be employed. In this arrangement, two A separate I10 channel printed wiring board is used. Any number of I10 boards as busbars and interconnected as one row of a processing device array. array of Any row can have a set of I10 boards and associated channels.

FIG. 7 shows a channel 26 in the form of a bus bar coupled to a calculator 50. . A display device 52 is also connected to the computer 5o. This structure is distributed type and pipe It was configured in line type processing mode and worked well. Inmos, Bristol, UK "Inmos Transputer" manufactured by putter) J was used as the processing device. The control node also has the same transp It was Tatea. Facility 24 was a dynamic random access storage device.

I10 channel 26 was implemented with an industry standard VME bus. Host used Computer 50 was a Sun J workstation. Arbitration is busbar request /permit, read/write, data available/configuration using request and acknowledge signals This was accomplished in the usual way by a defined busbar protocol.

Three separate printed wires, each with a different storage capacity associated with each storage device The board was realized. Furthermore, one of these printed wiring boards has four parts as shown in Figure 2. A 110-line system was realized with a processing device of. These printed wiring boards are compatible as described above. Four treatments are interconnected and have various row lengths and column heights in a toroidal arrangement. We configure computers of various sizes, ranging from physical units to 96 processing units. these While processing a large data set, the computer uses critical communication connections to parallel processing units. workstation host (workstati) without encountering bottlenecks. on host).

Using this invention, it is possible to easily change the I10 arrangement of processing equipment. . For pipelined applications, in one row, as shown in Figure 8, One I10 channel serves as the data input and another I10 channel serves as the data input. Can function as data output. Therefore, data is processed in each stage. flowing through the structure. When faster or slower data or throughput is required The array (and associated 110 rows) can be made more spacious while keeping the number of processing units constant. narrower or narrower. Instead, the processing speed changes, increasing the I10 throughput speed. If the degree is kept constant, the array will be make it higher or shorter by removing or adding OroνS) be able to. Processing speed changes by adding or removing processing devices, but No hardware is added. This increases both computational power and I10 throughput. cost-effective and flexible performance.

As mentioned above, FIG. 8 can be used equally well for distributed processing. different The I10 channel may be used as a data source and/or destination.

Having multiple I10 channels provides additional capabilities. processing equipment The entire array can operate as a switching network. source data It can read from an I10 channel and direct it to another I10 channel.

effect This invention provides improved I for toroidally connected distributed memory parallel computers. 10 performance. This invention provides a solution between the requirements of the processing unit and the I10 hardware. cost-effectively balance the implementation of multi-instruction, multi-data (MIMD) parallel processors. It shows a practical and flexible implementation. The invention utilizes a processing device array. array wider or narrower so that more (or fewer) processing units are on the I10 line. data (the buffering hardware has to adapt to this speed). (must be able to change the data rate) Ru. A simple torus or mesh has at least one row or column of 110 paths each. Any number of data by using a large number of rows or columns, such as It can have an I10 route. The above considerations explain the various needs of pipeline type and large flexibility in meeting large Ilo requirements for distributed and distributed processing. Gives you the ability. Common rows and associated buffers also meet the requirements of different applications You can adapt the size by extending or adding 110 lines like so: local cache for data storage and function. By providing a fast interface to This makes the individual processing devices and their interconnections relatively slow, simple, and inexpensive. I can do it.

Furthermore, if multiple I10 channels are used, the processing unit array can be reduced to a simple It can function as a switching network.

FIG. 5 ￥Koi 7゛ru Tako Rine I FIG. 7 FIG.8 international search report m+’mm+a’1keNtn-1t@, PCT/US ElB103340 country international investigation report

Claims (5)

[Claims] 1. Toroidally connected with rows of processing units, each with independent storage In a distributed memory parallel computer, a) at least one common I/O channel and b) the processing device adapted to be connected to the common I/O channel. (I/O) line and c) a plurality of buffer mechanisms, each associated with a particular processing unit of said I/O line; Each buffer mechanism specifies that any given I/O processing device in an I/O row The mechanism can be configured independently and before access to the buffer mechanism by the I/O channel. access to the buffer mechanism of other processing units on the I/O line. Connect the processing device to the I/O channel so that it can access and multiple buffer mechanisms, thereby effectively facilitating data distribution. A calculator characterized by: 2. Two I/O channels, each accessing a different I/O row, and each I/O A channel and its particular I/O line have associated multiple buffer mechanisms. 2. The computer according to claim 1. 3. 2. The computer of claim 1, wherein each buffer tree includes dual port storage. 4. The computer according to claim 1, wherein each buffer mechanism includes a FIFO buffer in a latch type. . 5. A first I/O channel receives input data in parallel and transfers the data to its I/O channel. O row, and a second I/O channel receives processed data from that I/O row. 3. A computer according to claim 2, wherein the computer receives and sends the data as parallel output.