JPH0344357U - - Google Patents
Info
- Publication number
- JPH0344357U JPH0344357U JP10210789U JP10210789U JPH0344357U JP H0344357 U JPH0344357 U JP H0344357U JP 10210789 U JP10210789 U JP 10210789U JP 10210789 U JP10210789 U JP 10210789U JP H0344357 U JPH0344357 U JP H0344357U
- Authority
- JP
- Japan
- Prior art keywords
- receiving circuit
- address field
- frame
- hdlc
- hdlc receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Landscapes
- Communication Control (AREA)
Description
第１図は本考案の実施例によるＨＤＬＣ受信回
路の構成を示すブロツク図、第２図は従来のＨＤ
ＬＣ受信回路の構成を示すブロツク図、第３図は
ＨＤＬＣのフレームの例を示す概略構成図である
。
主要部分の符号の説明、１……フラグ検出・Ｏ
削除回路、２……受信データシフトレジスタ、３
……ＣＲＣチエツク回路、４……局番号レジスタ
、５……照合回路、６……受信シーケンス制御回
路。
Figure 1 is a block diagram showing the configuration of an HDLC receiver circuit according to an embodiment of the present invention, and Figure 2 is a block diagram of a conventional HDLC receiver circuit.
FIG. 3 is a block diagram showing the configuration of the LC receiving circuit. FIG. 3 is a schematic configuration diagram showing an example of an HDLC frame. Explanation of the symbols of the main parts, 1...Flag detection/O
Deletion circuit, 2... Receive data shift register, 3
...CRC check circuit, 4...station number register, 5...verification circuit, 6...reception sequence control circuit.
Claims (1)
レームを受信するＨＤＬＣ受信回路であつて、前
記フレームが他局宛であることを前記アドレスフ
イールドが示したときにそれ以後の受信制御シー
ケンスを停止する制御手段を有することを特徴と
するＨＤＬＣ受信回路。 An HDLC receiving circuit that receives a frame including an address field indicating a destination station, and a control means that stops a subsequent reception control sequence when the address field indicates that the frame is addressed to another station. An HDLC receiving circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10210789U JPH0344357U (en) | 1989-08-31 | 1989-08-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10210789U JPH0344357U (en) | 1989-08-31 | 1989-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0344357U true JPH0344357U (en) | 1991-04-24 |
Family
ID=31651026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10210789U Pending JPH0344357U (en) | 1989-08-31 | 1989-08-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0344357U (en) |
-
1989
- 1989-08-31 JP JP10210789U patent/JPH0344357U/ja active Pending
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