JPH032896A - V-ram display device - Google Patents

Abstract

PURPOSE:To curtail the hardware, to reduce the software and to improve the utilization efficiency of a V-RAM by providing two sets of V-RAMs of a packed pixel system, allowing a host to correspond to an access space and bringing the hardware to access to the V-RAM concerned, and synthesizing and displaying them. CONSTITUTION:This device is provided with two sets of V-RAMs 1 of a packed pixel system for writing an image, and in accordance with a plane access space or a packed pixel access space from a host, a plane access converting circuit 2 or a packed pixel access circuit 3 brings one V-RAM concerned 1 to access, and also, the contents of these two V-RAMs 1 are synthesized and displayed. In such a way, the hardware can be curtailed, the software can be reduced, and the utilization efficiency of the V-RAM can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding a V-RAM display device that displays the contents of V-RAM by plain access and packed pixel access, two sets of packed pixel type V-RAM are provided and the space accessed by the host is Correspondingly, the hardware accesses the corresponding V-RAM and synthesizes and displays it, reducing hardware, software, and V-RAM.
With the aim of improving the utilization efficiency of
M, a brain access conversion circuit that performs packed pixel access to the one V-RAM in response to access to the plane access space from the host, and a brain access conversion circuit that accesses the packed pixel access space from the host in response to the access to the packed pixel access space from the host. a packed pixel access circuit for accessing another V-RAM as a packed pixel; 1? It is configured to access the AM and to synthesize and display the contents of these two V-RAMs.

[Industrial application field]

The present invention relates to a V-RAM display device that displays the contents of V-RAM using brain access and packed pixel access, and relates to a V-RAM display device for personal computers and game machines for hobby, education, and industry. be.

[Problems to be solved by conventional technology and invention] Conventional V
-RAM (Video RAM) display devices have had multiple sets of V-RAM access methods due to output circuit limitations. For this reason, the brain access method, which is suitable for text processing, and the packed pixel method, which is suitable for multicolor graphics, cannot coexist, and this has been dealt with by duplication of software or equipment.

Therefore, there is a problem in that software and hardware are duplicated, there is a lot of waste, and unused bits of packed pixels occur.

The present invention uses a packed vixel type V-RAM as 2i,
The hardware accesses one V-RAM corresponding to the space accessed by the host, synthesizes it, and displays it, reducing the amount of hardware and software and improving the efficiency of V-RAM usage. The purpose is to achieve this goal.

[Means to solve problems]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, V-RAMI is two sets of packed pixel type video RAMs into which images are stored.

The brain access conversion circuit 2 converts one V-RA in response to access from the host to the brain access space.
This is a packed pixel access to MI.

The packed pixel access circuit 3 performs packed pixel access to another V-RAMI in response to the access from the host to the packed pixel access space.

[Effect]

As shown in FIG. 1, the present invention provides a packed pixel-type 2Ml V-RAMI that stores 8 images, and provides brain access in response to access from the host to the brain access space or packed pixel access space. Conversion circuit 2 or packed pixel access circuit 3
accesses one applicable V-RAMI, and
The contents of these two V-RAMIs are combined and displayed.

Therefore, in response to the space accessed by the host (brain access space, packed pixel access space), the hardware performs packed pixel access to the corresponding V-RAM, and also synthesizes and displays the contents of these RAMs. , hardware reduction, software reduction, and V-r? It becomes possible to improve the efficiency of AM usage. .

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 1 to 4.

In Figure 1, if V-RAMI is a text VR
Comprised of AMI-1 and VRAM1-2 for graphics, packed pixel type 2 for writing images.
This is a set of video RAMs.

The brain access conversion circuit 2 performs packed pixel access to the V-RAMI-1 in response to the access from the CPU 4 to the plane access space (brain access area in FIG. 3).

The packed pixel access circuit 3 responds to the access from the CPU 4 to the packed pixel access space (packed pixel access area in FIG. 3) by using the V-RAMI.
-2 is a packed pixel access.

The CPU 4 accesses the brain access space or the packed pixel access space to draw text or graph ink on the screen.

The digital section 5 includes V-RAMI-1 and VRAM1-
4. To synthesize the digital image signals read from 2.
(see figure) and converts it into an analog image signal.

The CRT 6 is for displaying images. As shown in the lower part of the image, priority is given to displaying text, and pixels without text display are displayed graphically (see FIG. 4).

FIG. 2 shows a packed pixel structure and a brane structure. The 4-bit punctured pixel structure shown in the figure is
(1) degree), G (green), R (red), and B (blue) are assigned to 1 pixel (1 pixel, corresponding to 1 O in the figure), and 8 pixels are grouped together. be. In the case of graph ink display, the CPU 4 accesses the packed pixel access space to draw in units of pixels (pixel units). In this case, the punctured pixel access circuit 3 in FIG.
1? AM1-2 is accessed.

The brane structure is [0 (intensity 0) to I7 (intensity 7)
, GO or G7, RO or R7, BO or B7
8 pixels (corresponding to 8 O in the figure) are summarized. In the case of text display, the CPU 4 accesses the plane access space and draws in units of branes. In this case, the brain access conversion circuit 2 shown in FIG.
I am trying to access l-1.

FIG. 3 shows an example of a memory map according to the present invention. The packed pixel access area is the %MH where CPLI4 performs packed pixel access.

When you access this packed pixel access area,
Figure 1: Punctured pixel access circuit 3 is V-RAMI
-2 is accessed.

On the other hand, the brain access area is an area where the CPU 4 performs brain access. When this brain access area is accessed, the brain access conversion circuit 2 in FIG. 1 converts the brain access into a packed pixel access and accesses V-RAMI-1.

FIG. 4 shows an example of switching between text display/graphic ink display according to the present invention. This is to give priority to character display over graphic display, and to read out digital image data from V-RAM1-1 and V-RAMI-2 in FIG. Example of unit switching: 0 For example, if there is text image data, the text image data (V-
(image data read from RAMI-1) is sent as the combined image data, and on the other hand, if there is no text image data, the graph ink image data is sent as the combined image data. . The synthesized digital image data is converted into analog image data and input to the CRT 6 to display the image.

〔Effect of the invention〕

As described above, according to the present invention, two sets of packed pixel type V-RAMs are provided, and the hardware corresponds to the V-RAM that corresponds to the space accessed by the host (plain access space, packed pixel access space). RAM
In addition to accessing banked pixels, these V-R
Since a configuration is adopted in which the contents of AM are synthesized and displayed, it is possible to reduce hardware, reduce software processing, and improve V-RAM usage efficiency. In particular, the CPU 4 can access the packed pixel access space or the brain access space in each method as needed without being aware that the V-RAMI is a packed pixel, and can perform drawing processing at high speed. It becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of one embodiment of the present invention, FIG. 2 is an example of a packed pixel/brane structure, FIG. 3 is an example of a memory map according to the present invention, and FIG. 4 is a switching between text display/graphic display according to the present invention. Give an example. In the figure, 1.1-1 and 1-2 are V-RAMs, 2 is a brain access conversion circuit, 3 is a packed pixel access circuit, 4 is a CPU, 5 is a digital section, and 6 is a CRT.

Claims (1)

[Claims] In a V-RAM display device that displays the contents of V-RAM through plain access and packed pixel access, two sets of V-RAMs using the packed pixel method for writing images are provided.
M (1), a plane access conversion circuit (2) that performs packed pixel access to the one V-RAM (1) in response to access to the plane access space from the host, and a packed pixel access space from the host. a packed pixel access circuit (3) that performs packed pixel access to the other one V-RAM (1) in response to access from the host; The circuit (2) or the packed pixel access circuit (3) accesses any one of the V-RAMs (1) and is configured to synthesize and display the contents of these two V-RAMs (1). A V-RAM display device characterized by: