JPH03255657A - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPH03255657A
JPH03255657A JP2054119A JP5411990A JPH03255657A JP H03255657 A JPH03255657 A JP H03255657A JP 2054119 A JP2054119 A JP 2054119A JP 5411990 A JP5411990 A JP 5411990A JP H03255657 A JPH03255657 A JP H03255657A
Authority
JP
Japan
Prior art keywords
chips
board
integrated circuit
circuit device
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2054119A
Other languages
Japanese (ja)
Inventor
Akio Koyanagi
小柳　昭夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2054119A priority Critical patent/JPH03255657A/en
Publication of JPH03255657A publication Critical patent/JPH03255657A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enable components to be densely mounted on a board by a method wherein two IC chips are mounted on the board making their rear sides overlap each other, and one of them is connected through a flip chip bonding method and the other is connected through a wire bonding method. CONSTITUTION:Two IC chips 3 bonded together through a non-conductive adhesive agent 5 making their rear sides overlap each other are mounted on a board 1. The IC chips 3 are mounted on the board 1 through such a way that in one of the IC chips 3, a metallized electrode 2 provided onto the board 1 is electrically connected to a metallized electrode 12 formed on the chip 3 with a bump 6 through a flip chip bonding method, and in the other of the IC chips 3, the metallized electrodes 2 and 12 are electrically connected together with a gold wire 4 through a wire bonding method.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は混成集積回路装置に関し、特に２つの重なって
いるＩＣチップを実装した混成集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device mounting two overlapping IC chips.

〔従来の技術〕[Conventional technology]

従来の混成集積回路装置は、第２図に示すように、基板
１上に２個のＩＣチップ３を横に並べて同一平面上にマ
ウン１−　Ｌ、ＩＣチップ３のメタライズ電極１２と基
板上のメタライズ電１２を金線４で電気的に接続して実
装されていた。As shown in FIG. 2, in a conventional hybrid integrated circuit device, two IC chips 3 are arranged side by side on a substrate 1, mounted on the same plane, and the metallized electrode 12 of the IC chip 3 and the metallized electrode 12 on the substrate are mounted on the same plane. It was mounted by electrically connecting metallized wires 12 with gold wires 4.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の２個のＩＣチップを基板上に実装する方
法としては、第２図に示すように、ＩＣチップ３を横に
並べて同一平面上に実装されていた。As shown in FIG. 2, the conventional method for mounting two IC chips on a substrate is to arrange the IC chips 3 side by side and mount them on the same plane.

しかしながら、ＩＣチップ３２個分のスペースが基板１
上に必要になり、実装面積の低減をはかるには限界があ
った。However, the space for 32 IC chips is limited to one board.
Therefore, there was a limit to reducing the mounting area.

本発明の目的は、実装面積の低減により、高密度実装が
可能な混成集積回路装置を提供することにある。An object of the present invention is to provide a hybrid integrated circuit device that can be mounted at high density by reducing the mounting area.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、ＩＣチップを実装した混成集積回路装置にお
いて、２個の前記ＩＣチップのそれぞれの裏面を重ねて
一方の前記ＩＣチップをフリップチップ接続と、他方の
前記ＩＣチップをワイヤーボンディング接続を用い実装
されている。The present invention provides a hybrid integrated circuit device mounting IC chips, in which the back surfaces of two IC chips are overlapped, one of the IC chips is connected by flip-chip connection, and the other IC chip is connected by wire bonding. Implemented.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of one embodiment of the present invention.

第１図に示すように、基板１上に、２個のＩＣチップ３
のそれぞれの裏面を非導電性接着剤５により接続し、一
方をフリップチップ接続を用いて基板１上のメタライズ
電極２とＩＣチップ上に形成されたメタライズ電極１２
をバンプ６により電気的に接続し、他方をワイヤーボン
ディング接続を用いてメタライズ電！２．１２を金線４
により電気的に接続し、基板１上に実装されている。As shown in FIG. 1, two IC chips 3 are placed on a substrate 1.
The back surfaces of each are connected with a non-conductive adhesive 5, and one side is connected to the metallized electrode 2 on the substrate 1 and the metallized electrode 12 formed on the IC chip using flip-chip connection.
is electrically connected by bump 6, and the other is connected using wire bonding to metallize the electrode! 2.12 gold wire 4
are electrically connected and mounted on the substrate 1.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、一方をフリップチップ接
続と他方をワイヤーボンディング接続を用いて、２個の
ＩＣチップのそれぞれの裏面を重ねて基板上に実装する
ことにより部品搭載を高密度化できる効果がある。As explained above, the present invention enables high-density component mounting by mounting two IC chips on a board with their respective back sides overlapped using flip-chip connection on one side and wire bonding connection on the other side. effective.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の断面図、第２図は従来の混
成集積回路装置の１例の断面図である。 １・・・基板、２．１２・・・メタライズ電極、３・・
・ＩＣチップ、４・・・金線、５・・・非導電性接着剤
、６・・・バンプ。FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional hybrid integrated circuit device. 1... Substrate, 2.12... Metallized electrode, 3...
- IC chip, 4... Gold wire, 5... Non-conductive adhesive, 6... Bump.

Claims (1)

【特許請求の範囲】[Claims] ＩＣチップを実装した混成集積回路装置において、２個
の前記ＩＣチップのそれぞれの裏面を重ねて一方の前記
ＩＣチップをフリップチップ接続と、他方の前記ＩＣチ
ップをワイヤーボンディング接続を用い実装することを
特徴とする混成集積回路装置。In a hybrid integrated circuit device in which IC chips are mounted, the back surfaces of two IC chips are overlapped, and one of the IC chips is mounted using flip-chip connection, and the other IC chip is mounted using wire bonding connection. Features of hybrid integrated circuit device.
JP2054119A 1990-03-05 1990-03-05 Hybrid integrated circuit device Pending JPH03255657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2054119A JPH03255657A (en) 1990-03-05 1990-03-05 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2054119A JPH03255657A (en) 1990-03-05 1990-03-05 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH03255657A true JPH03255657A (en) 1991-11-14

Family

ID=12961712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2054119A Pending JPH03255657A (en) 1990-03-05 1990-03-05 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH03255657A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327325A (en) * 1993-02-08 1994-07-05 Fairchild Space And Defense Corporation Three-dimensional integrated circuit package
WO1996017505A1 (en) * 1994-12-01 1996-06-06 Motorola Inc. Method, flip-chip module, and communicator for providing three-dimensional package
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US5767570A (en) * 1993-03-18 1998-06-16 Lsi Logic Corporation Semiconductor packages for high I/O semiconductor dies
US5815372A (en) * 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
WO2001037332A1 (en) * 1999-11-16 2001-05-25 Indian Space Research Organisation A high density hybrid integrated circuit package having a flip-con structure
KR20020016278A (en) * 2000-08-25 2002-03-04 듀흐 마리 에스. Improved Method of Mounting Chips in Flip Chip Technology Process
US6452279B2 (en) 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US7015063B2 (en) 1998-03-31 2006-03-21 Micron Technology, Inc. Methods of utilizing a back to back semiconductor device module
US7906852B2 (en) 2006-12-20 2011-03-15 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of the same

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5327325A (en) * 1993-02-08 1994-07-05 Fairchild Space And Defense Corporation Three-dimensional integrated circuit package
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US5767570A (en) * 1993-03-18 1998-06-16 Lsi Logic Corporation Semiconductor packages for high I/O semiconductor dies
WO1996017505A1 (en) * 1994-12-01 1996-06-06 Motorola Inc. Method, flip-chip module, and communicator for providing three-dimensional package
US6337227B1 (en) 1996-02-20 2002-01-08 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6165815A (en) * 1996-02-20 2000-12-26 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6989285B2 (en) 1996-05-20 2006-01-24 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US7371612B2 (en) 1996-05-20 2008-05-13 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5815372A (en) * 1997-03-25 1998-09-29 Intel Corporation Packaging multiple dies on a ball grid array substrate
US7015063B2 (en) 1998-03-31 2006-03-21 Micron Technology, Inc. Methods of utilizing a back to back semiconductor device module
US7057291B2 (en) * 1998-03-31 2006-06-06 Micron Technology, Inc. Methods for securing vertically mountable semiconductor devices in back-to back relation
US7282789B2 (en) 1998-03-31 2007-10-16 Micron Technology, Inc. Back-to-back semiconductor device assemblies
WO2001037332A1 (en) * 1999-11-16 2001-05-25 Indian Space Research Organisation A high density hybrid integrated circuit package having a flip-con structure
US6452279B2 (en) 2000-07-14 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
KR20020016278A (en) * 2000-08-25 2002-03-04 듀흐 마리 에스. Improved Method of Mounting Chips in Flip Chip Technology Process
US7906852B2 (en) 2006-12-20 2011-03-15 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of the same

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