JPH03212955A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent malfunctions by a method wherein the wiring of a logic circuit group is separated from the wiring of an output buffer transistor group. CONSTITUTION:Pads P14a, P16a of power-supply lines 14a, 16a are independent of each other and are connected to independent power-supply pins Vdd1, Vdd2 by using wires W10, W12. Consequently, the lines 14a, 16a are separated and are independent of each other on a semiconductor integrated circuit 8. Since pads P14b, P16b of connecting lines 14b, 16b are connected to independent ground pins VSS1, VSS2 by using wires W14, W16, the lines 14b, 16b are separated and are independent of each other on the circuit 8. The pins VSS1, VSS2 are connected to a ground line GND which has been fixed to a stable ground potential; a stable positive power supply is fed to the pins Vdd1, Vdd2. Thereby, a ground noise by a switching operation of output buffer transistor groups 12a, 12b is absorbed by the line GND via the wire W14 and the pin VSS1 from the pad P14b, and is not propagated to an internal circuit 10. Thereby, the malfunction of a logic circuit is prevented surely and a stable circuit operation can be secured.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a logic circuit group and an output buffer transistor group that outputs a signal to an external terminal based on an output signal of the logic circuit group.

[Conventional technology]

2. Description of the Related Art Today, semiconductor integrated circuits (LSI) are being increasingly miniaturized, and along with this miniaturization, semiconductor integrated circuits are becoming larger in scale and have more bins. With this increase in the number of pins, the number of output bins tends to increase significantly.9 For example, some PLAs (Programmable Logic Arrays) have as many as 144 output bins (which also serve as input bins). Inside the semiconductor integrated circuit, an output buffer transistor consisting of a P-channel MOS transistor T1 and an N-channel MOS transistor T2 as shown in FIG. 5, for example, is provided corresponding to such an output pin. Drives the accompanying load and sends a signal to the outside. Since this load is usually relatively large, on the order of several tens to several hundreds <1) F, the current driving capability of the output buffer transistor is set to be large. When an output buffer transistor with a large current drive capacity performs a switching operation, a large instantaneous current flows through the power supply and ground lines inside the semiconductor integrated circuit, and due to the presence of parasitic impedance in the power supply and ground lines, Fluctuations in power supply/ground potential, that is, power supply/ground noise may occur. This noise increases as the number of output pins, ie, the number of output buffer transistors, increases, causing circuit malfunction. The means to prevent circuit malfunction from this power supply/ground noise are as follows:
Various methods have been considered for preventing circuit malfunctions due to ground noise, for example, as shown in FIG. In the means shown in FIG. 6, the grounding lines between the output buffer transistor groups 2a and 2b inside the semiconductor integrated circuit 3 and the other internal circuits 1 are respectively constituted by wirings AI and A2 made of aluminum, for example. Line Al, A
By branching 2 near the pad P where the potential is relatively stable, the output buffer transistor groups 2a and 2b
The ground noise generated in the internal circuit 1 from the ground wire A1
This prevents the signal from propagating to the ground wire A2. Therefore, the potential of the ground line A is stabilized, and the output buffer transistor group 2a
, 2b can prevent the internal circuit 1 from malfunctioning due to the noise generated. Also, regarding power supply noise, the power supply, *A3, and A4 (not shown) are provided with the same means as described above to prevent circuit malfunction.

[Problem to be solved by the invention]

However, in the conventional technology, although the potential near the bad P is relatively stable, when the number of output buffer transistors increases significantly, the instantaneous current associated with the switching operation of the buffer transistors also increases significantly. In short, there is a problem in that impedance between the pad P and an external power supply device that supplies power and ground potential becomes apparent, and the potential near the pad P fluctuates, leading to circuit malfunction. On the other hand, power supply/ground noise becomes apparent due to the presence of parasitic impedance of the power supply/ground line and impedance between the pad P and the external power supply, so if these impedances are reduced, Power supply/ground noise can be prevented. however,
Due to constraints such as thinning of wiring due to V & thinning of semiconductor integrated circuits and reduction of wiring width to reduce chip area, the impedance has been increased to the extent that it can sufficiently cope with a significant increase in the number of output buffer transistors. There is a practical limit to reducing the size of the wiring, and there is a problem that it is not an effective solution to the above-mentioned problem. Attempts have been made to reduce the impedance by parallelizing the power supply and ground lines and increasing the cross-sectional area of the wiring layer metal, but even with this technology, there is a practical limit to reducing the impedance. be. The present invention has been made in view of the above-mentioned conventional problems, and
An object of the present invention is to provide a semiconductor device that does not cause circuit malfunction even when power supply/ground noise increases due to the increase in the scale of semiconductor integrated circuits and the significant increase in the number of bins.

[Means to solve the problem]

The present invention provides a semiconductor device having a logic circuit group and an output buffer transistor group that outputs a signal to an external terminal based on an output signal of the logic circuit group. The first for supplying the potential
wiring, and a positive power supply to the output buffer transistor group.
A second wiring for supplying a negative power supply or a ground potential is provided independently, and a positive power supply, a negative power supply, or a ground potential is transmitted from the outside to each of the first and second wirings. The above problem is solved by including first and second power transmission means. Further, a plurality of the first and second power transmission means can be provided for each of the first and second wirings. Thereby, noise propagation can be more effectively prevented, and circuit malfunctions can be prevented even more reliably. The second wiring can be formed so that only the power source input to the source of the output buffer transistor is independent. As a result, even with a significant increase in the number of output buffer transistors, noise propagation can be reliably prevented and circuit operation can be stabilized.

[Effect]

In the present invention, in a semiconductor device having a logic circuit group and an output buffer transistor group, a first wiring for supplying a positive power supply, a negative power supply, or a ground potential to the logic circuit group; A second wiring for supplying a power supply, a negative power supply, or a ground potential is provided independently, and the first and second power supply means
and a positive power supply to a negative power supply from the outside to each of the second wiring,
Alternatively, the first wiring of the logic circuit group and the second wiring of the output buffer transistor group are separated by supplying a ground potential. Therefore, the power supply/ground noise generated by the switching operation of the output buffer transistor is prevented from propagating to the logic circuit group via the power supply/ground line.
The logic circuit will not malfunction due to noise generated in the output buffer transistor group.

【Example】

Embodiments of the present invention will be described in detail below with reference to the drawings. First, a first example will be explained. FIG. 1 is a plan view of a semiconductor integrated circuit 8 according to the first embodiment. As shown in FIG. 1, this semiconductor integrated circuit 8 includes an internal circuit 10 consisting of a logic circuit group, first and second output buffer transistor groups 12a and 12b, and a positive output buffer transistor group 12a and 12b. Pads P14a=P14b are connected to the negative part for supplying power and ground potential.
and a power line 1 having pads P16a and P16b in part thereof for supplying a positive power source and a ground potential to the internal circuit F#r10.
6a and ground line 16b, and independent power supply bins Vdd+ and V for transmitting positive power supplied from an external power supply device (not shown) to the power supply lines 14a and 16a, respectively.
dd2 and wires WI O, Wl 2, and the ground potential from the power supply device (not shown) are connected to the ground +1!14b, 16b.
Each independent ground h'n VSS
+, VSS2, and wires W14 and Wl6. Pads P14a and P16a of the power supply lines 14a and 16a
are independent from each other as shown in FIG.
It is connected to Vdd2. Therefore, each power line 1
4a and 16a are semiconductor integrated diagrams F! They are separated and independent from each other on @8. Further, the pads P14b and P16b of the grounding wires 14b and 16b are independent from each other, as shown in FIG. W16 is connected to each independent grounding bin VSS1, VSS2. Therefore, the ground lines 14b and 16b are separated and independent from each other on the semiconductor integrated circuit 8. The grounding bins VSSt and VSS2 are connected to a grounding line GND which has sufficiently low impedance and is fixed to a stable grounding potential, and this grounding line GND is supplied with a grounding potential from a power supply device (not shown). Further, the power supply bins VdL and Vdd2 similarly have sufficiently low impedance and are supplied with stable positive power from a power supply device (not shown). In this embodiment, each ground line 14b, 16b is connected to the ground line GND fixed at a stable ground potential as described above.
Since the wiring is branched into the wire W, the ground noise generated by the switching operation of the output buffer transistor groups 12a and 12b is routed from the ground pad P14b to the wire W.
14, only reaches the grounding line GND via the grounding bin Vss, and is absorbed by this grounding line GND, and other internal circuits 1
0 through the ground line GND. In the first embodiment, the output buffer transistors 12 constituting the first and second output buffer transistor groups 12a and 12b are, for example, as shown in FIG.
Consider a case where the device is configured with an N-channel MO3) transistor provided on a P-type substrate 22, or a case where a CMOS structure is used. In the circuit of FIG. 2, the output buffer transistor 12
A ground potential is supplied to the internal circuit 10 by a ground line 14b made of aluminum, and a ground potential is supplied to the internal circuit 10 by a ground line 16b made of aluminum. In addition, the second
In the figure, reference numeral 20 denotes an N-channel MOS transistor constituting the internal circuit 10. As shown in FIG. 2, the potential (
The source potential) may be fixed by connecting the ground line 14b and using the ground potential; however, in this case, the N-channel MOS transistor 20 constituting the internal circuit 10
Since the ground line 16b made of aluminum is used to fix the substrate potential near the substrate 22, there is a risk that ground noise generated in the output buffer transistor 12 will propagate to the internal circuit 10 via the substrate 22. The noise propagation through the substrate 22 is caused by the fact that the equivalent resistance "P" of the substrate is sufficiently large compared to the resistance r1, r2 of the grounding wires 14b, 16b. Although the extent of the noise is smaller than the propagation, the effect cannot be ignored if the number of output buffer transistors 12 increases significantly.Therefore, in order to take all possible measures to prevent the propagation of such ground noise, As shown in FIG. 3, as a ground line for fixing the substrate potential around the output buffer transistor 12, a ground line other than the aluminum wiring 14-b that supplies the ground potential to the output buffer transistor is used, for example, as a ground line of the internal circuit 10. By using the ground wire 16b as shown by the solid line in the figure, an even further noise prevention effect can be obtained.In addition to using the ground wire 16b, as shown in FIG.
A new grounding line 16c as shown by the broken line in FIG. 3 may be newly installed branching from the vicinity of the grounding line 16b. These grounding lines 16b and 16c can be used and wired depending on the ease of layout. Note that although the countermeasures against ground noise have been explained above, the pad P14a can also be used against power supply noise.
, P16a are separated, similar effects can be obtained. This first embodiment is suitable for supplying different power to each power supply bin and each power line when a semiconductor integrated circuit becomes large-scale and requires a plurality of power supplies. Next, a second example will be described. FIG. 4 is a plan view of the semiconductor integrated circuit 8 according to the second embodiment. In the second embodiment, in the semiconductor integrated circuit of the first embodiment, when the pads P14b and P16b are adjacent to each other, the grounding bin VSS of the first embodiment is applied. One common grounding bin VSS is provided instead of vss2, and wires W14 and W from pads P14b and P16b
16 are commonly connected to the grounding pin Vss. In this case, since the resistance value of the ground pin VSS is almost negligible, the same effect as in the first embodiment can be obtained by reducing the number of ground pins. Furthermore, when power is supplied from multiple large-scale power sources, it is suitable to provide power to each wiring by providing each wiring in the configuration as in the first embodiment, but in this first embodiment, Considering the case where the voltage is fixed, similar effects can be obtained with the configuration of the second embodiment. In the first and second embodiments, pads P14a, P14b, P16a, and P16b, which supply power and ground potentials to the output buffer transistors and internal circuits, are connected to power lines and ground lines 14a, 14b, 16a, and 16, respectively.
One pad was provided for each pad b, but as the number of output bins increases, if these pads are added as appropriate and connected to the output bins, a more stable positive power supply/ground potential can be obtained. Furthermore, in the first and second embodiments, as shown in FIGS. 2 and 3, a semiconductor integrated circuit formed on a P-type substrate was illustrated, but the semiconductor device in which the present invention can be implemented is as follows. The present invention is not limited to semiconductor integrated circuits configured on such P-type substrates, but can be similarly applied to semiconductor devices having structures of other conductivity types. Furthermore, in the first and second embodiments, a MOS transistor was used as an example of the output buffer transistor, but
The transistors constituting a semiconductor integrated circuit when implementing the present invention are not limited to this type of transistor, and the present invention can also be applied to a semiconductor device using other bipolar transistors, for example. Further, in the first and second embodiments, the positive power source is supplied from the power line and the ground potential is supplied from the ground line, but the power source supplied to the semiconductor device in which the present invention is implemented is limited to this type. However, the present invention can be implemented when supplying any power source including a negative power source.

【Effect of the invention】

As explained above, according to the present invention, when power supply/ground noise is generated from the output buffer transistor, the propagation of the noise is prevented to reliably prevent malfunction of the logic circuit, thereby ensuring stable circuit operation. be able to. In particular, an excellent effect can be obtained in that it is possible to reliably cope with the increase in the scale of semiconductor devices and the significant increase in the number of output bins included therein, and to obtain stable circuit operation.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the configuration of a semiconductor integrated circuit according to a first embodiment of the present invention; FIG. 2 is a vertical cross-sectional view showing the detailed configuration of an output buffer transistor and an internal circuit of the semiconductor integrated circuit; FIG. 3 is a longitudinal sectional view, FIG. 4 is a plan view of a main part of a semiconductor integrated circuit showing a second embodiment of the present invention, and FIG. 5 is a circuit showing a configuration of a typical output buffer transistor. FIG. 6 is a plan view of a main part showing an example of the configuration of power supply/ground wiring of a conventional semiconductor integrated circuit. 8... Semiconductor integrated circuit, 10... Internal circuit, 12... Output buffer transistor, 12a, 12b
... Output buffer transistor group, 14a, 16a.
...Power supply line for the output buffer transistor group and internal circuit, 14b, 16b...Ground line for the output buffer transistor group and internal circuit, WIO to W16...Wire, Vdd+, Vdd2-power supply bin, VSS+, VSS2-ground Bin, GND...Grounding wire, P14a, P16a, P14b, P16b...
Power supply pad, 20... N channel MOS transistor, 22...
Substrate, rp...Equivalent resistance within the substrate.

Claims (3)

[Claims] (1) In a semiconductor device having a logic circuit group and an output buffer transistor group that outputs a signal to an external terminal based on an output signal of the logic circuit group, the logic circuit group is connected to a positive power source, a negative power source, or a ground potential. and a second wiring for supplying a positive power source, a negative power source, or a ground potential to the output buffer transistor group, respectively provided independently, Connect each wire to an external positive power supply,
A semiconductor device comprising first and second power transmission means for transmitting a negative power supply or a ground potential. (2) The semiconductor device according to claim 1, wherein a plurality of said first and second power transmission means are provided for each of said first and second wirings. (3) The semiconductor device according to claim 1 or 2, wherein the second wiring is formed so that only a power source input to the source of the output buffer transistor is independent.