JPH03209672A - Data detecting circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of the data detecting circuit by constituting plural registers for storing the signal levels of reproduced signals so that the signal levels are stored in the descending order. CONSTITUTION:Input bit data S0 from a register R0 are compared with the storage bit data S1 of a register R1 by a comparator C1, a selector SL1 is controlled through a controller 3 in accordance with the compared result, and when the data S0 are smaller than the data S1, the data S0 are stored in the register R2 without changing the contents of the register R1, so that reproduced signals are stored in respective registers R1 to Rn in the descending order of signal levels. Data 1 are stored in registers CR1 to CRn corresponding to the registers R1 to Rn storing the data and the number of comparators is minimized only to n units, so that the constitution of the data detecting circuits can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention relates to a data detection circuit, for example, a so-called 4/15
The present invention relates to a data detection circuit that detects data from a signal modulated using a modulation method using a so-called difference detection method.

B0 Summary of the Invention The present invention comprises n storage means arranged in series for storing the signal level of an input signal, and a connection between each storage means to store the input signal level or the signal stored in the previous storage means. n-1 selection means for selecting a level and outputting the selected signal level to the subsequent storage means, and n comparison means for comparing the input signal level with the signal level stored in each of the storage means. and control means for controlling each of the storage means and each selection means so that the top n of the input signal levels are stored in the storage means based on the comparison results from each comparison means. Accordingly, the signal level of the reproduced signal is stored in the n storage means in descending order, and the data is reproduced.

C9 Prior Art In recent years, new recording media such as optical disks and magneto-optical disks have been developed and are becoming popular. Research is being conducted on how to record data on these recording media at high density. Research is also being conducted on how to increase the transmission speed in data transmission.

By the way, when data is recorded on a recording medium at a high density exceeding a certain value and then reproduced, or when the data transmission speed is increased, the individual reproduced waveforms overlap each other due to so-called code amount interference, resulting in errors during reproduction. was.

However, code amount interference can be controlled if the characteristics of the reproduction system and the characteristics of the transmission path are known. That is, when the characteristics of the reproduction system and transmission path are known, high-density recording or high-speed data transmission that tolerates code amount interference to a certain extent can be realized by making good use of the property of code amount interference. For example, as a modulation method, 4/15 (4 out
of 15) modulation etc. are known, and 4/1
A so-called differential detection method is known as a means for demodulating a signal modulated by 5 modulation or the like and reproducing data.

The above-mentioned 4/15 modulation is a modulation method in which 8-bit data is converted to 15-bit data, and there are always four "1"s in 15 bits (hereinafter referred to as one block). In addition, the difference detection method described above is useful when reproducing data from a signal modulated by a modulation method such as 4/15 modulation that selects a predetermined n bits within a fixed number of m bits. Detecting predetermined n signal levels in descending order of levels,
For example, data is reproduced by setting these as "1".

FIG. 2 is a circuit diagram of a data detection circuit that detects the top n signal levels of the above-mentioned recurrent signal used in the conventional difference detection method. The data detection circuit shown in FIG. 2 will now be explained.

A signal level obtained by sampling a reproduction signal reproduced from, for example, an optical disk or the like using a predetermined clock signal using an A/D converter (not shown) and converting it into a digital signal is supplied to the register RO via a terminal 50. be done. The reproduced signal is a signal modulated using a modulation method that selects a predetermined n focus within m bits as described above.

The output S of register RO is sent to registers R1-Rn and comparators 001-C1n. The output S of the register R1
, are supplied to the comparators CI2 to C1n and the comparator C01, and the output S2 of the register R2 is supplied to the comparators C23 to C2n and the comparators 002 to C12. Similarly below,
The output S7 of the last register Rn is connected to the comparator C0n-C(n
-1) supplied to n.

Comparator CQi (i=1 to n) is the output S0 of register RO
and the output S8 of the register R4, and sends the comparison result to the controller 51. The comparator C11 (1-2 to n) compares the output St of the register R1 and the output S8 of the register Ri, and sends the comparison result to the controller 51. Send to controller 5I. Similarly, the last comparator C(n-1) n is the output sn-1 of the register Rn-1 and the output S of the register Rn. and sends the comparison result to the controller 51.

The controller 51 controls the registers R1 to Rn and the register C based on the comparison results from the comparators CO1 to Cn-1n.
enable signals EN+ to EN that control RI to CRn;
Output. Moreover, the registers CR1 to CRn have m
The count value from the advance counter 52 is supplied.

That is, first, in synchronization with the input of the reproduction signal of the first bit of one block consisting of m bits, the register R1
~Rn, CRI~CRn, and the counter 52 are reset (cleared) by the initial setting signal INT, and the signal level of the reproduced signal of the first bit is stored in the register RO.

Next, the signal levels of n reproduced signals from the beginning of one block are sequentially stored in registers R1 to Rn, and
Registers CRI to CRn store count values from the counter 52 representing bit positions corresponding to signal levels stored in registers R1 to Rn, for example, rl to "n," respectively.

Continuously, when the signal level of the reproduced signal of the (n+1)th bit of one block is input, the controller 51:
Registers R1-Rn and CRI-CRn are updated based on the comparison results of comparators CO1-Cn-1n. for example,
Output S0 of register RO and output 5 of registers R1 to Rn
The minimum value of l-5,l is compared and the output S of register RO
When 0 is large, the register R in which the minimum value is stored
Enable signals EN, ~E are applied so that the output S0 of register RO is stored in i, and the current count value "n+1" is stored in register CRi corresponding to this register R1.
N, is used for control. Also, the output S0 of register RO
is small, the controller 51 sends an enable signal EN so as not to perform the above switching operation.

~EN, controlled using l.

The controller 51 repeatedly performs the above-described switching operation up to the last bit of one block. As a result, the register R
1-Rn stores n signal levels from the maximum signal level in l block, and register CRI-C
Rn stores count values, ie, bit positions, corresponding to the signal levels stored in registers R1 to Rn.

This stored bit position is taken out from terminals T1 to Tn.

D1 Problems to be Solved by the Invention As mentioned above, in the conventional circuit configuration for realizing the difference detection method, the number of comparators required to detect the top n signal levels from the maximum signal level is limited. For example, in the case of 4/15 modulation, 10 comparators are required and the circuit configuration is complicated.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data detection circuit with a small number of comparators and a simpler circuit configuration than the conventional one.

E9 Means for Solving Problems The data detection circuit according to the present invention has n storage means arranged in series for storing the signal level of an input signal, and connects each storage means to store the signal level of an input signal. n-1 selection means for selecting signal levels stored in the storage means at the previous stage and outputting the selected signal levels to the storage means at the rear stage; and input signal levels and signals stored in the respective storage means described above. n comparison means for comparing the levels, and each of the storage means so that the top n of the input signal levels are stored in the storage means based on the comparison results from each of the comparison means; The above problem is solved by having a control means for controlling each selection means.

F0 operation In the data detection circuit according to the present invention, the signal levels of input signals are stored in n storage means in descending order.

G. Embodiment An embodiment of the data detection circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a data detection circuit to which the present invention is applied.

For example, the signal level of the reproduced signal reproduced from an optical disk or the like is sampled using a predetermined clock signal using an A/D converter (not shown) and converted into a digital signal. Supplied via

The reproduced signal is a signal modulated using a modulation method that selects a predetermined n bit out of m bits.

Output S0 of register RO is register R1, selector 5L
It is supplied to I-5Ln-1 and comparators 01 to Cn. The output S of the register R1 is supplied to the selector SLI and the comparator C1, and the output S2 of the register R2 is supplied to the selector SL2 and the comparator C2. Similarly, the output S, , of the last register Rn is supplied to the comparator Cn. Further, each output of the selector 5L1=SLn-1 is supplied to the registers R2 to Rn, respectively.

The comparators C1 to Cn are the outputs S of the register RO. and each output S1'''''S- of the registers R1 to Rn, and sends the comparison result to the controller 3.

The controller 3 controls the registers R1 to Rn and the register C based on the comparison results from the comparators C1 to Cn.
Enable signals EN, ~EN, controlling RI~CRn;
, and the selectors SL1 to 5Ln-1
and outputs control signals SEL, -SEL, -+ for controlling selectors C3LI-C3Ln-1.

The above register CRI and selectors C3LI to C3Ln-
1 is supplied with the output (count value) C30 of the m-adic counter 2. Each output C5 of the above registers CRI to CRnI
+ to C3ll-1 are respectively supplied to selectors C3LI to C3Ln-1, and each output of selectors C3LI to C3Ln-1 is supplied to registers CR2 to CRn, respectively.

Thus, in this embodiment, the registers R1 to Rn are
The selectors SLI to 5L are used as n storage means arranged in series to store the signal level of the input signal.
n-1 selects n1 selections which connects each register R1 to Rn, selects a human signal level or a signal level stored in the storage means at the previous stage, and outputs the selected signal level to the storage means at the subsequent stage. The comparator C1
~Cn are used as n comparison means for comparing the input signal level with the signal level stored in each register R1-Rn, and the controller 3
Based on the comparison results from 1 to Cn, each register R1 to Rn and each selector SLI to
It is used as a control means to control 5Ln-1.

Next, the operation will be explained.

First, registers R1 to Rn are activated in synchronization with the input of the first bit of one block consisting of m pinpoints.

The counter 2 and the registers CRI to CRn are reset (cleared) by the initial setting signal INT, and the signal level of the reproduction signal of the first bit is stored in the register RO.

Next, the controller 3 stores the signal level of the reproduction signal of the first bit of one block in the register R1, and
The enable signal ENI is used to control the output C5o of the counter 2, that is, to store, for example, "1" in the register CR1, which represents the bit position corresponding to the signal level stored in the register R1.

Subsequently, the signal level of the reproduced signal of the second focus of one block is input, and after this signal level is stored in the register RO, the controller 3 adjusts the reproduced signal based on the comparison results of the comparators C1 to Cn. The signal levels of registers R1 to Rn are stored in descending order, and each register R1 to R
The enable signal EN is set so that the output C3D of the counter 2 representing the focus position corresponding to the signal level of the reproduced signal stored in the registers CR1 to CRn is stored in the registers CR1 to CRn.
I-EN, and control signals SEL+-5EL-+. For example, controller 3 has register RO
When the signal level of the output S0, that is, the reproduced signal of the second bit of l block, is smaller than the signal level of the output S of register R1, that is, the signal level of the reproduced signal of the first bit of one block, it is stored in register R1. The enable signal is set so that the output S0 of register RO is stored in register R2 without changing the contents, and "2" is stored in register CR2 without changing the contents stored in register CRI, that is, "1". Control is performed using ENI-UN and control signals SEL1 to SEL, -+. Further, for example, when the signal level of the output S0 of the register RO, that is, the reproduction signal of the second bit of the l block, is higher than the signal level of the output SI of the register R1, that is, the reproduction signal of the first bit of the l block, ,
The output S0 of the register RO is stored in the register R1, the output S of the register R1 is stored in the register R2, and
Enable signal EN to store "2" in register CRI and store output C5+ of register CRI, ie "1", in register CR2.

~EN, 1 and control signal SEL+ '=SEL, 1-
Control using +.

The controller 3 repeatedly performs the above-described operation of rearranging the reproduced signals in descending order of signal level up to n bits of one block.

Subsequently, the signal level of the reproduced signal of the (n+1)th bit of one block is inputted, and after this signal level is stored in the register RO, the controller 3 controls the comparators C1 to Cn.
The signal levels of the reproduced signals are stored in registers R1 to Rn in ascending order based on the comparison results of
The enable signals EN, ~EN and the control signals SEL, ~SEL are used to store the output CSo of the counter 2, which represents the bit position corresponding to the signal level of the reproduced signal stored in ~Rn, in the registers CRI~CRn. Control using , , . For example, the controller 3 determines that the signal level of the output S0 of the register RO, that is, the reproduction signal of the (n+1)th focus of one block, is the output S0 of the register Rn.
, when it is smaller than 1, registers R1 to Rn, CR1=
In order not to change the contents stored in CRn, enable signals EN, ~EN and control signals SEL, ~5
Control using EL-+. Further, for example, when the signal level of the output S0 of the register RO, that is, the reproduction signal of the n+1-th bit of the l block, is smaller than the output S of the register Ri and larger than the output S i + 1 of the register Ri+1, , stores the output S0 of register RO in register Ri+1, shifts the contents stored in registers after register Ri+1 by one, and stores "rn+1" in register CRi+1, which is stored in registers after register CR4+1. enable signals EN, ~EN, to shift the contents by one;
and control signals 5EL1 to 5EL-+.

The controller 3 repeatedly performs the above-described switching operation up to the last bit of one block.

That is, in the comparators C1 to Cn, the output S0 of the register RO and each output S1 to S of the registers R1 to Rn are compared m-1 times in the same block, and n signal levels are compared in descending order of signal level. enable signals ENI-EN, and so as to sequentially store in the registers R1-Rn, and store the output C3O of the counter 2 representing the bit position corresponding to the signal level stored in the registers R1-Rn in the registers CRI-CRn; Control signals SEL, ~S
Control using EL, , -+. As a result, register R
1-Rn stores n signal levels in order from the maximum signal level in l block, and registers CRI to CRn
The count values, that is, the bit positions corresponding to the signal levels stored in the registers R1 to Rn are stored in the registers R1 to Rn. The bit positions stored in these registers CRI-CRn are taken out from terminals T1-Tn, and data reproduction is performed.

As is clear from the above description, in this embodiment, the number of comparators is n and the circuit configuration of the data detection circuit can be simplified. Further, by reducing the number of comparators in this manner, the data detection circuit can be easily integrated into an IC.

Note that the present invention is not limited to the above embodiments, and for example, 5 bits of data can be converted into 7 bits (1 block).
5-, where there are always three marks in one block.
7 modulation method, 4-bit data is converted to 6-bit data (1 block), and each block always has 3 marks.
-6 modulation methods, 8 histo data to 11 pins (1)
The present invention may be applied to other modulation methods such as the 4/11 modulation method in which four marks always exist in an l block. Furthermore, the present invention may be applied to, for example, a reproduction system for data transmission.

Furthermore, in this embodiment, the signal level of the reproduced signal is converted to a digital signal and the signal processing described above is performed, but it is also possible to perform signal processing as an analog signal using a sample hold circuit, an analog switch, etc. You may also do so.

H0 Effects of the Invention As is clear from the above explanation, in the present invention, the register for storing the signal level of the reproduced signal is configured to store the signal levels in descending order of the signal level, thereby achieving an improvement over the conventional method. The number of comparators can be significantly reduced. As a result, the data detection circuit can be simplified. Furthermore, since the number of comparators can be significantly reduced, the data detection circuit can be easily integrated into an IC.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a data detection circuit according to the present invention,
FIG. 2 is a circuit diagram of a conventional data detection circuit. RO~Rn...Register SLI~5Ln-1...Selector C1~Cn...Comparator 3...Controller

Claims (1)

[Scope of Claims] n storage means arranged in series for storing the signal level of an input signal; and a connection between the storage means to store the input signal level or the signal level stored in the previous storage means. n-1 selection means for selecting the input signal level and outputting the selected signal level to the subsequent storage means; and n comparison means for comparing the input signal level with the signal level stored in each of the storage means. , control means for controlling each of the storage means and each selection means so that the top n of the input signal levels are stored in the storage means based on the comparison results from each of the comparison means. A data detection circuit characterized by: