JPH03191574A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH03191574A
JPH03191574A JP33202389A JP33202389A JPH03191574A JP H03191574 A JPH03191574 A JP H03191574A JP 33202389 A JP33202389 A JP 33202389A JP 33202389 A JP33202389 A JP 33202389A JP H03191574 A JPH03191574 A JP H03191574A
Authority
JP
Japan
Prior art keywords
film
silicon
silicon film
type
element formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33202389A
Other languages
Japanese (ja)
Inventor
Hideyuki Ooka
大岡 秀幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP33202389A priority Critical patent/JPH03191574A/en
Publication of JPH03191574A publication Critical patent/JPH03191574A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To enhance a resistant property to an electrostatic breakdown by a method wherein a silicon film is formed on the surface of a source-drain diffusion layer formed on a silicon substrate, a high-melting metal film formed on the surface of the silicon film is formed and a high-melting metal silicide film is formed on the surface of the silicon film by a reaction. CONSTITUTION:A field oxide film 2 is formed selectively on one main face of a P-type silicon substrate 1; an element formation region is partitioned; a source region and a drain region 8. 9 of an opposite conductivity type, i.e., of an N<+> type, are provided inside the element formation region so as to be aligned with gate electrodes 4, 5; and insulating sidewall parts 10 are formed on side faces of the gate electrodes 4, 5. A silicon film 11 is grown on the surface of the N<+> type diffusion layers 8, 9. A titanium film 12 is deposited on the surface including the silicon film 11; it is reacted with the silicon film 11; a titanium silicide film 13 is formed; and after that, the titanium film 12 which has not been reacted is removed; a high-melting metal silicide film is formed. Thereby, it is possible to relax that an electric current supplied form a contact is concentrated in gate-electrode end parts of the sourcediffusion layer and the drain-diffusion layer 8, 9; and it is possible to enhance an electrostatic breakdown strength.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に、絶縁ゲート型電界効
果トランジスタを有する半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an insulated gate field effect transistor.

〔従来の技術〕[Conventional technology]

半導体集積回路の高密度化のため、素子寸法は益々微細
化されている。このため、絶縁ゲート型電界効果トラン
ジスタ(以下MOSトランジスタと記す)も縮小されね
ばならないが、この際、短チヤネル効果が問題となるこ
とが、知られている。
Due to the increasing density of semiconductor integrated circuits, element dimensions are becoming increasingly finer. For this reason, insulated gate field effect transistors (hereinafter referred to as MOS transistors) must also be reduced in size, but it is known that short channel effects pose a problem in this case.

短チヤネル効果を防ぐ方法の1つとして、トランジスタ
のソース・ドレインの拡散深さを浅くすることが考えら
れる。しかし、拡散層を浅くすると、層抵抗が高くなる
ため、拡散層による配線抵抗が増大し、回路の動作速度
が著しく減少するという問題が生じる。
One possible way to prevent the short channel effect is to reduce the diffusion depth of the source and drain of the transistor. However, if the diffusion layer is made shallow, the layer resistance becomes high, which causes the problem that the wiring resistance due to the diffusion layer increases and the operating speed of the circuit decreases significantly.

上記の問題を解決する方法として、第5図に示すように
、P型シリコン基板1に形成したソース・ドレイン領域
のN+型型数散層89の表面にチタン膜を堆積し、その
後熱処理を行なうことにより、チタン膜とシリコン基板
1を反応させて硅化チタン膜13を形成し、浅い拡散層
の低抵抗化を実現する方法が提案されている。
As a method to solve the above problem, as shown in FIG. 5, a titanium film is deposited on the surface of the N+ type scattering layer 89 in the source/drain region formed on the P type silicon substrate 1, and then heat treatment is performed. Accordingly, a method has been proposed in which a titanium silicide film 13 is formed by causing a reaction between a titanium film and a silicon substrate 1 to realize a low resistance of a shallow diffusion layer.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置は、拡散層表面と直接反応さ
せて設けた高融点金属硅化物膜を有するMOS)ランジ
スタにおいて、その静電破壊(electrostat
ic discharge:ESD)耐圧が劣化すると
いう問題が、例えばクエインーロン・チェ7(Kuei
ng−Long Chen)らによりアイイーデイ−エ
ム・テクニカル・ダイジェス) (IEDMTechn
ical Digest) 1986年、484〜48
7頁に報告されている。
The above-mentioned conventional semiconductor device suffers from electrostatic breakdown (electrostat) in a MOS (MOS) transistor having a high melting point metal silicide film formed by directly reacting with the surface of a diffusion layer.
For example, the problem of deterioration of IC discharge (ESD) withstand voltage has been
ng-Long Chen) et al.
ical Digest) 1986, 484-48
It is reported on page 7.

これは、拡散層表面が高融点金属硅化物膜により低抵抗
化さhたため、フンタクトから供給された電流が、ソー
ス・ドレイン拡散層のゲート電極端部に集中し、局所的
な接合の熱破壊が生じ易くなったためと考えられている
This is because the surface of the diffusion layer has a low resistance due to the high melting point metal silicide film, so the current supplied from the mount concentrates on the end of the gate electrode of the source/drain diffusion layer, resulting in local thermal damage to the junction. It is thought that this is because it is more likely to occur.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、−導電型半導体基板の一主面に
設けたフィールド酸化膜により区画された素子形成領域
と、前記素子形成領域の表面に設けたゲート絶縁膜の上
に設けたゲート電極と、前記ゲート電極に整合して前記
素子形成領域内に設けた逆導電型のソース・ドレイン領
域を有する半導体装置において、前記ゲート電極の側面
に設けた絶縁性側壁部と、前記側壁部に隣接して前記ソ
ース・ドレイン領域の表面に設けたシリコン膜と、前記
シリコン膜の上面に設けた高融点金属硅化物膜とを有す
る。
The semiconductor device of the present invention includes: - an element formation region partitioned by a field oxide film provided on one principal surface of a conductive type semiconductor substrate; and a gate electrode provided on a gate insulating film provided on the surface of the element formation region; and an insulating sidewall portion provided on a side surface of the gate electrode, and an insulating sidewall portion adjacent to the sidewall portion in a semiconductor device having source/drain regions of opposite conductivity type provided in the element formation region in alignment with the gate electrode. and a high melting point metal silicide film provided on the upper surface of the silicon film.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(h)は本発明の第1の実施例の製造方
法を説明するための工程順に示した半導体チップの断面
図である。
FIGS. 1A to 1H are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the first embodiment of the present invention.

まず、第1図(a)に示すように、P型シリコン基板1
0−主面に選択的にフィールド酸化膜2を設けて素子形
成領域を区画し、素子形成領域の表面を熱酸化してゲー
ト酸化膜3を形成する。次に、ゲート酸化膜3を含む表
面に気相成長法により多結晶シリコン膜4及び硅化タン
グステン膜5をそれぞれ0.1〜0.3μmの厚さに順
次堆積し、硅化タングステン膜5の上に気相成長法によ
り酸化シリコン膜6を0.05〜0.2μmの厚さに堆
積する。
First, as shown in FIG. 1(a), a P-type silicon substrate 1
0- A field oxide film 2 is selectively provided on the main surface to define an element formation region, and a gate oxide film 3 is formed by thermally oxidizing the surface of the element formation region. Next, a polycrystalline silicon film 4 and a tungsten silicide film 5 are sequentially deposited to a thickness of 0.1 to 0.3 μm on the surface including the gate oxide film 3 by a vapor phase growth method, and the tungsten silicide film 5 is A silicon oxide film 6 is deposited to a thickness of 0.05 to 0.2 μm by vapor phase growth.

次に、酸化シリコン膜6の上にホトレジスト膜7を塗布
してパターニングし、ゲート電極形成用のパターンを形
成する。
Next, a photoresist film 7 is applied and patterned on the silicon oxide film 6 to form a pattern for forming a gate electrode.

次に、第1図(b)に示すように、ホトレジスト膜7を
マスクとして酸化シリコン膜6及び硅化タングステン膜
5並びに多結晶シリコン膜4を順次工、チングして除去
し、多結晶シリコン膜4及び硅化シリコン膜5の2層構
造からなるゲート電極を形成する。次に、ホトレジスト
膜7を除去した後、ゲート電極及びフィールド酸化膜2
をマスクとしてヒ素イオンをイオン注入して素子形成領
域にソース・ドレイン領域用のN+型型数散層89を形
成する。
Next, as shown in FIG. 1(b), using the photoresist film 7 as a mask, the silicon oxide film 6, the tungsten silicide film 5, and the polycrystalline silicon film 4 are sequentially etched and removed. A gate electrode having a two-layer structure of a silicon silicide film 5 and a silicon silicide film 5 is formed. Next, after removing the photoresist film 7, the gate electrode and field oxide film 2 are removed.
Using the mask as a mask, arsenic ions are implanted to form an N+ type scattering layer 89 for source/drain regions in the element formation region.

次に、第1図(c)に示すように、ゲート電極を含む表
面に酸化シリコン膜10を気相成長法により堆積する。
Next, as shown in FIG. 1(c), a silicon oxide film 10 is deposited on the surface including the gate electrode by vapor phase growth.

次に、第1図(d)に示すように、全面を異方性エツチ
ングしてゲート電極の側面にのみ酸化シリコン膜10を
残して他の領域の酸化シリコン膜10を除去し、N+型
型数散層89の表面を露出させる。
Next, as shown in FIG. 1(d), the entire surface is anisotropically etched to leave the silicon oxide film 10 only on the side surfaces of the gate electrode and remove the silicon oxide film 10 in other areas, thereby forming an N+ type silicon oxide film. The surface of the dispersed layer 89 is exposed.

次に、第1図(e)に示すように、N+型型数散層89
の表面に選択成長法を用いてシリコン膜11を0,1〜
0.4μmの厚さに成長させる。
Next, as shown in FIG. 1(e), the N+ type scattering layer 89
A silicon film 11 is grown on the surface of the silicon film 11 using a selective growth method.
It is grown to a thickness of 0.4 μm.

次に、第1図(f)に示すように、シリコン膜11を含
む表面にスバ、り法によりチタン膜12を0.05〜0
.5μmの厚さに堆積する。
Next, as shown in FIG. 1(f), a titanium film 12 of 0.05 to 0.0
.. Deposit to a thickness of 5 μm.

次に、第1図(g)に示すように、熱処理によりチタン
膜12とシリコン膜11を反応させて硅化チタン膜13
を形成した後、未反応のチタン膜12を除去する。
Next, as shown in FIG. 1(g), the titanium film 12 and the silicon film 11 are caused to react with each other by heat treatment to form a titanium silicide film 13.
After forming, the unreacted titanium film 12 is removed.

次に、第1図(h)に示すように、全面に層間絶縁膜と
してPSG膜14を堆積して選択的にコンタクトホール
な形成する0次にコンタクトホールを含む表面にアルミ
ニウム膜15を堆積して選択的に工、チングし、コンタ
クトホールの硅化チタン膜13と接続しPSG膜14の
上に延在する配線を形成する。
Next, as shown in FIG. 1(h), a PSG film 14 is deposited as an interlayer insulating film over the entire surface, and an aluminum film 15 is deposited on the surface including the zero-order contact hole to selectively form a contact hole. Then, a wiring is formed which connects to the titanium silicide film 13 in the contact hole and extends over the PSG film 14.

第2図(a)〜(d)は本発明の第2の実施例の製造方
法を説明するための工程順に示した半導体チップの断面
図である。
FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the second embodiment of the present invention.

第2図(a)に示すように、第1の実施例と同様の工程
によりゲート酸化膜3までを形成した後、ゲート酸化膜
3の上に多結晶シリコン膜4及び酸化シリコン膜6を順
次堆積し、酸化シリコン膜6及び多結晶シリコン膜4を
選択的に順次エツチングしてゲート電極を設ける。次に
ゲート電極及びフィールド酸化膜2をマスクとしてリン
イオンを低濃度にイオン注入してN−型拡散層16,1
7を形成する。次に、ゲート電極を含む表面に酸化シリ
コン膜10を堆積した後エッチバックしてゲート電極の
側面にのみ酸化シリコン膜1oを残して側壁部を形成し
、側壁部及びフィールド酸化膜2をマスクとしてヒ素イ
オンを高濃度にイオン注入してN−型拡散層16.17
に接続するN+型型数散層89を形成する。次に、リン
をドープした多結晶シリコン膜18を気相成長法により
堆積し、多結晶シリコン膜18の上にホトレジスト膜1
9を塗布してバターニングする。
As shown in FIG. 2(a), after forming up to the gate oxide film 3 through the same steps as in the first embodiment, a polycrystalline silicon film 4 and a silicon oxide film 6 are sequentially formed on the gate oxide film 3. The silicon oxide film 6 and the polycrystalline silicon film 4 are selectively and sequentially etched to form a gate electrode. Next, using the gate electrode and field oxide film 2 as a mask, phosphorus ions are implanted at a low concentration into N- type diffusion layers 16 and 1.
form 7. Next, a silicon oxide film 10 is deposited on the surface including the gate electrode, and then etched back to form a side wall portion, leaving the silicon oxide film 1o only on the side surfaces of the gate electrode, and using the side wall portion and field oxide film 2 as a mask. N-type diffusion layer 16.17 by implanting arsenic ions at high concentration
An N+ type scattering layer 89 connected to the N+ type scattering layer 89 is formed. Next, a polycrystalline silicon film 18 doped with phosphorus is deposited by vapor phase growth, and a photoresist film 1 is deposited on the polycrystalline silicon film 18.
Apply No. 9 and butter it.

次に、第2図(b)に示すように、ホトレジスト膜19
をマスクとして多結晶シリコン膜18をエツチングし、
N+型型数散層89に接続するコンタクト層を設ける0
次に、ホトレジスト膜19を除去した後、全面にモリブ
デン膜20をスバ。
Next, as shown in FIG. 2(b), the photoresist film 19
The polycrystalline silicon film 18 is etched using as a mask.
A contact layer connected to the N+ type scattering layer 89 is provided.
Next, after removing the photoresist film 19, a molybdenum film 20 is formed over the entire surface.

り法により堆積する。It is deposited by the method.

次に、第2図(c)に示すように、熱処理を行い多結晶
シリコン膜18とモリブデン膜20を反応させて硅化モ
リブデン膜21を形成し、未反応のモリブデン膜20を
除去する。
Next, as shown in FIG. 2(c), a heat treatment is performed to cause the polycrystalline silicon film 18 and the molybdenum film 20 to react to form a molybdenum silicide film 21, and the unreacted molybdenum film 20 is removed.

次に、第2図(d)に示すように、第1の実施例と同様
に全面にPSG膜14を堆積してコンタクトホールを設
け、コンタクトホールの硅化モリブデン膜21と接続し
てPSG膜14の上に延在するアルミニウム膜15によ
る配線を設け、LDD構造を有する半導体装置を構成す
る。
Next, as shown in FIG. 2(d), a contact hole is formed by depositing a PSG film 14 on the entire surface as in the first embodiment, and the PSG film 14 is connected to the molybdenum silicide film 21 in the contact hole. A semiconductor device having an LDD structure is constructed by providing wiring made of an aluminum film 15 extending over the semiconductor device.

なお、N+型型数散層89は多結晶シリコン膜18より
リンを拡散させて形成しても良い。
Note that the N+ type scattering layer 89 may be formed by diffusing phosphorus from the polycrystalline silicon film 18.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、シリコン基板上に形成さ
れたソース・ドレイン拡散層の表面にシリコン膜を形成
し、このシリコン膜表面に形成した高融点金属膜とシリ
コン膜の上面を反応させて高融点金属硅化物膜を形成す
ることにより、ゲート電極端部における高融点金属硅化
物膜とソース・ドレイン拡散層の界面における電流集中
を緩和して、静電破壊耐性を向上させるという効果を有
する。
As explained above, the present invention involves forming a silicon film on the surface of a source/drain diffusion layer formed on a silicon substrate, and causing a high melting point metal film formed on the surface of the silicon film to react with the upper surface of the silicon film. By forming a high melting point metal silicide film, it has the effect of alleviating current concentration at the interface between the high melting point metal silicide film and the source/drain diffusion layer at the end of the gate electrode, and improving resistance to electrostatic discharge damage. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(h)及び第2図(a)〜(d)は本発
明の第1及び第2の実施例の製造方法を説明するための
工程順に示した半導体チ、ブの断面図、第3図は従来の
半導体装置の一例を示す断面図である。 l・・・・・・P型シリコンM板、2・・・・・・フィ
ールド酸化膜、3・・・・・・ゲート酸化膜、4・・・
・・・多結晶シリコン膜、5・・・・・・硅化タングス
テン膜、6・・・・・・酸化シリコン膜、7・・・・・
・ホトレジスト膜、8,9・・・・・・N”1拡散層、
10・・・・・・酸化シリコン膜、11・・川・シリ:
t7L12・・・・・・チタン膜、13・・・・・・硅
化チタンffl、14・・・・・・PSGffl、15
・・団・アルミニウム膜、16.17・・・・・・N−
型拡散層、18・・・・・・多結晶シリコン膜、19・
・・・・・ホトレジスト膜、20・・・・・・モリブデ
ン膜、21・・・・・・硅化モリブデン膜。
FIGS. 1(a) to (h) and FIGS. 2(a) to (d) show semiconductor chips in the order of steps for explaining the manufacturing method of the first and second embodiments of the present invention. 3 is a cross-sectional view showing an example of a conventional semiconductor device. 1... P-type silicon M plate, 2... Field oxide film, 3... Gate oxide film, 4...
...Polycrystalline silicon film, 5...Tungsten silicide film, 6...Silicon oxide film, 7...
・Photoresist film, 8, 9...N"1 diffusion layer,
10...Silicon oxide film, 11...River silicon:
t7L12...Titanium film, 13...Titanium silicideffl, 14...PSGffl, 15
・・Group・Aluminum film, 16.17・・・・・・N-
Type diffusion layer, 18... Polycrystalline silicon film, 19.
... Photoresist film, 20 ... Molybdenum film, 21 ... Molybdenum silicide film.

Claims (1)

【特許請求の範囲】[Claims] 一導電型半導体基板の一主面に設けたフィールド酸化膜
により区画された素子形成領域と、前記素子形成領域の
表面に設けたゲート絶縁膜の上に設けたゲート電極と、
前記ゲート電極に整合して前記素子形成領域内に設けた
逆導電型のソース・ドレイン領域を有する半導体装置に
おいて、前記ゲート電極の側面に設けた絶縁性側壁部と
、前記側壁部に隣接して前記ソース・ドレイン領域の表
面に設けたシリコン膜と、前記シリコン膜の上面に設け
た高融点金属硅化物膜とを有することを特徴とする半導
体装置。
an element formation region partitioned by a field oxide film provided on one main surface of a semiconductor substrate of one conductivity type; a gate electrode provided on a gate insulating film provided on the surface of the element formation region;
In a semiconductor device having source/drain regions of opposite conductivity type provided in the element formation region in alignment with the gate electrode, an insulating side wall portion provided on a side surface of the gate electrode, and an insulating side wall portion adjacent to the side wall portion. A semiconductor device comprising: a silicon film provided on the surface of the source/drain region; and a high melting point metal silicide film provided on the upper surface of the silicon film.
JP33202389A 1989-12-20 1989-12-20 Semiconductor device Pending JPH03191574A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33202389A JPH03191574A (en) 1989-12-20 1989-12-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33202389A JPH03191574A (en) 1989-12-20 1989-12-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03191574A true JPH03191574A (en) 1991-08-21

Family

ID=18250277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33202389A Pending JPH03191574A (en) 1989-12-20 1989-12-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03191574A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01314709A (en) * 1988-06-09 1989-12-19 Katsuichiro Sato Swimming wear with waterproof pocket
JPH04342141A (en) * 1991-05-17 1992-11-27 Mitsubishi Electric Corp Manufacture of mos transistor
US5539229A (en) * 1994-12-28 1996-07-23 International Business Machines Corporation MOSFET with raised STI isolation self-aligned to the gate stack

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01314709A (en) * 1988-06-09 1989-12-19 Katsuichiro Sato Swimming wear with waterproof pocket
JPH04342141A (en) * 1991-05-17 1992-11-27 Mitsubishi Electric Corp Manufacture of mos transistor
US5539229A (en) * 1994-12-28 1996-07-23 International Business Machines Corporation MOSFET with raised STI isolation self-aligned to the gate stack
US6022781A (en) * 1994-12-28 2000-02-08 International Business Machines Corporation Method for fabricating a MOSFET with raised STI isolation self-aligned to the gate stack

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