JPH0316232A - Manufacture of charge coupled device - Google Patents

Abstract

PURPOSE:To enable control of N-type impurity concentration difference under a first layer and a second layer and prevention of dispersion by implanting divalent phosphorus ions from above the first layer after forming a low concentration of N-type region on a substrate and forming polycrystalline silicon gates of the first layer and the second layer in order. CONSTITUTION:A thermal oxide film 2 is formed on a P-type semiconductor silicon substrate 1, and then ions of phosphorus are implanted at the implantation quantity smaller than ever, and an N-type diffusion layer 3 is formed by heat treatment. Successively, the first layer polycrystalline silicon gate 4 is formed and the surface is oxidized, and then the second polycrystalline silicon gate 5 is formed, and without removing a photoresist pattern 6 used for selective etching, divalent phosphorus ions are introduced under the first layer polycrystalline silicon gate 4 by ion implantation method. Hereby, the N-type impurity concentration difference under the polycrystalline silicon gates of the first layer and the second layer can be controlled precisely, and dispersion in impurity concentration can be suppressed to the minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a charge coupled device having a two-layer gate structure made of polycrystalline silicon.

Conventional technology In order to operate a charge-coupled device with a two-layer gate structure, the first
A difference must be made between the substrate surface impurity concentrations under the layered polycrystalline silicon gate and under the second layered polycrystalline silicon gate. An example of a conventional method for this purpose will be explained using FIG. 2. FIG. 2 is a schematic diagram illustrating a part of the manufacturing process of a charge coupled device. First, a thermal oxide film 2 is formed on a P-type semiconductor silicon substrate 1, and then phosphorous is ion-implanted over the entire surface. The implanted phosphorus forms an N-type diffusion layer 3 by high-temperature heat treatment. Next, the first layer polycrystalline silicon gate 4
is formed, and boron ions are implanted using this first layer polycrystalline silicon gate 4 as a mask. By the next high heat treatment, boron diffuses into the N-type diffusion layer a, and the weak N-type diffusion layer 7
form. Thereafter, a second layer polycrystalline silicon gate 5 is formed. As a result, a low concentration N-type diffusion layer is formed under the second layer polycrystalline silicon gate 6 as well as under the first layer polycrystalline silicon gate 4.

Problems to be Solved by the Invention In the conventional method, after boron ion implantation, the thermal oxide film 8 on the N-type diffusion layer T is once removed and then thermally oxidized again to form the second gate oxide film 8. Therefore, boron redistribution occurs, making it difficult to obtain the desired boron concentration distribution.

Means for Solving the Problems According to the present invention, the most fundamental solution to the problem of boron redistribution due to thermal oxidation is not to use impurities that are likely to cause redistribution into the oxide film, such as boron. That is, it is necessary to abandon the method of creating a difference in impurity concentration by replacing the P-type impurity (boron) with the N-type region. In the present invention, first, a low concentration N-type region is formed, and after forming a polycrystalline polysilicon gate electrode, the second layer is penetrated through the first layer polysilicon gate from above the first layer polysilicon gate. By introducing valent phosphorus ions by ion implantation, the N-type impurity concentration under the first-layer polycrystalline silicon gate is made higher than the N-type impurity concentration under the second-layer polycrystalline silicon gate. In order to implant ions through a polycrystalline silicon layer, an ion implanter capable of extremely high acceleration is required, but by using divalent ions in the present invention, it can be easily performed with a general ion implanter. It can be put into practical use at the mass production level.

According to the structure described above, 9, 2 formed on a semiconductor substrate of one conductivity type.
Layered polycrystalline silicon gate structure (buried channel/&
- type) charge coupled device, after selectively etching the second layer polycrystalline silicon gate, divalent phosphorus ions are implanted under the first layer polycrystalline silicon gate without removing the etching photoresist mask pattern. By introducing this, it is possible to form a desired impurity concentration difference between the first layer polycrystalline silicon gate and the second layer polycrystalline silicon gate using an ion implantation process without using any extra steps. As such, an ideal potential barrier can be formed. The potential barrier created in this way can omit heat treatment such as re-formation of the oxide film, and also eliminates the need for a poron redoing process, making it possible to minimize variations in impurity concentration during manufacturing.

Embodiment An embodiment of the present invention will be described with reference to FIG. 1, which is a schematic diagram illustrating a part of the manufacturing process of a charge-coupled device.

In FIG. 1, 1 is a P-type semiconductor silicon substrate with a specific resistance of 20 g. After thermally oxidizing this substrate 1 to form a thermal oxide film 2 with a thickness of 6 onu, phosphorus ions are implanted at an acceleration energy of 100 kV. The defeated Rin is 11oO゜C
, an N-type diffusion layer 3 is formed by heat treatment in a nitrogen atmosphere. The concentration of the N-type diffusion layer 3 is such that the amount of phosphorus ions implanted is smaller than in the conventional method in order to correspond to the boron return region (region where a thin boron implantation is applied to the phosphorus implanted region) in the conventional method. Subsequently, a first layer polycrystalline silicon gate 4 is formed. The polycrystalline silicon thickness is 350 nu. After that, the surface of the first layer polycrystalline silicon gate 4 is oxidized, and then a second layer polycrystalline silicon gate 6 is formed according to the photoresist pattern 6. The thickness of the second layer polycrystalline silicon gate is soon m. In this state, divalent phosphorus ions are implanted at an acceleration energy of 180 keV. This is 360k when converted to monovalent phosphorus.
The energy corresponds to eV, and the phosphorus ions penetrate through the first layer polycrystalline silicon gate 4 and reach the channel portion. The phosphorus ions are deeply diffused by heat treatment in the subsequent step (maximum temperature is 1100° C.), forming an N-type diffusion region 9. The impurity concentration of the N-type diffusion region 9 is determined by the total amount of the two phosphorus ion implantations. In the above diffusion method, the structure is similar to that of the conventional method, that is, the bottom of the first layer polycrystalline silicon gate and the bottom of the second layer polycrystalline silicon gate are both N type, and the concentration of the former is higher than that of the latter. We were able to realize a structure with a large capacity.

Effects of the Invention By using the present invention, boron is not used to create a difference in H-type impurity concentration under the polycrystalline silicon gates of the b1 first layer and the second layer, so impurity regeneration into the oxide film is prevented. It has become possible to precisely control impurity concentration without causing variations in impurity concentration due to distribution.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of the manufacturing process of a charge-coupled device according to the present invention, and FIG. 2 is a schematic diagram of a conventional charge-coupled device manufacturing process. 1... P-type semiconductor silicon substrate, 2...
・Thermal oxide film, 3...N-type diffusion layer, 4...
・First layer polycrystalline silicon gate, 6... Second layer polycrystalline silicon gate, 6... Photoresist pattern, 7... Boron ion implantation/reverse diffusion N-type diffusion layer, 8...Reformed thermal oxide film layer, 9...N-type diffusion layer into which additional ions have been implanted.

Claims (1)

[Claims] In a charge-coupled device with a two-layer polycrystalline silicon gate structure formed on a semiconductor substrate of one conductivity type, after selective etching of the second-layer polycrystalline silicon gate, divalent phosphorus ions are generated without removing the etching photoresist mask pattern. is introduced under the first layer polycrystalline silicon gate by ion implantation using the photoresist pattern as a mask, thereby creating a charge potential barrier between the first layer polycrystalline silicon gate and the second layer polycrystalline silicon gate. 1. A method for manufacturing a charge-coupled device, comprising: forming a charge-coupled device.