JPH03147041A - Error correction system - Google Patents

Abstract

PURPOSE:To correct errors in more than two data bits, which include a fixed fault in one address words by previously holding position information of a fixed fault bit in a registration means in correspondence with respective addresses, correcting the fixed fault through the use of the information and detecting and correcting the intermittent fault of one bit. CONSTITUTION:A memory element string 1 outputs data corresponding to an address signal 100 inputted from an external part as a data signal 200. A registration means 3 outputs a fixed fault data bit signal 300 corresponding to the inputted address signal 100. The data signal 200 is inputted to an inversion/ correction means 4 with the fixed fault data bit signal 300, and is outputted as a data signal 201 after a fixed fault data bit position is inverted and corrected. The data signal 201 is inputted to an error detection/correction means 2 and the error except for the fixed fault data bit which is previously inverted and corrected, namely, the intermittent fault is detected or corrected. Then, it is outputted as a data signal 202.

Description

Detailed Description of the Invention Technical Field The present invention relates to an error correction system, and more particularly, to an error correction system, in which N (N is a natural number) bits with a fixed failure are read from a storage device, and one bit is an intermittent failure. The present invention relates to an error correction system for data containing intermittent faulty bits.

Prior Art Conventional error correction methods for data read from a storage device having a memory element matrix of M (M is the number of data bits) rows and XL (L is the number of address words) columns are as follows:
An error detection and correction means capable of detecting an error of at least two data bits and correcting an error of at least one data bit in an address word, such as an error correction code (ECC) such as a Hamming code.
An error correction method using the orrecLing Code) has been implemented.

In particular, it is possible to detect errors in two data bits in one address word, such as Hamming code, and to correct errors in one data bit (5EC-DISID: SlngIe
Error Correctlon-Double
The Error Dotectlon) code is relatively easy to use and is implemented as a common ECC. This is because the majority of data bit errors in storage devices are 1 data bit, so using the 5EC-DED code can be used to correct them, and as a result, the reliability of the storage device can be improved. be.

Furthermore, ECC that can correct errors of two or more data bits in one address word has been devised for the purpose of improving the reliability of storage devices, but it is relatively difficult to put it into practical use, and it is difficult to put it into practical use. Since the amount of hardware involved is quite large, it has little effect on improving the reliability of the entire storage device, and is therefore not generally implemented.

On the other hand, as the storage capacity of storage devices increases, the incidence of data bit errors in memory failures increases, and improvements in error correction technology are beginning to be required. In particular, in semiconductor memory devices, the incidence of intermittent 1-bit errors such as soft errors in memory elements is increasing with storage capacity, and the occurrence of errors of 2 bits or more when combined with the occurrence of fixed failures is increasing. rate is increasing.

However, such an FCC capable of correcting errors of 2 data bits or more has the drawback that it is difficult to put it into practical use as described above.

OBJECT OF THE INVENTION The object of the present invention is to solve the above-mentioned conventional SIE C-D I7
1) As easy as the error correction method using codes,
Another object of the present invention is to provide an error correction 1L system that can correct errors of 2 data bits or more including fixed faults in one address word.

Composition of the Invention The error correction system according to the present invention reads out N bits (N is a natural number) of fixed fault bits that are fixed faults and 1 intermittent fault bit of intermittent faults that are read from a storage device. An error correction system for data comprising: a holding means for holding correction information for all fixed failure bits in the data; and a correction system in the holding means when the data is read from the storage device. The present invention is characterized by comprising a first error correction means for correcting the data based on information, and a second error correction means for correcting a 1-bit intermittent failure bit in the data.

Example The present invention will be described in detail below using drawing F1.

FIG. 1 is a block diagram showing the configuration of an embodiment of an error correction system according to the present invention.

In the figure, a memory element matrix 1 transfers data corresponding to an address signal 100 manually inputted from the outside into a data signal 200.
This is a storage device that outputs as . The registration means 3 outputs a fixed fault data bit signal 300 corresponding to the manually entered address signal 100. This fixed failure data bit signal 300 indicates the position of the fixed failure bit of the data corresponding to the address signal 100. In other words, the fixed fault data bit signal 300 indicates the position of the fixed fault bit for all data in the memory element matrix 1.

The data signal 200 is input to the inversion correction means 4 together with the fixed fault data bit signal 300, and after the fixed fault data bit position indicated by the fixed fault data bit signal 300 is inverted and corrected, it is output as a data signal 201. The data signal 201 is input to the error detection and correction means 2, where errors other than fixed fault data bits that have already been inverted corrected, that is, intermittent faults, are detected or corrected and output as a data signal 202. In other words, after correcting the fixed fault, the intermittent fault is corrected.
A step-by-step operation takes place.

This will be further explained with reference to FIG. FIG. 2 is a conceptual diagram showing an example of the error correction process in the error correction system of this embodiment.

In the figure, (a) is a data signal 200 from memory element matrix 1 in FIG. 1, (b) is a fixed failure data bit signal 300 in FIG. 1, and (c) is a data signal 2 from memory element matrix 1 in FIG.
01 and (d) respectively show an example of the data signal 202 in FIG. Further, in the figure, correct bits are indicated by a 0 mark, error bits are indicated by an x mark, and it is assumed that the second bit is an intermittent fault and the sixth bit is a fixed fault.

First, when the data signal 200 shown in (a) is output from the memory element matrix ]-, it is input to the inversion correction means 4. Here, the error bit marked with an X in the sixth bit of the fixed fault data bit signal 300 shown in (b) is inverted to become the data signal 201 shown in (C).

This means that the fixed fault has been corrected.

Since the data signal 201 has a single data bit error only in the error pit marked with an X in the second bit, error detection and correction can be performed by the error detection means 2 using a 5EC-DED code or the like as in the conventional case.

Therefore, errors are detected and corrected by the error detection and correction means 2, resulting in a correct data signal, which is output as a data signal 202 in (d).

In other words, in this embodiment, the position information of the fixed fault bit is stored in advance in the registration means in correspondence with each address, the fixed fault is corrected using that information, and then the intermittent fault of one bit is detected and It is being corrected. Therefore, even if there are two or more bits of fixed faults, if position information for all of them is stored in advance in the registration means, it can be effectively corrected. Note that intermittent errors are corrected using the 5EC-DED code, etc., as in the past, so it is possible to correct up to a maximum of 1-bit error. In other words, it is possible to correct two or more bits, including fixed faults and intermittent faults.

In this embodiment, only the position information of the error pit is held in the registration means, but the position information and the correct value of the bit are held in advance, and the value is set in the bit position. It is clear that similar effects can be obtained.

According to the present invention, as described in detail, S E C-1)E
Errors of 2 data bits or more, including fixed faults in one address word, can be corrected with the same ease as the conventional error correction method for storage devices using D codes, making it possible to correct errors of 2 data bits or more, including fixed faults in one address word. E that can correct errors of two or more data bits in one address word in
Since it is possible to obtain the same level of data bit error countermeasure effect as CC, as a result, the reliability of the entire storage device can be improved beyond what could be expected with conventional storage device error correction methods. effective.

In particular, in semiconductor memory devices, the incidence of intermittent 1-bit errors such as soft errors in memory elements is increasing with storage capacity, and the occurrence of fixed failures is also increasing.
Since the incidence of errors of one data bit or more is increasing, applying the present invention will have a significant effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an error correction system according to an embodiment of the present invention, and FIG. 2 is a conceptual diagram showing an example of an error correction process. Explanation of symbols of main parts 1...Memory element matrix 2...Error detection and correction means 3...Registration means 4...Inversion correction means FIG. Figure 2

Claims (1)

[Claims] (1) N that has been read from the storage device and has a fixed failure
(N is a natural number) An error correction system for data including a fixed fault bit and a 1-bit intermittent fault bit that is an intermittent fault, and holds correction information for all fixed fault bits related to the data. holding means; first error correction means for correcting the data based on correction information in the holding means when the data is read from the storage device; and a first error correction means for correcting the data based on correction information in the holding means; An error correction system comprising: second error correction means for correcting errors.