JPH03142800A - Electrically erasable and writable programmable read only memory - Google Patents

Abstract

PURPOSE:To always preserve data in a normal EEPROM by detecting that a memory cell is destructed, modifying the address of the EEPROM according to a detected result and writing data to the normal memory cell of the EEPROM where the destruction does not occur. CONSTITUTION:When the selected memory cell is destroyed, '1' is raised in a bit which has the output of a syndrome generating circuit 11. Accordingly, the output of an OR circuit 12 is made '1' and it is detected that the memory cell is destroyed. At such a time, since an address decoder 2 decodes the output of the OR circuit 12 as a most significant bit A8 of the address, a memory band 2 is selected and the output of the address decoder 2 selects the prescribed EEPROM memory cell, which is determined by address information A0-A7 of the memory bank 2, and executes erasing and writing. Thus, the data can be always preserved in the normal EEPROM cell.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to electrically erasable/programmable programmable read-only memory (hereinafter referred to as "EEPROMJ"), and in particular to a programmable read-only memory (hereinafter referred to as "EEPROMJ") that has a built-in error correction code circuit. EEF
Related to ROM.

[Prior Art] Conventional EEFROMs have the problem of memory cells being destroyed and data being lost due to repeated writing and erasing.
EEFROMs with built-in error correction code (error correction code) circuits have been manufactured.

An example of an EEPROM with a built-in ECC circuit is a 12-bit memory cell with 8 bits of main data and 4 bits of redundant data added to each byte, and an ECC circuit, with 1 bit of the 12-bit memory cell being By restoring and reading correct 8-bit data even if the corresponding memory cell is destroyed, reliability of written data is improved.

A basic configuration block diagram of a conventional EEPROM is shown in FIG. When the EEPROM write operation is executed, address information AO to A7 is manually input to the address decoder 32,
Predetermined 8 bits of the EEPROM memory cell array 36 are selected, and the write data is transferred to the WR data latch 3.
It is latched to 7. In addition, the write-only timer 33 is started to automatically generate an erase cycle and a write cycle (for example, 5 nsec each), and first the EEPROM is erased, and then the contents of the 'vVR data latch 37 are written. When the write-only timer 33 detects that the write cycle has ended, a write end signal is generated.

When performing a read operation from the EEPROM, a predetermined EEFROM is selected based on the address information, and 8-bit main data 40 and 4-bit redundant data 39 are input to the syndrome generation circuit 41 via the selector 38. The syndrome generation circuit 41 uses the main data 40 that is manually generated.
A syndrome is generated based on the redundant data 39. At this time, if all the selected cells are normal and the main data 40 and redundant data 39 are not damaged at all, the outputs of the syndrome generation circuit 41 will all be 0''. It is decoded by a circuit 42, and an error vector 43 is generated which indicates which bits of the main data 40 and the redundant data 39 have an error.If the main data 40 has no error, the main data 40 is passed through an error correction circuit 44. It is latched by the RD data latch 45 and output to the data bus 46. If there is an error in the main data 40, the correct data whose error has been corrected by the error correction circuit 44 is outputted to the data bus 46 via the RD data latch 45. is output to.

[Problem to be solved by the invention] The conventional EEFROM with a built-in ECC circuit described above has
Number of bits that can be corrected by the C circuit (for example, in the case of a memory cell with 4 bits of redundant data added to 8 bits of main data, the number of bits that can be corrected by the ECC circuit is 1 bit)
If any of the above cells fail, correct main data cannot be restored. In addition, although correct data can be obtained by the ECC circuit, it is not possible to know that a part of the memory cell is destroyed, so it is not possible to know that the EEPROM has been destroyed until correct data can no longer be obtained. The disadvantage is that it can be seen.

[Differences between the invention and the prior art] In the conventional EEFROM described above, when a memory cell is destroyed, correct data is restored and read by an ECC circuit, whereas the present invention restores and reads correct data when a memory cell is destroyed. Detects the EEPROM address and modifies the EEPROM address based on the result to create a normal EEPROM that has not been destroyed.
The difference is that writing is performed on memory cells.

- [Means for Solving the Problems] In addition to the conventional EEPROM circuit, the EEFROM of the present invention includes a means for detecting destruction of an EPROM memory cell to be written, and an EEPROM based on the result.
It has means for modifying the address of the ROM and writing to a normal EEPROM memory cell in which no destruction has occurred.

[Example code] Next, the present invention will be explained using the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The block diagram in Figure 1 shows an address decoder 2 that decodes address information AO to A7, and sufficient time required for erasing and writing (for example, 5m5ec for erasing and 5m5ec for writing).
a write-only timer 3 for securing m5ec),
RD/WR control circuit 4 that controls whether to write or read from EEPROM memory cells
and EEPROM according to the state of the RD/WR control circuit 4.
It consists of a high voltage generation circuit 5 that generates a high voltage to be supplied to the memory cell array 6, and a memory bank 1 and a memory bank 2, with each bank having 256 12-bit memories each consisting of 8-bit main data and 4-bit redundant data. EE
A PROM memory cell array 6, a WR data latch 7 that latches write data, and a setter 8 that divides the 12-bit data read from the EEPROM memory cell array 6 into 8-bit main data and 4-bit redundant data 9. and a syndrome generation circuit 11 that generates a syndrome based on the manually generated main data 10 and redundant data 9.
and an OR circuit 12 that takes the OR of the outputs of the syndrome generation circuit 11.

Next, the write operation of the EEPR'OM of the present invention will be explained.

When the CPU executes a write operation to the EEPROM area, it latches the write data into the 'vVR data latch 7 and checks whether the EEPROM memory cell to be written has been destroyed. First, address information AO-A7 is generated and decoded by address decoder 2, predetermined 12 bits of EEPROM memory cell array 6 are selected, and the contents are manually input to selector 8. The 12-bit data is divided by the selector 8 into 8-bit main data 10 and 4-bit redundant data 9, and is input to the syndrome generation circuit 11. The syndrome generation circuit 11 generates a syndrome based on these data.

For example, if all the selected memory cells are normal, all the outputs of the syndrome generation circuit 11 are II.
OII, and the output of the OR circuit 12 also becomes "'0", so it is determined that the EEPRON memory cell to be written is normal, and the memory bank 1 address information 1E3 is
Erasing and writing are performed to a predetermined EEPROM selected by AO to A7. In addition, if the selected memory cell is destroyed, a certain bit of the output of the syndrome generating circuit 11 is set to "1", so the output of the OR circuit 12 becomes "1".
1"', and it is detected that the memory cell is destroyed. At this time, the address decoder 2 outputs the OR circuit 1.
Since the output of address decoder 2 is decoded as the most significant address bit (A8), memory bank 2 is selected and the output of address decoder 2 is address information AO-A? of memory bank 2.
A predetermined EEPROM memory cell determined by is selected and erased/written.

FIG. 2 is a block diagram of a second embodiment of the present invention. In this figure, the same means as in FIG. 1 are given the same reference numerals.

In this embodiment, in addition to the components 1 to 14 of the first embodiment, the syndrome generation circuit 11
A switching circuit 15 that switches the output light of the output, an error vector generation circuit 16 that generates an error vector, an error correction circuit 17 that corrects errors in the main data, and a mode that switches the information source of the most significant address A8. It has a register 18, an inverter 19 that inverts the output of the mode register, and transfer gates 20 and 21 that are turned on when the outputs of the mode register 18 and inverter 19 are at high level, respectively.

In this embodiment, the mode register 18 makes it possible to switch between using 8 for address information or using the output of the OR circuit 12 in the most significant bit of the address.

For example, when the mode register 18 is set to '0', the transfer gate 21 is turned on and 8 is selected for the address information as the most significant bit of the address.
This is a conventional EEFROM with a built-in FCC circuit selected by address information AO to 8. In addition, the mode register 18
When is set to "1", the transfer gate 20 is turned on, so the output of the OR circuit 12 is selected as the most significant bit of the address, and the destruction of the memory cell is detected as in the first embodiment. Based on the results, writing is performed to a normal EEPROM memory cell in which no destruction has occurred.

[Effects of the Invention] As explained above, the present invention detects that destruction has occurred in an EEPROM memory cell, and selects an EEPROM memory cell in which no destruction has occurred by modifying, for example, the most significant bit of the address based on the detection result. By doing so, it is possible to always store data in a normal EEPROM memory cell, and the reliability of written data can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an EEFROM according to a first embodiment of the present invention, and FIG. 2 is a block diagram of an EEFROM according to a second embodiment of the present invention.
FIG. 3 is a block diagram of a conventional EEPROM. 2.32...address decoder, 3,33...
-Write-only timer, 4.34◆...RD/WR control circuit, 5.35...High voltage generation circuit, 6.36...EEPROM memory cell array, 7.
37...WR data latch, 8.38...Selector, 9.39◆...4-bit redundant data, 10.40◆.
・8-bit main data, 11.41...Syndrome generation circuit, 12...
...OR circuit, 13.45...RD data latch, 14.46...Data bus, 15...Switching circuit, 16.42...Error vector generation circuit, 17.44...
...Error correction circuit, 18...Mode register, 19...Inverter, 20.21...Transfer gate, 43...
・Error vector, AO~A8・ ・Address information.

Claims (1)

[Claims] In electrically erasable/writable programmable read-only memory with a built-in error correction code circuit, there is a means for detecting that a memory cell has been destroyed, and an address is modified based on the result to determine whether the memory cell is normal and not destroyed. 1. An electrically erasable and writable programmable read-only memory, characterized in that it is equipped with a means for selecting and writing memory cells.