JPH0311792A - Formation of solder bump - Google Patents
Formation of solder bumpInfo
- Publication number
- JPH0311792A JPH0311792A JP14744389A JP14744389A JPH0311792A JP H0311792 A JPH0311792 A JP H0311792A JP 14744389 A JP14744389 A JP 14744389A JP 14744389 A JP14744389 A JP 14744389A JP H0311792 A JPH0311792 A JP H0311792A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- hole
- ball
- solder bump
- flux
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 88
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 230000004907 flux Effects 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000002844 melting Methods 0.000 claims abstract description 5
- 230000008018 melting Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000004020 conductor Substances 0.000 abstract description 11
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052721 tungsten Inorganic materials 0.000 abstract description 11
- 239000010937 tungsten Substances 0.000 abstract description 11
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 6
- 229910001220 stainless steel Inorganic materials 0.000 abstract description 2
- 239000010935 stainless steel Substances 0.000 abstract description 2
- 239000007787 solid Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（概要）
はんだバンプの形成方法、特にバイアホールの真上には
んだバンプを形成させるための方法に関し、
はんだバンプ内に空洞ができないようにすることを目的
とし、
基板上のはんだバンプ形成部に形成した導体パターンに
はんだフラックスを塗布し、その上にはんだボールを搭
載し、それらを減圧された槽内で該はんだボールの溶融
温度に加熱することを特徴とし構成する。[Detailed Description of the Invention] (Summary) This invention relates to a method for forming solder bumps, particularly a method for forming solder bumps directly above via holes, with the purpose of preventing cavities from forming within the solder bumps, and for forming solder bumps on a substrate. The method is characterized in that solder flux is applied to the conductor pattern formed on the solder bump forming portion, a solder ball is mounted on the solder flux, and the solder balls are heated to the melting temperature of the solder ball in a vacuum tank.
〔産業上の利用分野］
本発明ははんだバンプの形成方法、特にバイアホールの
真上の導体パターンにはんだバンプを形成せしめるのに
有効な新規方法に関する。[Industrial Application Field] The present invention relates to a method for forming solder bumps, and more particularly to a novel method effective for forming solder bumps on a conductive pattern directly above a via hole.
はんだバンプの形成には、はんだボールが一般に広く使
用されている。その従来方法は、絶縁基板のはんだバン
プ形成部に導体パターンを形成し、その上にはんだフラ
ックスを塗布し、その上に搭載したはんだボールを大気
中で加熱溶解する方法であり、使用されるはんだの量は
はんだボールの大きさによって決まるため、均一なはん
だバンプが形成される。Solder balls are generally widely used to form solder bumps. The conventional method is to form a conductive pattern on the solder bump forming part of an insulating substrate, apply solder flux on it, and heat and melt the solder balls mounted on it in the atmosphere. The amount of solder is determined by the size of the solder ball, so a uniform solder bump is formed.
第２図は従来方法でバイアホールの真上に形成されたは
んだバンプの断面図（イ）と、バイアホールの側方に形
成したはんだハンプの断面図（［１）である。FIG. 2 is a cross-sectional view (A) of a solder bump formed directly above a via hole by a conventional method, and a cross-sectional view ([1)] of a solder hump formed on the side of the via hole.
第２図（イ）において、セラミック基板りの透孔２にタ
ングステン３を充填したバイアホールの真上に導体パタ
ーン（ランド）４を形成せしめると、タングステン３に
空洞５が形成されているとき、導体パターン４には空洞
５に連通ずる透孔６が形成される。In FIG. 2(a), when a conductive pattern (land) 4 is formed directly above the via hole 2 filled with tungsten 3 in the ceramic substrate, when a cavity 5 is formed in the tungsten 3, A through hole 6 communicating with the cavity 5 is formed in the conductor pattern 4 .
かかる導体パターン４の上にはんだフラ・ンクスを塗布
し、その上にはんだボールを搭載して形成したはんだバ
ンプ１１は、空洞５内の空気および空洞５内に侵入した
はんだフラ・ンクスがはんだボールの加熱溶解時に膨張
し、はんだバンプ１１内に空洞１２を形成させるように
なる。このような空洞１２は、はんだバンプ１１に所望
の電子部品等を接続させたとき、電気的および機械的接
続不良の要因となる。Solder bumps 11 are formed by applying solder flux on the conductor pattern 4 and mounting solder balls thereon.The solder bumps 11 are formed by applying solder flux on the conductor pattern 4 and mounting solder balls thereon. When heated and melted, the solder bump expands and forms a cavity 12 within the solder bump 11. Such a cavity 12 becomes a cause of electrical and mechanical connection failure when a desired electronic component or the like is connected to the solder bump 11.
第２図（ロ）において、空洞１２が形成されないように
した従来のはんだバンプ１３は、セラミック基板１の透
孔２にタングステン３を充填したバイアホールと連結導
体パターン１５を介して接続し、バイアホールより側方
に形成した導体パターン（ランド）１４に形成してなる
。かかるはんだバンプ１３は、タングステン３内の空洞
５に影響されず、従って中実（空洞のない）となる。In FIG. 2(B), a conventional solder bump 13 in which no cavity 12 is formed is connected to a via hole filled with tungsten 3 in a through hole 2 of a ceramic substrate 1 via a connecting conductor pattern 15. It is formed in a conductive pattern (land) 14 formed laterally from the hole. Such solder bumps 13 are not affected by the cavities 5 in the tungsten 3 and are therefore solid (without cavities).
〔発明が解決しようとする課題］
以上説明したように、はんだボールを使用した従来のは
んだバンプは、バイアホールの真上に形成させるとはん
だバンプ内に空洞ができ易いという欠点があり、このよ
うな空洞をなくすには、バイアホールより外れた位置に
はんだバンプが形成されるため、回路基板の回路形成面
積および部品搭載面積が狭められるという問題点があっ
た。[Problems to be Solved by the Invention] As explained above, conventional solder bumps using solder balls have the disadvantage that cavities tend to form inside the solder bumps when they are formed directly above a via hole. In order to eliminate such cavities, solder bumps must be formed outside the via holes, which poses a problem in that the circuit formation area and component mounting area of the circuit board are narrowed.
本発明の目的は、バイアホールの真上にはんだバンプを
形成できるようにすることであり、回路基板の活用面積
を広げることである。An object of the present invention is to enable the formation of solder bumps directly above via holes, thereby increasing the usable area of a circuit board.
［課題を解決するための手段］
上記目的は第１図に示す本発明の実施例によれば、セラ
ミック基板ｌのはんだバンプ形成部に形成した導体パタ
ーン４にはんだフランクスフを塗布し、その上にはんだ
ボール９を搭載し、それらを減圧された槽内ではんだボ
ール９の溶融温度に加熱することを特徴としたはんだハ
ンプ１０の形成方法である。[Means for Solving the Problem] According to the embodiment of the present invention shown in FIG. This method of forming a solder hump 10 is characterized in that solder balls 9 are mounted and heated to the melting temperature of the solder balls 9 in a vacuum tank.
上記手段によれば、減圧槽内ではんだボールを加熱溶融
しはんだバンプが形成されるため、該はんだバンプがバ
イアホールの真上に位置し該バイアホールに空洞を有す
るも、空洞内の空気および空洞内に侵入したはんだフラ
ックスは、溶融状態のはんだバンプから抜は出すことが
可能となり、バイアホールの真上に中実のはんだバンプ
が形成されると共に、使用するはんだフラックスは従来
方法よりも少量でよいため後工程の洗浄が容易になる。According to the above means, since the solder bump is formed by heating and melting the solder ball in the reduced pressure tank, even though the solder bump is located directly above the via hole and has a cavity in the via hole, the air in the cavity and the solder bump are formed. The solder flux that has entered the cavity can be extracted from the molten solder bump, forming a solid solder bump directly above the via hole, and using a smaller amount of solder flux than the conventional method. This makes cleaning in the post-process easier.
以下に、図面を用いて本発明方法の実施例を説明する。 Examples of the method of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例によるはんだバンプの形成方
法の説明図である。FIG. 1 is an explanatory diagram of a method of forming a solder bump according to an embodiment of the present invention.
第１図（イ）において、１はアルミナ基板、３はアルミ
ナ基板１の透孔２に充填させたタングステンである。透
孔２にタングステン３を充填でなるバイアホールの上に
形成した導体パターン（ランド）４は、Ｃｒ／Ｃｕ／Ｎ
ｉ／Ａｕの多層構成であり、スパッタリング法および電
気めっき等にて被着したＣｒ／Ｃｕ／Ｎｉ／Ａｕの厚さ
は、例えばＣｒ；０．１ ｕ１１１＋ Ｃｕ； ５ μ
ｍ＋ Ｎｉ： ２ ｐ ｍｌ Ａｕ； １ ｕｍである
。そして、タングステン３に空洞５が形成されたとき、
導体パターン４には空洞５に連通する透孔６が形成され
る。In FIG. 1(a), 1 is an alumina substrate, and 3 is tungsten filled in the through hole 2 of the alumina substrate 1. In FIG. The conductor pattern (land) 4 formed on the via hole made by filling the through hole 2 with tungsten 3 is made of Cr/Cu/N.
It has a multilayer structure of i/Au, and the thickness of Cr/Cu/Ni/Au deposited by sputtering method, electroplating, etc. is, for example, Cr; 0.1 u111+ Cu; 5 μ
m+Ni: 2 pml Au; 1 um. Then, when the cavity 5 is formed in the tungsten 3,
A through hole 6 communicating with the cavity 5 is formed in the conductor pattern 4 .
かかるアルミナ基板１は、半生状態のグリーンシートに
透孔２をあけ、透孔２にタングステンペーストを充填し
、しかるのちグリーンシートとタングステンペーストを
同時に焼成し製造される。Such an alumina substrate 1 is manufactured by punching through holes 2 in a semi-baked green sheet, filling the through holes 2 with tungsten paste, and then firing the green sheet and the tungsten paste at the same time.
次いで第１図（ロ）に示す如く、アルミナ基板１の全上
面にはんだフランクスフを塗布するが、使用するはんだ
フランクスフは、なるべく空洞５や透孔６に侵入しない
ようにするためおよび、本発明方法は減圧槽内で加熱す
るのではんだフラックスは従来量の１７４量程度で済む
ため、低粘度のものを薄く塗布することが望ましい。Next, as shown in FIG. 1(B), solder franking cloth is applied to the entire upper surface of the alumina substrate 1, but the solder franking cloth used is to be used in order to prevent it from entering the cavity 5 and through hole 6 as much as possible, and to Since the method of the invention heats the solder flux in a reduced pressure tank, the amount of solder flux required is about 174 compared to the conventional amount, so it is desirable to apply a thin layer of low viscosity solder flux.
そこで第１図（ハ）に示す如く、はんだ濡れ性のない材
料（例えばステンレス）またははんだ濡れ防止処理の施
されたマスク８を利用し、導体パターン４の上にはんだ
ボール９を搭載する。Therefore, as shown in FIG. 1(c), a solder ball 9 is mounted on the conductor pattern 4 using a mask 8 made of a material that does not have solder wettability (for example, stainless steel) or treated to prevent solder wettability.
しかるのち、マスク８と共にはんだボール９の搭載され
たアルミナ基板１を、例えば１０−３気圧に減圧された
真空槽内でホットプレートを使用する等により、はんだ
フラックス７のガス抜きのため約１４０°Ｃに加熱した
のち、はんだボール９が溶融する温度例えば２００°Ｃ
に加熱すると、空洞５および透孔６内の空気は該ガス抜
き加熱およびはんだ溶融加熱によって抜けるようになり
、かつ、冷却された溶融はんだボール９の一部が透孔６
を埋めるようになる。Thereafter, the alumina substrate 1 on which the solder balls 9 are mounted together with the mask 8 is heated at an angle of about 140° to degas the solder flux 7 by using a hot plate in a vacuum chamber with a reduced pressure of, for example, 10 −3 atmospheres. The temperature at which the solder ball 9 melts after being heated to 200°C, for example
When heated to a temperature of
will begin to fill in.
そのため、第１図（ニ）に示す如く、バイアホールの真
上に形成されたはんだバンプ１０は、空洞のない中実性
が確保されるようになる。Therefore, as shown in FIG. 1(d), the solder bump 10 formed directly above the via hole is ensured to be solid without any cavity.
以上説明したように本発明方法によれば、減圧槽内では
んだボールを加熱溶融しはんだバンプを形成せしめるた
め、該はんだバンプは空洞を有するバイアホールの真上
に位置せしめるも中実となり、基板表面に形成せしめる
回路や搭載部品の密度が高められると共に、はんだバン
プを利用した電気的接続の信頼性が向上し、さらにはん
だフラックスは従来より少量で済むため後工程の洗浄が
容易になるという効果が顕著である。As explained above, according to the method of the present invention, the solder balls are heated and melted in a vacuum tank to form solder bumps, so that the solder bumps become solid even though they are positioned directly above the via holes having cavities, and the solder balls become solid on the substrate. The density of circuits and mounted components formed on the surface is increased, the reliability of electrical connections using solder bumps is improved, and since less solder flux is required than before, post-process cleaning becomes easier. is remarkable.
第１図は本発明の一実施例によるはんだバンプの説明図
、
第２図は従来方法によるはんだハンプの説明図、である
。
図中において、
ｌはセラミック基板、
４はバンプ形成用導体パターン、
７ははんだフラックス、
９ははんだボール、
１０ははんだバンプ、
を示す。
４ｃｔ明の一実侑偵１１Ｚ書う１ゴんＴビバ７ブｎ説明
記１１ 図
５０１−FIG. 1 is an explanatory diagram of a solder bump according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a solder hump according to a conventional method. In the figure, 1 is a ceramic substrate, 4 is a bump-forming conductor pattern, 7 is solder flux, 9 is a solder ball, and 10 is a solder bump. 4ct Akira no Kazumi Yusei 11Z writing 1 Gon T Viva 7 Bu n Explanation 11 Figure 501-
Claims (1)
ターン（４）にはんだフラックス（７）を塗布し、その
上にはんだボール（９）を搭載し、それらを減圧された
槽内で該はんだボール（９）の溶融温度に加熱すること
を特徴としたはんだバンプの形成方法。Solder flux (7) is applied to the conductive pattern (4) formed on the solder bump forming area on the board (1), and solder balls (9) are mounted on it, and the solder flux (7) is applied to the conductive pattern (4) formed on the solder bump forming area on the substrate (1). A method for forming a solder bump, characterized by heating to the melting temperature of a ball (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14744389A JPH0311792A (en) | 1989-06-09 | 1989-06-09 | Formation of solder bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14744389A JPH0311792A (en) | 1989-06-09 | 1989-06-09 | Formation of solder bump |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0311792A true JPH0311792A (en) | 1991-01-21 |
Family
ID=15430458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14744389A Pending JPH0311792A (en) | 1989-06-09 | 1989-06-09 | Formation of solder bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0311792A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291778B1 (en) | 1995-06-06 | 2001-09-18 | Ibiden, Co., Ltd. | Printed circuit boards |
| US6525275B1 (en) | 1996-08-05 | 2003-02-25 | Ibiden Co., Ltd. | Multilayer printed circuit boards |
| US6831234B1 (en) | 1996-06-19 | 2004-12-14 | Ibiden Co., Ltd. | Multilayer printed circuit board |
| JP2016139648A (en) * | 2015-01-26 | 2016-08-04 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
-
1989
- 1989-06-09 JP JP14744389A patent/JPH0311792A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291778B1 (en) | 1995-06-06 | 2001-09-18 | Ibiden, Co., Ltd. | Printed circuit boards |
| US6303880B1 (en) | 1995-06-06 | 2001-10-16 | Ibiden Co., Ltd. | Printed circuit boards |
| US6831234B1 (en) | 1996-06-19 | 2004-12-14 | Ibiden Co., Ltd. | Multilayer printed circuit board |
| US6525275B1 (en) | 1996-08-05 | 2003-02-25 | Ibiden Co., Ltd. | Multilayer printed circuit boards |
| JP2016139648A (en) * | 2015-01-26 | 2016-08-04 | 株式会社東芝 | Semiconductor device and manufacturing method of the same |
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