JPH03110648A - Data processing system - Google Patents

Abstract

PURPOSE:To reduce the overhead caused by the frequent occurrence of conversion due to indexing of a table on a main storage by providing each entry of an address conversion table (TLB) with a field where private space control information is stored. CONSTITUTION:Private space control information is held in a P register 6, and each entry of a TLB 3 is provided with a private space control field P. When the indexed TLB entry is a common segment conversion pair, the corre sponding P field is certainly '0', and the value of the P register and the P field do not coincide with each other to cause a TLB miss. Then, address conver sion based on the table on the main storage is performed and an obtained conversion pair is written in the entry of the TLB 3 to satisfy a TLB hit condi tion. Thus, conversion based on indexing of the table on the main storage is not always performed though the access to a private space is continuous, and unnecessary overhead on the processing performance is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multiple virtual address space data processing system having address translation buffers (TLBs).

[Background Art] Conventionally, in a processing system that uses virtual addressing in multiple virtual memory spaces, address processing is performed in order to perform high-speed address conversion to obtain a real address from a virtual address space and a logical address. Translation buffer (TL
I3) is well known.

Address translation is performed using segment tables and page tables, which are translation tables defined by the system for each virtual address space. Each entry in the TLB includes a field that stores the segment table starting point (STo) defined in the segment table descriptor (STD), which is the starting point in the main memory of the segment table, and A field is provided to store the defined common segment bit (C). For conversion by the TLB, ST
The contents of the O and C fields determine the success of the translation to a real address (TLB hit). At this time, when accessing the address space, the contents of the STO field are compared with the STO in the STD used to convert the virtual address of the accessed space to a real address, and if they match, it is determined that the conversion was successful. However, if the content of the C field is '1', that is, if the segment table is a common segment table for all address spaces, the content of the STO field in the TLB entry and the STO in the STD are The conversion is determined to be successful without comparison.

In addition, the fields of the TLB entry include, for example,
For virtual computer systems, etc., the Japanese Patent Publication No. 57-23347
As shown in this issue, a VM-ID field is provided as identification information of a guest virtual machine (guest VM) to improve performance.

In IBM's ESA/370 architecture, when performing translation using the TLB to access an address space, private control information (private control bit) indicates that the address space is a private space, even if the translation pair in the TLB entry indexed for accessing that address space is a common segment translation pair. Does not allow address translation through the use of translation pairs.

In a processing system that implements such an architecture, when the conversion pair based on the TLB index for private space access is a common segment conversion pair,
It is necessary to always perform conversion using the indexes of the segment table and page table on the main memory without using the conversion pair.

[Problems to be Solved by the Invention] The above-mentioned conventional technology has the problem that when accessing a private space,
If the conversion pair based on the TLB, especially the TLB index consisting of multiple rows, is a common segment conversion pair, the conversion pair is not used as described above, and the conversion based on the segment table and page table index in main memory is performed. Need to do it all the time. Therefore, when private space is accessed consecutively within the same page, conversions due to segment table and page table indexes on main memory occur frequently, resulting in unnecessary overhead in terms of processing performance.6 The purpose of the present invention is to An object of the present invention is to provide a data processing system that can reduce overhead caused by frequent conversions due to indexing of segment tables and page tables on main memory.

Another object of the present invention is to provide a data processing system having means for registering address translation pairs for private space access in a TLB.

[Means for Solving the Problems] In order to achieve the above object, a data processing system according to the present invention provides a virtual address space formula having an address translation buffer that holds address translation pairs and is indexed by a portion of a logical address. In the data processing system, each entry of the address translation buffer is provided with a field for storing private space control information defined in a segment table descriptor used for translation from a virtual address to a real address.

According to another aspect, a data processing apparatus according to the invention is provided in a virtual address space based data processing system having an address translation buffer that holds address translation pairs and is indexed by a portion of a logical address.

Each entry of the address translation buffer is provided with a field for storing private space control information defined in a segment table descriptor used for translation from a virtual address to a real address, and when accessing the address space, The private space control information defined in the segment table descriptor used for converting virtual addresses to real addresses in the address space is compared with the contents of the private space control information field of the address translation buffer, and if they match, the address is determined. The present invention is characterized in that it includes means for determining whether or not the address translation is successful, which is a condition for success in translation.

According to yet another aspect, a data processing system according to the present invention maintains an address translation pair and a common segment bit, at least one segment bit indexed by a portion of a logical address.
In a virtual address space type data processing system having an address translation buffer composed of rows, each entry of the address translation buffer has a private space control defined in a segment table descriptor used for translation from a virtual address to a real address. In addition to providing a field for storing bits, a private space control bit defined in a segment table descriptor used to convert a virtual address in the address space to a real address when accessing an address space and a private field in the address translation buffer are provided. The private space control bit field and the common segment in the same entry of the address translation buffer are provided with an address translation success determination means for comparing the values of the space control bit field and making a match between the two a condition for successful address translation. The logic value "1" is not registered in the bit field at the same time.

In this data processing system, preferably, when a private space access is performed in which a private space control bit defined in a segment table descriptor used for virtual address to real address translation is a logical value "1", the address translation If there is an entry whose common segment bit has a logical value of '1' among the entries indexed from the buffer, register the private space access conversion pair for that entry along with the private space control bit's logical value '1'. Alternatively, for a multi-row address translation buffer, a private space whose private space control bit defined in a segment table descriptor used for translation from a virtual address to a real address has a logical value of '1'. When accessing, if there is an entry whose common segment bit is logical '1' among the plurality of entries indexed from the address translation buffer, invalidating means invalidates all entries in the column to which the entry belongs; , the conversion pair of the private space access for one entry in the column is set to the logical value '1' of the private space control bit.
What is the registration method to register at the same time?

[Operation] When the address translation buffer (TLI3) is referenced for accessing the virtual address space, the private space control bits defined in the STD used for translation from virtual addresses to real addresses in the address space and the indexed The contents of the private space control bit field in the TLB entry are compared, and a match between the two is a condition for successful address translation.

On the other hand, address translation such that both the private space control bit field and the common segment bit field have a logical value of 11' is not allowed.

Therefore, when the private space is accessed, if the common segment bit field of the indexed TLB entry has a logical value of '1', the private space side control bit and the indexed TLB entry are does not match the value of the private space control bit field of
Address translation is performed that refers to the segment table and page table on the main memory.

Therefore, the address translation pair obtained by this address translation is registered in the TLB together with the logical value 11' of the private space control bit. After registration, address translation of the private space can be performed using this translation pair in the TLB.

In order to register a conversion pair in the private space, detect that the indexed conversion pair is a common segment conversion pair, invalidate that entry or all indexed entries including that entry, and register the corresponding Register a private space address translation pair in one of the entries.

As mentioned above, when accessing private space.

If the indexed TLB entry is a common segment translation pair, address translation is performed using the segment and page table on the main memory as a translation failure, and the resulting translation pair is registered together with the private space control bit.

Since then, even when accesses to the private space are consecutive within the same page, the address conversion by TLB is successful, avoiding frequent address conversions due to table references in main memory, and improving the processing performance of data processing systems. can be achieved.

[Example code] An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 illustrates the relevant portions of the present invention of a multiple virtual address space data processing system. The system part in FIG. 1 includes an instruction execution unit 1 that executes individual instructions;
Register groups 5 to 9 each having a predetermined value set by the instruction execution unit 1, TLB 3, and the register group 5.
~9 and the write control unit 2 that controls data writing in the TLB 3 according to information from an address conversion unit (not shown), and a write control unit 2 that controls data writing in the TLB 3 according to information from the address conversion unit (not shown), and a write control unit 2 that controls data writing in the TLB 3 in accordance with information from the address conversion unit (not shown), and
The TLB hit determination section 4 determines LB hits.

Register 5 is a VM mode register (G register) in the virtual machine system, and is set to 1' in guest VM mode. Registers 6 and 7 are registers that hold part of the contents of the segment table descriptor (STD). That is, register 6 is a private space control register (P register) that holds private space control information, and is set to 1' when the virtual address space to be accessed is a private space. Register 7 is a segment table origin register (STO register) that holds the segment table base point (STO) in the STD. In addition, register 8 is
Real mode register (R register) that indicates whether TLB indexing is performed using virtual addresses or real addresses.
, and register 9 is an address register that holds an effective address. Address register 9 is.

For example, it consists of 31 bits. The upper 1st to 19th bits constitute a page address and are bits subjected to address conversion, and the 20th to 31st bits are bits common to the real address.

When an access request to the address space is generated, the instruction execution unit 1 sets predetermined data in the G register 5, the P register 6, the STO register 7, the R register 8, and the address register 9, respectively. Thereafter, a reference request is issued to TLB3.

TLB3 employs a set associative method. That is, it has one or more entries selected by the column address via the column address decoder 10, each entry is called a row, and this row is the target of the index or RB. In the present embodiment shown in FIG. 1, the TLB configuration has 11 colors, 512 degrees, and 1 row, that is, 512 entries, but other configurations, such as a plurality of rows, can be easily inferred.

Each entry in TLB3 includes a valid field (V), a guest field (G), a private space control field (P), a common segment 1 field (C), and a segment origin field (STO).

It consists of a virtual address field (VA), a real address mode field (R), and an absolute address field (PA). The number of bits in each field is shown in parentheses.

■The field 1 indicates whether this entry is valid or invalid.
The C field, which is a bit field and indicates 1' when valid and '0' when invalid, is an address translation field that indicates whether the entry corresponds to a host or guest VM in the virtual machine system. It is information. This field is 11' for guest VM and 1 for host.
It becomes 0'. The P field is a field that indicates whether the entry defines a private space translation pair, and when it is '1', it indicates that the entry is a private space address translation pair, and 0' When , it indicates that it is not a private space.The R field is a 1-bit field that indicates whether the address to be translated of the entry is a real address or a virtual address.When it is 0', it is a virtual address 1' indicates a real address. The C field indicates that the entry is an address translation pair using a common segment when this field is 1'.

When the common segment bit in the segment table used during address conversion is 11', this field becomes 1'. The STO field is in the segment descriptor at the time of address translation of the entry.

Represents the segment table starting address. The VA field is the bits other than the column address in the page frame address for TLB access, and in FIG. 1, it is a 10-bit field that stores bits 1 to 10. The PA field is the page frame address of the real address, 19 pits! store ~.

The TLB hit determination section 4 includes comparison circuits 11 to 15, OR gates 16 and 17, an AND gate 18, and an inverter 19. Comparison circuit 11 compares the C field of TLB 3 with the contents of G register 5, and when the value is -4, it becomes 1'.
Output. Comparison circuit 12 compares the P field of -TLB3 and the contents of P register 6, and when they match, it outputs 1'.
Output. Furthermore, the comparison circuit 13 compares the STO, the comparison circuit 14 compares the VA field and the page frame address other than the column address of the access address register 9, and the comparison circuit 15 compares the real address mode. Outputs 1'. The conditions for a TLB hit in the TLB hit determination unit 4 are: ■The V field of the TLB entry is 11'■TLB
The contents of the C field and G register 5 match, the contents of the @TLBR field and R register 8 match, and the TLB VA field and the page frame address part other than the column address in address register 9 match.

■TLB C field is 1' or TLB S
The contents of the TO field and the STO register 7 match, ■TLB The contents of the P field and the P register match.

If all of the above conditions ■ to ■ are satisfied, TLB hit 2
0 becomes 11', and if not established, TLB miss 21 becomes 1'. TLB hit 20, PA field output 22 to cache control unit (not shown), TLB miss 2
1 are respectively transferred to an address translation control unit (not shown).

As can be seen from the above condition (■), if the space to be accessed is a private space, the translation pair of the indexed TLB entry is also a translation pair of the private space.
This is a condition for B-hit.

The TLB write control unit 2 performs TLI3 by address conversion.
Controls registration and TLB invalidation.

When registering TLB, G of TLB3, 5TO1P.

The VA and R fields each have a G register 5,
STO register 7, P register 6, address register 9
, the contents of R register 8 are stored.

The values C and PA transferred from the address translation unit are stored in the C field and the PA field, respectively.

When converting a virtual address in a private space to a real address, the address conversion unit does not allow conversion in which the common segment bit becomes 11, so the P and C fields do not become 1' at the same time in the TLB entry.

Therefore, when accessing the private space (the value of P register 6 is 1'), if the indexed TLB entry is a common segment translation pair (when the C field is 1'), the corresponding P field is always 10'. Therefore, the value of the P register 6 and the P field do not match, and a TLB miss is sure to occur. Therefore, as mentioned above, the address translation control unit is notified of this, and new address translation is performed using the segment table and page table in the main memory.
The resulting conversion pair is written to the corresponding entry in TLB3. When writing this, the value of P register 6'
1' is written to the P field. From then on, the TLB
For private space access to index an entry, the value of the P register 6 and the value of the P field match, so the TLB hit condition is satisfied. As a result, even if the private space is accessed continuously, conversion by indexing the segment table and page table in main memory is not always performed, and unnecessary overhead in processing performance can be avoided. can.

If TLB3 has multiple rows, when the primer 1-space is accessed, if there is a TLB entry whose C field is 1' in the indexed column of TLI3, that I
Only the TLB entry is replaced with a new translation pair and associated field information. Alternatively, invalidate all TLB entries that fall under that column, i.e., write 101 to its V field), and then.

Write the new translation pair and the contents of each associated field to the ITLB entry. At this time, the ■ field is 1
1' P field is '1', C field is 0'
shall be. The former method has the advantage of improving TLB usage efficiency because it does not invalidate all entries in a column.

On the other hand, the latter method has the advantage that invalidation processing is easy because all entries in the same column are invalidated.

According to the present invention, when accessing a private space, even if the indexed TLB entry is a common segment translation pair, the translation pair is not used;
It becomes possible to register the P field as 1' in the LB. Conversion by indexing segment tables and page tables on main memory is only performed at the time of registration in the TLB.
It is possible to reduce conversion overhead and improve processing performance.

[Effects of the Invention] In the present invention, a private space control information field defined in the STD is provided in the TLB entry, and in TLI3 access, the content of the field is compared with the private space control information in the STD, and this match is detected as an address. Since this is set as a condition for successful conversion, even if the indexed TLB entry is a common segment conversion pair, a new conversion pair can be registered without using that entry.

Therefore, when the TLB index result when private space is accessed, the indexed conversion pair is a common segment conversion pair, and access to the private space is continuous,
Processing performance can be improved without constantly performing conversion using indexes of segment tables and page tables on the main memory, without generating unnecessary overhead in terms of processing performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, particularly a TLB and a TLB hit determination section. 1... Instruction execution section, 2... TLB write control section, 3.
... TLB, 4... TLB hit determination unit, 5... Guest register, 6... Private space control register, 7... STO register, 8... Real address mode register, 9... Address register, 1o...
・Column address decoder.

Claims (1)

[Scope of Claims] 1. In a virtual address space type data processing system having an address translation buffer that holds address translation pairs and is indexed by a part of a logical address, each entry of the address translation buffer is provided with information from a virtual address to A data processing system comprising a field for storing private space control information defined in a segment table descriptor used for conversion to a real address. 2. In a virtual address space-based data processing system having an address translation buffer that holds address translation pairs and is indexed by a portion of a logical address, each entry of the address translation buffer includes a virtual address to real address translation. A field is provided to store private space control information defined in the segment table descriptor used, and a field is defined in the segment table descriptor used to convert virtual addresses to real addresses in the address space when accessing the address space. The data processing apparatus is characterized in that the data processing apparatus comprises an address translation success determination means that compares the private space control information sent to the private space control information field with the content of the private space control information field of the address translation buffer, and sets a condition for successful address translation if the two match. system. 3. In a virtual address space type data processing system having an address translation buffer consisting of at least one row holding address translation pairs and common segment bits and indexed by a portion of a logical address, each entry of the address translation buffer In addition to providing a field to store the private space control bits defined in the segment table descriptor used for converting virtual addresses to real addresses, when accessing an address space, a field is provided to store the private space control bits defined in the segment table descriptor used to convert virtual addresses to real addresses. Compares the private space control bit defined in the segment table descriptor used for the conversion with the value of the private space control bit field of the address translation buffer, and determines whether the address translation is successful if the two match. A data processing system, comprising: a logical value '1' is not registered in the private space control bit field and the common segment bit field in the same entry of the address translation buffer at the same time. 4. In the entry indexed from the address translation buffer during private space access where the private space control bit defined in the segment table descriptor used for translation from a virtual address to a real address has a logical value of '1'. If there is an entry in which the common segment bit has a logical value of '1', registration means is provided for registering the private space access conversion pair for the entry along with the logical value '1' of the private space control bit. The data processing system according to claim 3, characterized in that: 5. Regarding a multi-row address translation buffer, when accessing a private space where the private space control bit defined in the segment table descriptor used for translation from a virtual address to a real address has a logical value of '1', the address If there is an entry whose common segment bit is logical ``1'' among the plurality of entries indexed from the conversion buffer, an invalidation means for invalidating all entries in the column to which the entry belongs; 4. The data processing system according to claim 3, further comprising registration means for registering the private space access conversion pair for the entry together with a logical value '1' of the private space control bit.