JPH0281477U - - Google Patents

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Publication number
JPH0281477U
JPH0281477U JP16140688U JP16140688U JPH0281477U JP H0281477 U JPH0281477 U JP H0281477U JP 16140688 U JP16140688 U JP 16140688U JP 16140688 U JP16140688 U JP 16140688U JP H0281477 U JPH0281477 U JP H0281477U
Authority
JP
Japan
Prior art keywords
pulse signal
hold circuit
waveform
circuit
peak
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16140688U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16140688U priority Critical patent/JPH0281477U/ja
Publication of JPH0281477U publication Critical patent/JPH0281477U/ja
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例のブロツク回路図、
第2図のa〜eは夫々第1図のa〜e部位におけ
る各信号波形図、第3図は従来のピークホールド
回路のブロツク回路図、第4図のa〜eは夫々第
3図のa〜e部位における各信号波形図である。 1……入力端子、2……検出器、3……波形整
形回路、4……タイマー回路、5……ナンド回路
、6……ホールド回路、7……パルスメータ、8
……タイマー回路。
FIG. 1 is a block circuit diagram of an embodiment of the present invention.
A to e in FIG. 2 are respective signal waveform diagrams at locations a to e in FIG. 1, FIG. 3 is a block circuit diagram of a conventional peak hold circuit, and a to e in FIG. It is each signal waveform diagram in parts a-e. 1... Input terminal, 2... Detector, 3... Waveform shaping circuit, 4... Timer circuit, 5... NAND circuit, 6... Hold circuit, 7... Pulse meter, 8
...Timer circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 検出した電源パルス信号をホールド回路におい
てピークホールドする回路において、前記電源パ
ルス信号を波形整形し、その立ち上がり部分を任
意に除去した前記波形整形信号をゲートパルス信
号として前記ホールド回路を駆動するように構成
したことを特徴とするピークホールド回路。
The circuit holds the peak of a detected power pulse signal in a hold circuit, and is configured to waveform-shape the power pulse signal and arbitrarily remove a rising portion of the waveform-shaped signal to drive the hold circuit as a gate pulse signal. A peak hold circuit characterized by:
JP16140688U 1988-12-13 1988-12-13 Pending JPH0281477U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16140688U JPH0281477U (en) 1988-12-13 1988-12-13

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16140688U JPH0281477U (en) 1988-12-13 1988-12-13

Publications (1)

Publication Number Publication Date
JPH0281477U true JPH0281477U (en) 1990-06-22

Family

ID=31444312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16140688U Pending JPH0281477U (en) 1988-12-13 1988-12-13

Country Status (1)

Country Link
JP (1) JPH0281477U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0560814A (en) * 1991-08-30 1993-03-12 Nippon Telegr & Teleph Corp <Ntt> Signal level measuring instrument

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0560814A (en) * 1991-08-30 1993-03-12 Nippon Telegr & Teleph Corp <Ntt> Signal level measuring instrument

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