JPH027472A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent different electrodes from being short-circuited by a method wherein a dug part is formed in a region opposite to a first electrode on the rear surface of an electrode sheet. CONSTITUTION:A mask is set in a part other than regions opposite to gate electrodes 6 on the rear of a cathode electrode sheet 9 composed of molybdenum; the sheet is etched down to about 200mum by using nitric acid or the like; dug parts 9a are formed. Marks are formed on the surface of the cathode electrode sheet 9 corresponding to the dug parts 9a or plane parts 9b; by referring to the marks, the plane parts and cathode electrodes 5 are pasted without dislocation. Thereby, a distance between the gate electrodes 6 and the cathode electrodes 5 amounts to 200mum or higher; the gate electrodes 6 and the cathode electrodes 5 are not short-circuited except when a metal particle or a silicon particle which can be visually detected adheres to the gate electrodes 6 or an insulating film 8. Accordingly, a process to remove the metal particle or the like by using a microscope is made unnecessary; a production process can be simplified; a yield can be enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a structure in which electrode plates are connected from above.

[Conventional technology]

Figure 2 shows a conventional gate turn-off thyristor (GTO)
FIG. In the figure, 1 is an n-base layer, and the surface of this n-base layer 1 has a p-base N2. An n emitter layer 3 is formed on the back surface.

An n emitter layer 4 is formed on the upper surface of the convex portion of the n base layer 2, and a cathode electrode 5 is formed on this n emitter layer 4, so that the cathode electrode 5 is arranged in an island shape as shown in the figure. It turns out. Further, a gate electrode 1fi 6 is formed on the bottom surface of the concave portion of the n base layer 2, and an anode electrode 7 is formed in ohmic contact with the back surface of the n emitter layer 3, and the gate electrode 6 is covered with an insulating film 8. .

Further, all of the island-shaped cathode electrodes 5 and a cathode electrode plate 9 made of a hard material are electrically connected from above.

In the GTO configured in this way, the operation of turning off the anode current flowing from the n-emitter layer 3 to the n-emitter layer 4 is to apply a negative voltage to the cathode electrode 1i5 to the gate electrode 6.
This is done by giving a current to n-base layer 2 and extracting carriers from gate electrode 6.

The ratio of the above-mentioned anode current to the gate current that extracts carriers in the n-base layer 2 from the gate electrode 6 is called turn-off gain (G). 0 usually indicates a value of O 3-5. Therefore, although the potential difference between the cathode electrode 5 and the gate electrode 6 is 15 to 30V, the anode current is 10V.
If the current is approximately 00A, a large gate current of 200 to 340A will be required to turn off the GTO.

[Problem to be solved by the invention]

The conventional GTO is configured as described above, and the insulating film 8
The cathode electrode plate 9 (cathode electrode 5) and gate electrode 6 were insulated.

However, during the manufacturing process, foreign substances such as chipped silicon particles or metal pieces from manufacturing parts may be deposited on the gate electrode 6 or insulating Il! 8. Further, a cathode electrode 5. During the vapor deposition of metal such as aluminum in vacuum when forming the gate electrode 6, large particles of the electrode material (
An insulating layer (approximately the thickness of the insulator Ill 8) is deposited on the gate electrode 6.

In such a case, metal particles or silicon particles can pierce the insulating film 8, and these particles can damage the cathode electrode plate 9.
There was a problem that the gate electrode 6 was short-circuited. Therefore,
It is necessary to detect and remove such particles by inspection using a microscope or the like, which complicates the manufacturing process. In addition, there may be cases where particles cannot be detected even with the above-mentioned tests.
The short circuit problem between the cathode electrode plate 9 and the gate electrode 6 described above cannot be avoided.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device in which different electrodes are not short-circuited.

[Means to solve the problem]

The semiconductor device according to the present invention is a semiconductor chip formed by stacking a plurality of semiconductor layers, and the top semiconductor layer forming the top layer is formed to protrude from only a part of the top surface of the semiconductor chip. By this, the top surface of the semiconductor chip has a convex portion formed by the protrusion, a concave portion corresponding to the peripheral portion of the convex portion, and a first electrode formed on the bottom surface of the four portions. , a second electrode formed on the upper surface of the convex portion, provided above the first and second electrodes, and having an extension facing both the first and second electrodes; an electrode plate fixed to a second upper surface to be electrically connected to the uppermost semiconductor layer via the second electrode; A trench that is depressed toward the upper surface of the electrode plate is provided in a region facing the electrode.

[Effect]

The electrode plate according to the present invention has a recess on the lower surface thereof in a region opposite to the first electrode region.
A relatively large space can be formed between the electrode and the electrode plate.

〔Example〕

FIG. 1 is a partial sectional view showing a GTO which is an embodiment of the present invention. Below, while referring to the same figure, 1! The J construction method will be explained.

First, p-type diffusion is performed on the front and back surfaces of an n-base layer 1, which is a silicon substrate, using gallium, boron, etc., to form an n-base layer 2 and an n-emitter layer 3.

On the surface of this n base layer 2, phosphorus is diffused over the entire surface or selectively to form an n emitter layer 4 having a thickness of about 20 μm. Next, by selectively etching a portion of the n emitter layer 4 and the n base layer 2, an island-shaped n emitter layer 4 is formed to protrude as shown in the figure. These island-shaped n emitter layers 4 are arranged in parallel at intervals of approximately 500 μm, and their width is approximately 200 μm.
It is m. Due to the protruding formation of the n-emitter layer 4, the semiconductor chip made up of the semiconductor layers 1 to 4 has a recess 10 and a projection 11 on its upper surface.

Next, an anode electrode 7 is formed on the back surface of the n-emitter layer 3 by vapor-depositing aluminum, and this anode electrode 7 is
A metal reinforcing plate (not shown) such as a molybdenum plate is attached to the back side of the plate. In addition, by depositing a metal material to a thickness of about 10 μm on the ρ base layer 2 and the entire surface of the n emitter layer 41 and partially removing it by photolithography, the cathode electrode 5 is formed on the convex portion 11 as shown in FIG. A gate electrode 6 is formed on the top surface of the wafer, and a gate electrode 6 is formed on the bottom surface of each of the four parts. This gate electrode 6 is covered with an insulating film 8 made of polyimide or the like and having a thickness of 3 μm.

Then, on the back surface of the cathode electrode plate 9 made of molybdenum, a region other than the region that should face the gate electrode 6 is masked, and etched by about 200 μm with nitric acid or the like, and the dug portion 9a is etched.
form. In addition, a mark is placed on the surface of the cathode electrode plate 9 corresponding to the dug portion 9a or the flat portion 9b, and the mark allows the flat portion 9b and the cathode electrode 5 to be bonded together without misalignment.

The cathode electrode plate 9 of the GTO manufactured in this way is the first
As shown in the figure, a grooved portion 9a is provided on the gate electrode 6, extending toward both the gate electrode 6 and the cathode electrode 5, and recessed toward the upper surface of the cathode electrode plate 9. Become. As a result, the gate electrode 6
The distance between and the cathode electrode 5 is 200μ, so
Gate electrode 6 except that visually detectable metal particles or silicon particles adhere to gate electrode 6 or insulating film 8
, there will be no short circuit between the cathode electrode plates 9.

Therefore, the step of removing metal particles and the like using a microscope is unnecessary, the manufacturing process is simplified, and the yield can be improved.

Roughly, in addition to this embodiment, by filling the space between the cathode electrode plate 9 and the gate electrode 6 by pouring or spraying an insulating material such as epoxy resin into the digging part 9a of the cathode electrode plate 9, the gate electrode 6 can be formed. It becomes possible to completely eliminate short circuits with the cathode electrode plate 9, and the insulation Il! The formation of 8 is unnecessary.

〔Effect of the invention〕

As explained above, according to the present invention, since the groove is provided in the region facing the first electrode on the lower surface of the electrode plate, there is no possibility of short-circuiting between different electrodes.

[Brief explanation of the drawing]

FIG. 1 is a partial sectional view showing a GTO which is an embodiment of the present invention, and FIG. 2 is a partial sectional view showing a conventional G and TO. In the figure, 5 is a cathode electrode, 6 is a gate electrode, 9 is a cathode electrode plate, and 9a is a trenched portion. FIG. 1 Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 2

Claims (1)

[Claims] (1) A semiconductor chip formed by stacking a plurality of semiconductor layers, in which the top semiconductor layer forming the top layer is formed to protrude from only a part of the top surface of the semiconductor chip. A semiconductor chip whose upper surface has a convex portion formed by the protrusion and a concave portion corresponding to a peripheral portion of the convex portion, a first electrode formed on the bottom surface of the concave portion, and a first electrode formed on the bottom surface of the convex portion. a second electrode formed on the upper surface; and a second electrode provided above the first and second electrodes, extending to face both the first and second electrodes, and on the second upper surface. A semiconductor device comprising: an electrode plate that is fixedly fixed to the uppermost semiconductor layer to be electrically connected to the uppermost semiconductor layer via the second electrode; a region of the lower surface of the electrode plate that faces the first electrode; A semiconductor device, further comprising a recess that is depressed toward the upper surface of the electrode plate.