JPH0244318A - Display device - Google Patents

Display device

Info

Publication number
JPH0244318A
JPH0244318A JP63194519A JP19451988A JPH0244318A JP H0244318 A JPH0244318 A JP H0244318A JP 63194519 A JP63194519 A JP 63194519A JP 19451988 A JP19451988 A JP 19451988A JP H0244318 A JPH0244318 A JP H0244318A
Authority
JP
Japan
Prior art keywords
transparent conductor
data line
drain
display
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63194519A
Other languages
Japanese (ja)
Other versions
JP2714016B2 (en
Inventor
Mitsushi Ikeda
光志 池田
Meiko Ogawa
小川 盟子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19451988A priority Critical patent/JP2714016B2/en
Publication of JPH0244318A publication Critical patent/JPH0244318A/en
Application granted granted Critical
Publication of JP2714016B2 publication Critical patent/JP2714016B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To cut down cost and to reduce wiring resistance and to increase a rate of performation by forming a data line and a drain of a transparent conductor and metallic layers laminated on it and by forming an picture element electrode and a source of a transparent conductor. CONSTITUTION:The data line and the drain of a thin film transistor TFT are formed of the transparent conductor 13 and the metallic layer 16 and 17 laminated on it, and the picture element electrode and the source of the TFT are formed of the transparent conductor 13. The wiring resistance of a data line is reduced without reducing the numerical aperture. I.e., the resistance of the data line and the drain concerning with the propagation of a signal are low because the metallic layers 16 and 17 are laminated on th transparent conductor 13. Besides, since the picture element which acts to display and the source electrode are formed on only the transparent conductor, the rate of perforation of the source part can be increased as a display electrode. Thus, the efficiency of display can be improved and the cost can be cut down.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明はアクティブマトリックス型表示装置に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to an active matrix display device.

(従来の技術) 近年、非晶質シリコン膜(以下a−8i膜と略称)を用
いた薄膜トランジスタ(以下TPTと略称)をスイッチ
ング素子として用いたアクティブマトリックス型液晶表
示装置が注目されている。これは、廉価なガラス基板が
利用できるために、大面積。
(Prior Art) In recent years, active matrix liquid crystal display devices using thin film transistors (hereinafter abbreviated as TPT) using an amorphous silicon film (hereinafter abbreviated as A-8I film) as switching elements have been attracting attention. This is due to the availability of inexpensive glass substrates, which allow for large areas.

高精細、高画質、廉価等が達成できる可能性があるから
である。
This is because there is a possibility that high definition, high image quality, low cost, etc. can be achieved.

第3図にTFTアレイを用いたデイスプレィの等何回路
を示す。この第3図において、31(3L。
FIG. 3 shows an equivalent circuit for a display using a TFT array. In this FIG. 3, 31 (3L.

31□、・・・31o)id行方向の’rFT 33の
ゲート電極を共通にドライブするアドレスライン、32
(32+。
31□,...31o) Address line 32 that commonly drives the gate electrodes of 'rFT 33 in the id row direction.
(32+.

32□、・・・32rl)はデイスプレィ信号を列方向
のTFvr 33のソースに送るデータラインである。
32□, . . . 32rl) are data lines that send display signals to the sources of the TFvr 33 in the column direction.

TFT 33はアドレスライン31とデータライン32
の各クロスポイントに対応した画素毎に用いられ、各ド
レイン電極は表示素子35と共にキャパ/り34にも接
続されている。表示素子35は例えば液晶やエレクトロ
ルミネッセンス素子である。具体的に液晶デイスプレィ
パネルを例にとると、アドレスライン31、データライ
ン32、トランジスタ33およびキャパシタ34を集積
形成した駆動回路基板と、これに対向する透明電極を全
面に形成した基板との間に液晶層を挟持することにより
構成される。このようなデイスプレィパネルはアドレス
ライン毎にデータを書き込む線順次方式で駆動され、表
示素子35をデユーティ比はぼ100チで駆動できる利
点がある。なお、上記構成でキャパシタ34は付けられ
ないこともある。
TFT 33 has address line 31 and data line 32
Each drain electrode is connected to the capacitor 34 as well as the display element 35. The display element 35 is, for example, a liquid crystal or an electroluminescent element. Taking a liquid crystal display panel as an example, there is a gap between a drive circuit board on which address lines 31, data lines 32, transistors 33, and capacitors 34 are integrated, and an opposing board on which transparent electrodes are formed on the entire surface. It is constructed by sandwiching a liquid crystal layer between the two. Such a display panel is driven by a line sequential method in which data is written for each address line, and has the advantage that the display element 35 can be driven at a duty ratio of approximately 100 inches. Note that the capacitor 34 may not be attached in the above configuration.

次に、第4図にこの種のデイスプレィの具体的な構造を
示す。第4図において、ガラス基板41の上にアドレス
線及びゲートとなる配線ノ2ターフ42を形成し、ゲー
ト絶縁膜43、a−8i44を堆積し、a−8iの島を
形成する。表示電極45を形成した後にソース461、
ドレイン電極462、データ線となる配線を形成する。
Next, FIG. 4 shows the specific structure of this type of display. In FIG. 4, a wiring no. 2 turf 42 serving as an address line and a gate is formed on a glass substrate 41, and a gate insulating film 43 and an a-8i 44 are deposited to form an a-8i island. After forming the display electrode 45, the source 461,
A drain electrode 462 and wiring to become a data line are formed.

この種のデイスプレィを大面積、高精細化すると、コス
トの増加、配線抵抗の増化及び開口率の減少の問題が生
じ製造が困難になる。コストを減少させるためには、製
作プロセスの減少、特にマスクプロセスの減少が効果的
である。例えばTF′I′のソース、ドレイン及び表示
用透明電極を同一のITOで製造することが行なわれて
いる( JapanDisplay 86 、 PD−
3)。このように7−ス(画素電極側)を透明電極にす
ることは開口率を増大させるのに効果的である。しかし
、ITOは抵抗率が数mΩ釧と金属の10〜100αよ
り1桁以上大きい。このため対角10インチの表示装置
では巾20μm、2m、Qm、厚さ2000A、長さ2
0薗の配線では配線抵抗がIMΩと大きいためパルスの
伝播遅延が4m5ec と大きくこれは書き込み時間3
0μ冠に比較して非常に大きく駆動が不可能である。
If this type of display is made to have a large area and high definition, there will be problems such as an increase in cost, an increase in wiring resistance, and a decrease in aperture ratio, making manufacturing difficult. In order to reduce costs, it is effective to reduce the manufacturing process, especially the mask process. For example, the source, drain, and display transparent electrode of TF'I' are manufactured from the same ITO (Japan Display 86, PD-
3). Making the 7-space (pixel electrode side) a transparent electrode in this way is effective in increasing the aperture ratio. However, ITO has a resistivity of several mΩ, which is more than an order of magnitude higher than that of metal, which has a resistivity of 10 to 100α. Therefore, for a display device with a diagonal of 10 inches, the width is 20 μm, 2 m, Qm, the thickness is 2000 A, and the length is 2
In the case of 0-son wiring, the wiring resistance is as large as IMΩ, so the pulse propagation delay is 4m5ec, which is the write time of 3
It is very large compared to a 0μ crown and cannot be driven.

(本発明が解決しようとする課題) 上述のごとく、従来の逆スタツガ型のTPTを用いた表
示装置用基板では、コストの増加、配線抵抗の増加及び
開口率の減少の問題を同時に解決することは困難であっ
た。本発明は上記の問題を同時に解決することを目的と
する。
(Problems to be Solved by the Present Invention) As described above, it is necessary to simultaneously solve the problems of increased cost, increased wiring resistance, and decreased aperture ratio in a display device substrate using a conventional inverted staggered TPT. was difficult. The present invention aims to simultaneously solve the above problems.

〔発明の構成〕[Structure of the invention]

(課題を解決するための手段) 本発明は、絶縁性基板上に形成された複数のアドレス配
線と、このアドレス配線に絶縁的に交差部を形成する複
数のデータ線と、これら交差部近傍に配置された画素電
極と、前記交差部に隣接して配置されており、前記アド
レス線に電気的接続きれたゲート、前記データ線に電気
的接続されたドレイン、前記画素電極に電気的接続され
たソースとからなる薄膜トランジスタとを具備した表示
装置において、前記データ線及びドレインは透明導体と
その上に積層された金属層により形成され、前記画素電
極及びソースが透明導体により形成されていることを特
徴とする表示装置である。
(Means for Solving the Problems) The present invention provides a plurality of address wirings formed on an insulating substrate, a plurality of data lines forming insulating intersections with the address wirings, and a plurality of data lines in the vicinity of these intersections. a gate located adjacent to the intersection and electrically connected to the address line, a drain electrically connected to the data line, and a drain electrically connected to the pixel electrode. In the display device, the data line and the drain are formed of a transparent conductor and a metal layer laminated thereon, and the pixel electrode and the source are formed of a transparent conductor. This is a display device.

(作用) 本発明は、データ線及びTPTのドレインを透明導体と
その上に積層された金属層により形成し、画素電極及び
TF′Tのソースを透明導体により形成し、開口率を減
少させずにデータラインの配線抵抗を減少させることが
できる。すなわち、信号の伝播に関係するデータ線及び
ドレイ/は透明導体上に金属(好ましくは低抵抗金属)
層が積層されているため、データライン抵抗が低く、表
示作用のある画素電極及びソース電極を透明導体のみで
形成するため、ソースの部分まで表示電極として開口率
を上けることができる。
(Function) In the present invention, the data line and the TPT drain are formed from a transparent conductor and a metal layer laminated thereon, and the pixel electrode and the TF'T source are formed from a transparent conductor, without reducing the aperture ratio. The wiring resistance of data lines can be reduced. That is, data lines and drains related to signal propagation are metal (preferably low resistance metal) on transparent conductors.
Since the layers are laminated, the data line resistance is low, and since the pixel electrode and source electrode, which have a display function, are formed only from transparent conductors, it is possible to increase the aperture ratio up to the source portion as a display electrode.

また、本発明ではデータ線及びドレインの金属層をメッ
キ法により形成すれば、製造プロセスを簡素化すること
ができる。
Furthermore, in the present invention, the manufacturing process can be simplified by forming the data line and drain metal layers by plating.

(実施例) 以下、本発明の第1の実施例を第1図を用いて説明する
。ガラス基板1工の上にTa12を2000^スパツタ
し、CF4と02を用いたプラズマエツチングによりテ
ーバエツチングを行ないゲート電極をパターン形成した
。次に、プラズマC’ V D法により5iOx13を
2oooX、アンド−プロ−8i14を3000AX 
n a−8i15  を50OA堆積した。M) 15
  を50OA堆積した後にパターニングしてa−8i
の島を形成した。次にコンタクトホールを開口した後に
、ITO膜16を200OA。
(Example) Hereinafter, a first example of the present invention will be described using FIG. 1. 2000^ of Ta12 was sputtered onto a glass substrate, and a gate electrode was patterned by plasma etching using CF4 and 02. Next, by plasma C' V D method, 5iOx13 was 2oooX, and-pro-8i14 was 3000AX
50OA of na-8i15 was deposited. M) 15
After depositing 50OA of
formed an island. Next, after opening a contact hole, the ITO film 16 was deposited at a thickness of 200 OA.

Ni17を500Xを堆積し、Ni/ITOをエツチン
グして、データ線及びソース、ドレイン及び画素電極を
形成した。次にデータ線の端に電気的接触を取り、ワッ
ト浴中でデータ線及びドレインのみにCL118を1μ
mメッキ形成した。次に、HCtによりノース及び画素
電極上のNiをエツチングし、除去した。
Ni17 was deposited at 500X and Ni/ITO was etched to form data lines, source, drain, and pixel electrodes. Next, make electrical contact to the end of the data line and add 1μ of CL118 to the data line and drain only in a Watts bath.
M plating was formed. Next, Ni on the north and pixel electrodes was etched and removed using HCt.

次に、CDEによりチャネル部のna−8iをエツチン
グして、TFTアレイを完成させた。次に5iNx19
  をプラズマC’VDにより堆積してバンベー7ヨン
を行なった。コンタクト部の5iNxlQをエツチング
除去した後に、ポリイミド20を5ooX形成した後に
ラビング配向を行なった。
Next, the na-8i in the channel portion was etched by CDE to complete the TFT array. Next 5iNx19
was deposited by plasma C'VD, and then subjected to a deposition process. After removing the 5iNxlQ in the contact portion by etching, a 5ooX polyimide 20 was formed, and then rubbing orientation was performed.

同様にポリイミド配向21を行なった対向基板22を接
着して、TN液晶23を封入して液晶デイスプレィを形
成した。
A counter substrate 22 on which polyimide orientation 21 was similarly applied was adhered, and a TN liquid crystal 23 was sealed to form a liquid crystal display.

このようなアドレス線を形成することによりライン抵抗
は、IMΩから1にΩと大きく減少できた。又、このよ
うなメッキプロセスを用いることにより、データ線と画
素電極を同一のマスクで形成できるためマスク数を1枚
減少することができた。又、ソース部の電極を除去する
ことにより、画素の開口率を大きくできた。
By forming such an address line, the line resistance could be greatly reduced from IMΩ to 1Ω. Further, by using such a plating process, the data line and the pixel electrode can be formed using the same mask, so the number of masks can be reduced by one. Furthermore, by removing the electrode in the source section, the aperture ratio of the pixel could be increased.

次に、第2図に別の実施例を示す。ガラス基板11の上
に実施例1と同様にa−8iO島及びコンタクトホール
を形成する。次に、■TO膜16、Cv27を500 
AXAl、28を500OA堆積し、A L / Cv
 / I T Oをエツチングして、データ線及びソー
ス、ドレイン及び画素電極を形成した。次にパターニン
グによりソース及び画素電極上のkl/CV をエツチ
ング除去した。
Next, FIG. 2 shows another embodiment. A-8iO islands and contact holes are formed on the glass substrate 11 in the same manner as in Example 1. Next, ■ TO film 16, Cv27
Deposit 500OA of AXAl, 28, AL/Cv
/ITO was etched to form data lines, source, drain, and pixel electrodes. Next, kl/CV on the source and pixel electrodes was etched away by patterning.

次に、実施例1と同様にして液晶デイスプレィを形成し
た。
Next, a liquid crystal display was formed in the same manner as in Example 1.

このようなアドレス線を形成することにより、ライ/抵
抗はIMΩから2にΩと大きく減少できた。又、第1の
実施例と同様にドレイン部の電囁を除去することにより
画面の開口率を大きくできた。
By forming such an address line, the lie/resistance could be greatly reduced from IMΩ to 2Ω. Further, as in the first embodiment, the aperture ratio of the screen can be increased by removing the electric whisper in the drain section.

データライン上層の金属はAt、Cuに限らすλu 、
 A g等の低抵抗金属でも良い。ITO上の中間金属
はCv、Niに限らず、密着性の良い金属ならば何でも
良い。
The metal on the upper layer of the data line is limited to At and Cu.λu,
A low resistance metal such as Ag may also be used. The intermediate metal on the ITO is not limited to Cv or Ni, but any metal with good adhesion may be used.

又、デイスプレィは本実施例のような、白黒形に限らず
、カラーフィルターを装置したカラーデイスプレィでも
同様の効果が得られる。
Further, the display is not limited to a black and white type as in this embodiment, but the same effect can be obtained with a color display equipped with a color filter.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、開口率を増加して、且つ配設抵抗が減
少でき、又マスクプロセスを減少することができ、デイ
スプレィの性能向上及びコストの低減が実現できる。
According to the present invention, the aperture ratio can be increased, the arrangement resistance can be reduced, and the number of mask processes can be reduced, thereby improving display performance and reducing costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明の一実施例の表示装置の概略
図、第3図はアクティブマトリックス型デイスプレィの
等価回路図、第4図は従来の表示装置の概略図を示す。 11・・・ガラス基板、12・・・ゲート及びアドレス
電極、13・・・a−si、14・・・ゲート絶縁膜、
15 ・=Mo/n  a−8i    1 6 ・=
 I T Ol 17 ・−Ni。
1 and 2 are schematic diagrams of a display device according to an embodiment of the present invention, FIG. 3 is an equivalent circuit diagram of an active matrix type display, and FIG. 4 is a schematic diagram of a conventional display device. DESCRIPTION OF SYMBOLS 11...Glass substrate, 12...Gate and address electrode, 13...A-SI, 14...Gate insulating film,
15 ・=Mo/na-8i 1 6 ・=
I T Ol 17 ·-Ni.

Claims (2)

【特許請求の範囲】[Claims] (1)絶縁性基板上に形成された複数のアドレス配線と
、このアドレス配線に絶縁的に交差部を形成する複数の
データ線と、これら交差部近傍に配置された画素電極と
、前記交差部に隣接して配置されており、前記アドレス
線に電気的接続されたゲート、前記データ線に電気的接
続されたドレイン、前記画素電極に電気的接続されたソ
ースとからなる薄膜トランジスタとを具備した表示装置
において、前記データ線及びドレインは透明導体とその
上に積層された金属層により形成され、前記画素電極及
びソースが透明導体により形成されていることを特徴と
する表示装置。
(1) A plurality of address wirings formed on an insulating substrate, a plurality of data lines forming intersections with the address wirings insulatively, pixel electrodes arranged near these intersections, and the intersections. a display comprising a thin film transistor disposed adjacent to the address line, the thin film transistor having a gate electrically connected to the address line, a drain electrically connected to the data line, and a source electrically connected to the pixel electrode. A display device characterized in that the data line and the drain are formed of a transparent conductor and a metal layer laminated thereon, and the pixel electrode and the source are formed of a transparent conductor.
(2)前記データ線及びドレインの金属層がメッキ法に
より形成されていることを特徴とする表示装置。
(2) A display device characterized in that the data line and drain metal layers are formed by a plating method.
JP19451988A 1988-08-05 1988-08-05 Display device Expired - Fee Related JP2714016B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19451988A JP2714016B2 (en) 1988-08-05 1988-08-05 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19451988A JP2714016B2 (en) 1988-08-05 1988-08-05 Display device

Publications (2)

Publication Number Publication Date
JPH0244318A true JPH0244318A (en) 1990-02-14
JP2714016B2 JP2714016B2 (en) 1998-02-16

Family

ID=16325884

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19451988A Expired - Fee Related JP2714016B2 (en) 1988-08-05 1988-08-05 Display device

Country Status (1)

Country Link
JP (1) JP2714016B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06194688A (en) * 1992-10-09 1994-07-15 Fujitsu Ltd Thin-film transistor matrix device and its production
US5751381A (en) * 1993-12-21 1998-05-12 Hitachi, Ltd. Active matrix LCD device with image signal lines having a multilayered structure
JP2001044439A (en) * 1999-07-28 2001-02-16 Nec Corp Transistor and manufacture thereof
JP2002303877A (en) * 2001-01-18 2002-10-18 Lg Phillips Lcd Co Ltd Array substrate for liquid crystal display device and method for manufacturing it
JP2004519009A (en) * 2001-02-03 2004-06-24 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Method for improving the conductivity of transparent conductor lines
JP2015135973A (en) * 2009-10-14 2015-07-27 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP2015159290A (en) * 2009-07-18 2015-09-03 株式会社半導体エネルギー研究所 display device
JP2015173265A (en) * 2009-08-07 2015-10-01 株式会社半導体エネルギー研究所 semiconductor device
JP2019050394A (en) * 2018-10-31 2019-03-28 株式会社半導体エネルギー研究所 Semiconductor device and electronic apparatus
US10665610B2 (en) 2000-12-11 2020-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and manufacturing method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61179486A (en) * 1985-02-04 1986-08-12 三菱電機株式会社 Conductor device
JPS62288883A (en) * 1986-06-09 1987-12-15 アルプス電気株式会社 Manufacture of thin film transistor
JPS63221324A (en) * 1987-03-11 1988-09-14 Hitachi Ltd Liquid crystal display device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61179486A (en) * 1985-02-04 1986-08-12 三菱電機株式会社 Conductor device
JPS62288883A (en) * 1986-06-09 1987-12-15 アルプス電気株式会社 Manufacture of thin film transistor
JPS63221324A (en) * 1987-03-11 1988-09-14 Hitachi Ltd Liquid crystal display device

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06194688A (en) * 1992-10-09 1994-07-15 Fujitsu Ltd Thin-film transistor matrix device and its production
US5751381A (en) * 1993-12-21 1998-05-12 Hitachi, Ltd. Active matrix LCD device with image signal lines having a multilayered structure
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